[go: up one dir, main page]

CN100474581C - Bridging type multi-chip packaging structure - Google Patents

Bridging type multi-chip packaging structure Download PDF

Info

Publication number
CN100474581C
CN100474581C CNB031562701A CN03156270A CN100474581C CN 100474581 C CN100474581 C CN 100474581C CN B031562701 A CNB031562701 A CN B031562701A CN 03156270 A CN03156270 A CN 03156270A CN 100474581 C CN100474581 C CN 100474581C
Authority
CN
China
Prior art keywords
chip
bridged
style
package structure
multichip package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB031562701A
Other languages
Chinese (zh)
Other versions
CN1591862A (en
Inventor
洪志斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CNB031562701A priority Critical patent/CN100474581C/en
Publication of CN1591862A publication Critical patent/CN1591862A/en
Application granted granted Critical
Publication of CN100474581C publication Critical patent/CN100474581C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A bridge type multi-chip package mainly comprises a carrier, a first chip, a second chip and at least one conductive bump. The carrier has an upper surface and a corresponding lower surface, and a plurality of carrier contacts are located on the upper surface of the carrier. The first chip has a first active surface, and the first chip further has at least one first contact disposed on the first active surface of the first chip. Similarly, the second chip has a second active surface, and the second chip further has at least one second contact disposed on the second active surface of the second chip. The first side wall of the first chip is closely adjacent to the second side wall of the second chip, and the first active surface of the first chip and the second active surface of the second chip are in a coplanar configuration. The conductive bump extends on the first active surface of the first chip and the second active surface of the second chip, so that the first contact of the first chip is electrically connected with the second contact of the second chip.

Description

桥接形式的多芯片封装构造 Multi-chip package structure in the form of a bridge

技术领域 technical field

本发明涉及一种多芯片封装构造，特别涉及一种桥接形式的多芯片封装构造。The invention relates to a multi-chip packaging structure, in particular to a bridge-type multi-chip packaging structure.

背景技术 Background technique

近年来，随着电子技术的日新月异，高科技电子产品也相继问世，因而更人性化、功能性更佳的电子产品不断推陈出新，然而各种产品无不朝向轻、薄、短、小的趋势设计，以提供更便利舒适的使用。而一个电子产品的完成，电子封装扮演着重要的角色，其芯片间电性连接的方式，一般常见的有两种，第一种为引线键合(wire-bonding)的方式、第二种为倒装芯片(flip chip)的方式。就引线键合的方式而言，其利用一引线键合机台将其引线键合头先移动至芯片的接点上，并利用尖端放电的方式将导电线的端点熔化而成为球型的样式，如此便可以将导电线打到芯片的接点上，然后便移动引线键合头到另一芯片的接点上，而在移动的过程中，引线键合头亦会放出导电线，最后再利用超音波熔接的方式将导电线打到另一芯片的接点上。In recent years, with the rapid development of electronic technology, high-tech electronic products have also come out one after another, so more humanized and functional electronic products are constantly being introduced. However, all kinds of products are designed towards the trend of light, thin, short and small. To provide more convenient and comfortable use. In the completion of an electronic product, electronic packaging plays an important role. There are generally two ways of electrical connection between chips. The first is wire-bonding, and the second is wire-bonding. Flip chip (flip chip) way. As far as the wire bonding method is concerned, it uses a wire bonding machine to move its wire bonding head to the contact point of the chip first, and uses tip discharge to melt the ends of the conductive wires into a spherical shape. In this way, the conductive wire can be hit on the contact of the chip, and then the wire bonding head is moved to the contact of another chip. During the movement, the wire bonding head will also release the conductive wire, and finally the ultrasonic wave is used to The way of welding is to hit the conductive wire to the contact of another chip.

接下来，将介绍一种已知利用引线键合方式的多芯片封装结构。请参照图1，其图示已知利用引线键合方式的多芯片封装结构的剖面示意图。该封装结构包括一载板10、一第一芯片12、一第二芯片14、多条导电线160、162、164、一封装材料18及多个焊球19。载板10具有一上表面102及对应的下表面104，而载板10具有多个载板接点106及第一芯片座105与第二芯片座109，载板接点106及第一芯片座105与第二芯片座109位在载板10的上表面102上，并且载板接点106环绕在第一芯片座105与第二芯片座109的周围，而载板接点107位在载板10的下表面104上。第一芯片12具有一主动表面122及对应的第一背面124，而第一芯片12还具有多个第一芯片接点126，位在第一芯片12的主动表面122上。第一芯片12以其第一背面124并通过一黏着材料(未标示于图中)贴附到载板10的芯片座108上，而利用引线键合的方式使第一芯片12与载板10电性连接，其中导电线160的一端接合到第一芯片接点126上，而导电线160的另一端接合到载板接点106上。同样地，第二芯片14具有一第二主动表面142及对应的第二背面144，而第二芯片14还具有多个第二芯片接点146，位在第二芯片14的第二主动表面142上。第二芯片14以其第二背面144并通过一黏着材料(未标示于图中)贴附到载板10的芯片座109上，而利用引线键合的方式使第二芯片14与载板10电性连接，其中导电线162的一端接合到第二芯片接点146上，而导电线162的另一端接合到载板接点108上。此外，第一芯片12与第二芯片14通过导电线164电性导通。另外，封装材料18包覆第一芯片12、第二芯片14、载板10的上表面102及导电线160、162及164。Next, a known multi-chip package structure using wire bonding will be introduced. Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional multi-chip package structure utilizing wire bonding. The packaging structure includes a carrier board 10 , a first chip 12 , a second chip 14 , a plurality of conductive wires 160 , 162 , 164 , a packaging material 18 and a plurality of solder balls 19 . The carrier 10 has an upper surface 102 and a corresponding lower surface 104, and the carrier 10 has a plurality of carrier contacts 106 and a first chip holder 105 and a second chip holder 109, the carrier contact 106 and the first chip holder 105 and The second chip holder 109 is located on the upper surface 102 of the carrier 10 , and the carrier contacts 106 surround the first chip holder 105 and the second chip holder 109 , and the carrier contacts 107 are located on the lower surface of the carrier 10 104 on. The first chip 12 has an active surface 122 and a corresponding first back surface 124 , and the first chip 12 also has a plurality of first chip contacts 126 located on the active surface 122 of the first chip 12 . The first chip 12 is attached to the chip seat 108 of the carrier 10 with its first back surface 124 and through an adhesive material (not shown in the figure), and the first chip 12 is connected to the carrier 10 by wire bonding. Electrical connection, wherein one end of the conductive wire 160 is bonded to the first chip contact 126 , and the other end of the conductive wire 160 is bonded to the carrier contact 106 . Similarly, the second chip 14 has a second active surface 142 and a corresponding second back surface 144, and the second chip 14 also has a plurality of second chip contacts 146 on the second active surface 142 of the second chip 14. . The second chip 14 is attached to the chip seat 109 of the carrier 10 with its second back surface 144 and through an adhesive material (not shown in the figure), and the second chip 14 is connected to the carrier 10 by wire bonding. Electrical connection, wherein one end of the conductive wire 162 is bonded to the second chip contact 146 , and the other end of the conductive wire 162 is bonded to the carrier contact 108 . In addition, the first chip 12 and the second chip 14 are electrically connected through the conductive wire 164 . In addition, the packaging material 18 covers the first chip 12 , the second chip 14 , the upper surface 102 of the carrier 10 and the conductive wires 160 , 162 and 164 .

在上述的封装结构中，第一芯片12通过导线164与第二芯片14电性连接，然而由于导线164的截面积甚小并且长度甚长，因此特性阻抗匹配不良，使得讯号会被快速地衰减，并且在高频电路运作时，会有电感电容寄生效应(Parasitics)的发生，以致产生讯号反射的情形。此外，由于导线164与第一芯片接点传输路径的面积甚小，不利于电压及电流提供，导致电源及接地的效果变差。In the above-mentioned packaging structure, the first chip 12 is electrically connected to the second chip 14 through the wire 164. However, because the cross-sectional area of the wire 164 is very small and the length is very long, the characteristic impedance matching is poor, so that the signal will be rapidly attenuated. , and when the high-frequency circuit is operating, there will be parasitic effects (Parasitics) of the inductance and capacitance, resulting in signal reflection. In addition, due to the very small area of the transmission path between the wire 164 and the contact of the first chip, it is not conducive to supplying voltage and current, resulting in poor effects of power supply and grounding.

有鉴于此，为避免前述多芯片封装构造的缺点，以提升多芯片封装构造的芯片效能，实为一重要的课题。In view of this, in order to avoid the aforementioned disadvantages of the multi-chip packaging structure, it is an important issue to improve the chip performance of the multi-chip packaging structure.

发明内容 Contents of the invention

有鉴于上述课题，本发明的目的提供一种多芯片封装结构，以桥接型式的导电材料取代导电线，如此可缩短芯片间电性连接的距离，使得多芯片封装结构的电性效能可以提高。In view of the above problems, the purpose of the present invention is to provide a multi-chip packaging structure, which replaces conductive wires with bridge-type conductive materials, so that the distance between the chips can be shortened and the electrical performance of the multi-chip packaging structure can be improved.

由此，为了达成上述目的，本发明提出一种芯片封装结构，至少包括一载板、一第一芯片、一第二芯片及至少一导电凸块及多个焊球。载板具有一上表面及对应的下表面，载板还具至少一载板接点，均位在载板的上表面。第一芯片具有一第一主动表面，第一芯片还具有至少一第一芯片接点，配置在第一芯片的第一主动表面上。同样地，第二芯片具有一第二主动表面，第二芯片还具有至少一第二芯片接点，配置在第二芯片的第二主动表面上。其中，第一芯片及第二芯片以引线键合方式配置于载板上，并与载板电性连接。此外，第一芯片的至少一第一侧壁紧邻第二芯片的第二侧壁，并且第一芯片的第一主动表面与第二芯片的第二主动表面为共平面的配置。导电凸块在第一芯片的第一主动表面上及第二芯片的第二表面上延伸，使第一芯片的第一接点与第二芯片的第二接点电性连接。Therefore, in order to achieve the above object, the present invention proposes a chip packaging structure, which at least includes a carrier board, a first chip, a second chip, at least one conductive bump and a plurality of solder balls. The carrier board has an upper surface and a corresponding lower surface, and the carrier board also has at least one carrier board contact, all of which are located on the upper surface of the carrier board. The first chip has a first active surface, and the first chip also has at least one first chip contact configured on the first active surface of the first chip. Likewise, the second chip has a second active surface, and the second chip also has at least one second chip contact configured on the second active surface of the second chip. Wherein, the first chip and the second chip are arranged on the carrier board by wire bonding, and are electrically connected with the carrier board. In addition, at least one first sidewall of the first chip is adjacent to the second sidewall of the second chip, and the first active surface of the first chip and the second active surface of the second chip are coplanar. The conductive bump extends on the first active surface of the first chip and the second surface of the second chip, so as to electrically connect the first contact of the first chip to the second contact of the second chip.

承上所述，其中芯片封装结构还包括一封装材料，包覆第一芯片及第二芯片、载板的上表面及导电凸块。第一芯片接点及第二芯片接点分别位在第一芯片及第二芯片的边缘上，且紧邻配置。此外，导电凸块可以是锡铅合金、无铅导电材料或导电胶。Based on the above, the chip packaging structure further includes a packaging material covering the first chip and the second chip, the upper surface of the carrier board and the conductive bump. The first chip contact and the second chip contact are located on the edge of the first chip and the second chip respectively, and are arranged adjacent to each other. In addition, the conductive bump can be tin-lead alloy, lead-free conductive material or conductive glue.

综上所述，本发明的多芯片封装结构，由于芯片间的接点可以透过导电凸块电性连接，因此芯片接点间的传导路径甚短，且传导路径的径宽甚大，故可以降低传导阻抗，而减缓讯号的衰减，并且可以适于在高频电路的运作，而减少电感电容寄生效应的发生。另外，由于导电凸块与芯片接点接触的面积甚大，且载板接点可以直接与芯片接点接触，故可以避免发生如引线键合结构的阻抗不匹配的现象，并且会有甚佳的电源及接地效果。To sum up, in the multi-chip packaging structure of the present invention, since the contacts between the chips can be electrically connected through conductive bumps, the conduction path between the chip contacts is very short, and the diameter of the conduction path is very wide, so the conduction can be reduced. Impedance, so as to slow down the attenuation of the signal, and can be suitable for operation in high-frequency circuits, so as to reduce the occurrence of parasitic effects of inductance and capacitance. In addition, since the contact area between the conductive bump and the chip contact is very large, and the carrier board contact can directly contact the chip contact, it can avoid the phenomenon of impedance mismatch such as the wire bonding structure, and there will be excellent power supply and grounding Effect.

以下将参照相关附图，说明依本发明较佳实施例的桥接形式的多芯片封装构造。The bridging-type multi-chip package structure according to a preferred embodiment of the present invention will be described below with reference to related drawings.

附图说明 Description of drawings

图1为一示意图，显示已知多芯片封装构造。FIG. 1 is a schematic diagram showing a conventional multi-chip package structure.

图2为一示意图，显示本发明第一较佳实施例中的桥接形式的多芯片封装结构。FIG. 2 is a schematic diagram showing the multi-chip packaging structure in bridge form in the first preferred embodiment of the present invention.

图3为一示意图，显示本发明第二较佳实施例中的桥接形式的多芯片封装结构。FIG. 3 is a schematic diagram showing a bridge-type multi-chip packaging structure in a second preferred embodiment of the present invention.

图4为一示意图，显示本发明第三较佳实施例中的桥接形式的多芯片封装结构。FIG. 4 is a schematic diagram showing a bridge-type multi-chip package structure in a third preferred embodiment of the present invention.

图5为一示意图，显示本发明第四较佳实施例中的桥接形式的多芯片封装结构。FIG. 5 is a schematic diagram showing a bridge-type multi-chip package structure in a fourth preferred embodiment of the present invention.

图6为一示意图，显示本发明第五较佳实施例中的桥接形式的多芯片封装结构。FIG. 6 is a schematic diagram showing a bridge-type multi-chip package structure in a fifth preferred embodiment of the present invention.

图7至图9为一示意图，显示本发明第四较佳实施例的一种桥接形式的多芯片封装结构制程的剖面示意图。7 to 9 are schematic diagrams showing a cross-sectional view of a bridge-type multi-chip packaging structure manufacturing process according to a fourth preferred embodiment of the present invention.

图中符号说明Explanation of symbols in the figure

10        载板10 carrier board

102       载板上表面102 The upper surface of the carrier board

104       载板下表面104 Lower surface of carrier board

105       第一芯片座105 The first chip seat

106、108  载板接点106, 108 carrier board contacts

107       导电组件(焊球)107 Conductive components (solder balls)

109       第二芯片座109 Second chip seat

12        第一芯片12 first chip

122       第一主动面122 The first active surface

124       第一背面124 first back

126       第一芯片接点126 first chip contacts

14        第二芯片14 second chip

142       第二主动表面142 second active surface

144       第二背面144 second back

146       第二芯片接点146 Second chip contacts

160、162、164  导电线160, 162, 164 Conductive wire

18             封胶体18 Sealant

20             载板20 carrier board

201            开口201 opening

202            载板上表面202 The upper surface of the carrier board

203            周壁203 Perimeter wall

204            载板下表面204 Lower surface of carrier board

206、208       载板接点206, 208 carrier board contacts

207            导电组件(焊球)207 Conductive components (solder balls)

21             散热片21 heat sink

22             第一芯片22 The first chip

221            第一侧壁221 first side wall

222            第一主动面222 The first active surface

223            第三侧壁223 third side wall

224            第一背面224 The first back

226、228       第一芯片接点226, 228 The first chip contact

24             第二芯片24 second chip

241            第二侧壁241 Second side wall

242            第二主动表面242 Second active surface

243            第四侧壁243 Fourth side wall

244            第二背面244 second back

246、248       第二芯片接点246, 248 Second chip contacts

254            屏蔽层254 shielding layer

256            开口256 opening

258            焊料258 Solder

259            导电凸块259 Conductive bumps

260、262       导电线260, 262 Conductive wire

264            导电凸块264 Conductive bumps

268            导电凸块268 Conductive bumps

28             封胶体28 Sealant

29           填充体29 filler

292          填充体上表面292 Upper surface of filling body

具体实施方式 Detailed ways

图2揭示一种本发明第一较佳实施例的桥接形式的多芯片封装构造，其主要包括一载板20、一第一芯片22、一第二芯片24及一导电凸块264。该载板20具有一上表面202及对应的一下表面204，多个载板接点206、208，均位在载板20的上表面。第一芯片22具有一第一主动表面222，该第一芯片22还具有至少一第一接点226，配置在第一芯片22的第一主动表面222上。同样地，第二芯片24具有一第二主动表面242，该第二芯片24还具有至少一第二接点246，配置在第二芯片24的第二主动表面242上。其中，第一芯片22以其背面(第一背面224)并通过一黏着材料(如银胶)设置于载板20上；同样地，第二芯片24以其背面(第二背面224)并通过一黏着材料(如银胶)设置于载板20上。导电线260电性连接第一芯片22的第一接点226与载板20的载板接点206，而导电线262电性连接第二芯片24的第二接点246与载板20的载板接点208。FIG. 2 discloses a bridge multi-chip package structure according to the first preferred embodiment of the present invention, which mainly includes a carrier 20 , a first chip 22 , a second chip 24 and a conductive bump 264 . The carrier board 20 has an upper surface 202 and a corresponding lower surface 204 , and a plurality of carrier board contacts 206 , 208 are located on the upper surface of the carrier board 20 . The first chip 22 has a first active surface 222 , and the first chip 22 also has at least one first contact 226 disposed on the first active surface 222 of the first chip 22 . Likewise, the second chip 24 has a second active surface 242 , and the second chip 24 also has at least one second contact 246 disposed on the second active surface 242 of the second chip 24 . Wherein, the first chip 22 is arranged on the carrier 20 with its back side (the first back side 224) and through an adhesive material (such as silver glue); An adhesive material (such as silver glue) is disposed on the carrier board 20 . The conductive wire 260 electrically connects the first contact 226 of the first chip 22 to the carrier contact 206 of the carrier 20 , and the conductive wire 262 electrically connects the second contact 246 of the second chip 24 to the carrier contact 208 of the carrier 20 .

此外，第一芯片22的第一侧壁221紧邻第二芯片24的第二侧壁241，且第一芯片22的第一主动表面222与第二芯片24的第二主动表面242为共平面的配置，再者，第一芯片接点226及第二芯片接点246分别位在第一芯片22及第二芯片24的边缘上，且紧邻配置。导电凸块264在第一芯片22的第一主动表面222上及第二芯片24的第二主动表面242上延伸，使第一芯片22的第一接点228与第二芯片24的第二接点248电性连接。承上所述，该多芯片封装结构还包括一封装材料280，包覆第一芯片22及第二芯片24、载板20的上表面202及导电凸块264。此外，上述的导电凸块264可以是锡铅合金、无铅导电材料或导电胶。In addition, the first sidewall 221 of the first chip 22 is adjacent to the second sidewall 241 of the second chip 24, and the first active surface 222 of the first chip 22 is coplanar with the second active surface 242 of the second chip 24. configuration, moreover, the first chip contact 226 and the second chip contact 246 are located on the edge of the first chip 22 and the second chip 24 respectively, and are arranged adjacent to each other. The conductive bump 264 extends on the first active surface 222 of the first chip 22 and on the second active surface 242 of the second chip 24, so that the first contact 228 of the first chip 22 is connected to the second contact 248 of the second chip 24 electrical connection. Based on the above, the multi-chip packaging structure further includes a packaging material 280 covering the first chip 22 and the second chip 24 , the upper surface 202 of the carrier 20 and the conductive bump 264 . In addition, the above-mentioned conductive bump 264 may be tin-lead alloy, lead-free conductive material or conductive glue.

如图3所示，本发明的第二较佳实施例的桥接形式的多芯片封装构造，当第一芯片22的第一侧边221与第二芯片24的第二侧边241间具有一较大的空隙时，可先设置一填充体29，如不导电胶体。该填充体29的上表面与第一芯片22的第一主动表面222及第二芯片24的第二主动表面242共平面。接着，可以利用网板印刷的方式，形成一焊料到第一芯片接点226、第二芯片接点246及填充体的上表面292上，其中焊料由一助焊剂(未绘示)及多个金属粒子(未绘示)所构成，金属粒子均匀地混合在助焊剂中。之后，便进行回焊的制程，使得金属粒子可以熔融聚合而固化形成导电凸块264到第一芯片接点226及第二芯片接点246上。其中第一芯片接点226及第二芯片接点246可通过导电凸块264相互电性连接，而导电凸块264比如是锡铅合金或是无铅导电材料。As shown in FIG. 3 , in the multi-chip packaging structure of the bridge form in the second preferred embodiment of the present invention, when there is a relatively small distance between the first side 221 of the first chip 22 and the second side 241 of the second chip 24 When the gap is large, a filling body 29 can be provided first, such as non-conductive colloid. The top surface of the filler 29 is coplanar with the first active surface 222 of the first chip 22 and the second active surface 242 of the second chip 24 . Then, a solder can be formed on the first chip contact 226, the second chip contact 246 and the upper surface 292 of the filler by screen printing, wherein the solder is composed of a flux (not shown) and a plurality of metal particles ( not shown), the metal particles are evenly mixed in the flux. Afterwards, a reflow process is performed, so that the metal particles can be melted and polymerized to be solidified to form conductive bumps 264 on the first chip contacts 226 and the second chip contacts 246 . The first chip contact 226 and the second chip contact 246 can be electrically connected to each other through the conductive bump 264, and the conductive bump 264 is, for example, tin-lead alloy or lead-free conductive material.

接着，请参照图4，为本发明的第三较佳实施例的桥接形式的多芯片封装构造。其中，载板20具有一开口201，第一芯片22及第二芯片24容置于该开口201中，而封胶体28包覆该载板20上表面202的部分、第一芯片22、第二芯片24及导电凸块264，并且使第一芯片22及第二芯片24的背面外露的，以通过此进一步缩小整体封装构造的厚度。Next, please refer to FIG. 4 , which shows a bridge-type multi-chip package structure according to a third preferred embodiment of the present invention. Wherein, the carrier board 20 has an opening 201, the first chip 22 and the second chip 24 are accommodated in the opening 201, and the encapsulant 28 covers the part of the upper surface 202 of the carrier board 20, the first chip 22, the second chip The chips 24 and the conductive bumps 264 are exposed, and the backsides of the first chip 22 and the second chip 24 are exposed, so as to further reduce the thickness of the overall package structure.

再者，承上所述，如图5所示，亦可设置一散热片21于载板20下表面204，而第一芯片22及第二芯片24设置在散热片21上，如此更可提升封装体的散热效能，此为本发明的第四较佳实施例的桥接形式的多芯片封装构造。Furthermore, as mentioned above, as shown in Figure 5, a heat sink 21 can also be arranged on the lower surface 204 of the carrier board 20, and the first chip 22 and the second chip 24 are arranged on the heat sink 21, so that the The heat dissipation performance of the package is the bridging multi-chip package structure of the fourth preferred embodiment of the present invention.

承上所述，请参照图6，为本发明的第五较佳实施例的桥接形式的多芯片封装构造。载板20亦具有一开口201，第一芯片22及第二芯片24同时容置于该开口201中，而该开口201的大小恰可容置第一芯片22及第二芯片24。其中，第一芯片22具有一第三侧边223，第二芯片24具有一第四侧边243，开口20内具有一周壁203，该第一芯片22及第二芯片24的侧壁紧邻开口的周壁203，且第一芯片22的第一主动表面222、第二芯片24的第二主动表面242与载板20的上表面202共平面配置。接着，形成一第二导电凸块266以电性连接第一芯片22与载板20。同样地，另形成一第三导电凸块268以电性连接第二芯片24与载板20。Based on the above, please refer to FIG. 6 , which is a bridge-type multi-chip package structure according to a fifth preferred embodiment of the present invention. The carrier 20 also has an opening 201 , the first chip 22 and the second chip 24 are accommodated in the opening 201 at the same time, and the size of the opening 201 is just enough to accommodate the first chip 22 and the second chip 24 . Wherein, the first chip 22 has a third side 223, the second chip 24 has a fourth side 243, there is a peripheral wall 203 in the opening 20, and the side walls of the first chip 22 and the second chip 24 are adjacent to the opening. The surrounding wall 203 , and the first active surface 222 of the first chip 22 , the second active surface 242 of the second chip 24 and the upper surface 202 of the carrier 20 are coplanar. Next, a second conductive bump 266 is formed to electrically connect the first chip 22 and the carrier 20 . Similarly, a third conductive bump 268 is formed to electrically connect the second chip 24 and the carrier 20 .

不论是上述何种实施例，皆可于载板的上表面或下表面另植接多个焊球于其上，用以与外界电性导通的接点。Regardless of the above-mentioned embodiments, a plurality of solder balls can be planted on the upper surface or the lower surface of the carrier board to serve as contacts for electrical conduction with the outside world.

在上述的封装结构中，由于芯片接点间可以透过导电凸块电性连接，因此芯片接点间及芯片与载板接点间的传导路径甚短，且传导路径的径宽甚大，故可以降低传导阻抗，而减缓讯号的衰减，并且可以适于在高频电路的运作，而减少电感电容寄生效应(Parasitics)的发生。此外，由于导电凸块与载板接点或芯片接点接触的面积甚大，且载板接点可以直接与芯片接点接触，因此其接触阻抗甚小，故可以避免发生阻抗不匹配的现象，以致产生讯号反射的情形。另外，由于本发明可以改善芯片封装结构中如上所述的电性效能，因此会有甚佳的电源及接地的效果。In the above package structure, since the chip contacts can be electrically connected through conductive bumps, the conduction paths between the chip contacts and between the chip and the substrate contacts are very short, and the diameter of the conduction path is very wide, so the conduction can be reduced. Impedance, so as to slow down the attenuation of the signal, and can be suitable for operation in high-frequency circuits, and reduce the occurrence of parasitic effects (Parasitics) of inductance and capacitance. In addition, since the contact area between the conductive bump and the contact of the carrier board or the contact of the chip is very large, and the contact of the carrier board can directly contact the contact of the chip, the contact impedance is very small, so the phenomenon of impedance mismatch can be avoided, resulting in signal reflection situation. In addition, because the present invention can improve the above-mentioned electrical performance in the chip package structure, it will have excellent power supply and grounding effects.

在上述实施例中，以网板印刷的方式形成焊料于芯片接点上及载板点上，然而本发明形成焊料的方式并非仅限于此，请参照图7至图9，亦可以先形成一屏蔽层(mask layer)254到第一芯片22的第一主动表面222、第二芯片24的第二主动表面242及载板20的上表面202上，当屏蔽层254为感光材质时，如光阻，便可以直接透过曝光的步骤而直接形成开口256，以暴露出第一芯片接点226、第二芯片接点246及载板接点208；当屏蔽层254为非感光材质时，便可以透过微影蚀刻等步骤而形成开口256，以暴露出第一芯片接点226、第二芯片接点246及载板接点208。接着，便可以利用印刷的方式，形成一焊料258到屏蔽层254的开口256中，形成如图8所示的样式，其中焊料258由一助焊剂(未绘示)及多个金属粒子(未绘示)所构成，金属粒子均匀地混合在助焊剂中。之后，便进行回焊的制程，使得金属粒子可以熔融聚合而固化形成导电凸块259到第一芯片接点226、第二芯片接点246及载板接点208，如图9所示，其中第一芯片接点226可以通过导电凸块259与第二芯片接点246电性连接。同样地，第一芯片接点226可以通过导电凸块259与载板接点208电性连接。接着，便将屏蔽层254去除。其接下来的制程，如第一较佳实施例所述，在此便不再赘述。需说明的是，图4、5、6、7、8及9中各组件的参考符号与图3中的各组件的参考符号相对应。In the above-mentioned embodiment, the solder is formed on the chip contact and the carrier board by screen printing. However, the method of forming the solder in the present invention is not limited to this. Please refer to FIGS. Layer (mask layer) 254 to the first active surface 222 of the first chip 22, the second active surface 242 of the second chip 24 and the upper surface 202 of the carrier 20, when the shielding layer 254 is a photosensitive material, such as photoresist , the opening 256 can be directly formed through the exposure step to expose the first chip contact 226, the second chip contact 246 and the carrier board contact 208; The opening 256 is formed by steps such as shadow etching to expose the first chip contact 226 , the second chip contact 246 and the carrier contact 208 . Then, just can utilize the mode of printing, form a solder 258 in the opening 256 of shielding layer 254, form the style as shown in Figure 8, wherein solder 258 is made of a flux (not shown) and a plurality of metal particles (not shown) Shown), the metal particles are evenly mixed in the flux. After that, the reflow process is carried out so that the metal particles can be melted and polymerized to solidify to form conductive bumps 259 to the first chip contact 226, the second chip contact 246 and the carrier board contact 208, as shown in FIG. 9, wherein the first chip The contact 226 can be electrically connected to the second chip contact 246 through the conductive bump 259 . Likewise, the first chip contact 226 can be electrically connected to the carrier contact 208 through the conductive bump 259 . Then, the shielding layer 254 is removed. The subsequent manufacturing process is as described in the first preferred embodiment, and will not be repeated here. It should be noted that the reference symbols of the components in FIGS. 4 , 5 , 6 , 7 , 8 and 9 correspond to the reference symbols of the components in FIG. 3 .

于本实施例的详细说明中所提出的具体的实施例仅为了易于说明本发明的技术内容，而并非将本发明狭义地限制于该实施例，因此，在不超出本发明的精神及以下申请专利范围的情况，可作种种变化实施。The specific embodiment proposed in the detailed description of the present embodiment is only for the ease of explaining the technical content of the present invention, and the present invention is not narrowly limited to this embodiment, therefore, without departing from the spirit of the present invention and the following application The scope of the patent can be implemented in various ways.

Claims (31)

1. the multichip package structure of a bridged-style is characterized in that, comprises:
One support plate, this support plate has a upper surface and a lower surface;
One first chip, it has one first active surface, one first back side and a first side wall, this first active surface has at least one first contact and this first side wall connects this first active surface and this first back side, this first chip disposes with the upper surface of this first back side towards this encapsulating carrier plate, and electrically connects with this support plate;
One second chip, it has one second active surface, one second back side and one second sidewall, this second active surface has at least one second contact and this second sidewall connects this second active surface and this second back side, this second chip disposes with the upper surface of this second back side towards this encapsulating carrier plate, and electrically connects with this support plate; And
At least one first conductive projection, this conductive projection are attached on first active surface of this first chip and on second active surface of second chip and extend, and make the electric connection of this first chip and this second chip.
2. the multichip package structure of bridged-style as claimed in claim 1 wherein more comprises an encapsulating material, and it coats this first chip, this second chip, this upper surface of said carrier plate and this first conductive projection.
3. the multichip package structure of bridged-style as claimed in claim 1 wherein more comprises a plurality of conductive components, and this conductive component is arranged on the lower surface of this support plate.
4. the multichip package structure of bridged-style as claimed in claim 3, wherein said conductive component is a soldered ball.
5. the multichip package structure of bridged-style as claimed in claim 1, first contact to the small part that wherein said first chip has is positioned on the edge of this first chip.
6. the multichip package structure of bridged-style as claimed in claim 1, second contact to the small part that wherein said second chip has is positioned on the edge of this second chip.
7. the multichip package structure of bridged-style as claimed in claim 1, wherein said first conductive projection is a leypewter.
8. the multichip package structure of bridged-style as claimed in claim 1, the unleaded electric conducting material of wherein said first conductive projection.
9. the multichip package structure of bridged-style as claimed in claim 1, first contact of wherein said first chip abuts against the next door of second contact of this second chip.
10. the multichip package structure of bridged-style as claimed in claim 1, wherein said first conductive projection is a conducting resinl.
11. the multichip package structure of bridged-style as claimed in claim 1, second sidewall of wherein said second chip is in close proximity to the first side wall of described first chip.
12. the multichip package structure of bridged-style as claimed in claim 1, second contact that wherein said second chip has is in close proximity to first joint configuration that described first chip has.
13. the multichip package structure of bridged-style as claimed in claim 1, the active surface of the active surface of wherein said second chip and described first chip is coplanar configuration.
14. the multichip package structure of bridged-style as claimed in claim 1 more comprises many conductor wires, wherein first chip electrically connects by described conductor wire and this support plate.
15. the multichip package structure of bridged-style as claimed in claim 1 also comprises many conductor wires, wherein second chip electrically connects by described conductor wire and this support plate.
16. the multichip package structure of bridged-style as claimed in claim 13, between second sidewall of the first side wall of wherein said first chip and described second chip one obturator is set, this obturator has a upper surface, and this upper surface is a copline with the active surface of first chip and the active surface of second chip simultaneously.
17. the multichip package structure of bridged-style as claimed in claim 1, wherein this support plate also has an opening, and described first chip and described second chip are placed in this opening.
18. the multichip package structure of bridged-style as claimed in claim 17 wherein also comprises a fin, described fin is arranged at the lower surface of this support plate.
19. the multichip package structure of bridged-style as claimed in claim 18 wherein also comprises a plurality of soldered balls, described soldered ball is arranged at this upper surface of said carrier plate.
20. the multichip package structure of bridged-style as claimed in claim 17, wherein said open interior has a perisporium, this first chip and this second chip also have the 3rd sidewall and one the 4th sidewall respectively, and the 3rd sidewall and the 4th sidewall are close to this perisporium respectively.
21. the multichip package structure of bridged-style as claimed in claim 17, the active surface of the active surface of wherein said second chip, described first chip and described upper surface of said carrier plate are coplanar configuration.
22. the multichip package structure of bridged-style as claimed in claim 20 wherein also comprises a fin, this fin is arranged at the lower surface of this support plate.
23. the multichip package structure of bridged-style as claimed in claim 21 wherein also comprises a fin, this fin is arranged at the lower surface of this support plate.
24. the multichip package structure of bridged-style as claimed in claim 22 wherein also comprises a plurality of soldered balls, described soldered ball is arranged on this upper surface of said carrier plate.
25. the multichip package structure of bridged-style as claimed in claim 23 wherein also comprises a plurality of soldered balls, described soldered ball is arranged on this upper surface of said carrier plate.
26. the multichip package structure of bridged-style as claimed in claim 17 also comprises many conductor wires, wherein first chip electrically connects by described conductor wire and this support plate.
27. the multichip package structure of bridged-style as claimed in claim 17 also comprises many conductor wires, wherein second chip electrically connects by described conductor wire and this support plate.
28. the multichip package structure of bridged-style as claimed in claim 20 also comprises at least one second conductive projection, wherein first chip electrically connects by described second conductive projection and this support plate.
29. the multichip package structure of bridged-style as claimed in claim 20 also comprises at least one second conductive projection, wherein second chip electrically connects by described second conductive projection and this support plate.
30. the multichip package structure of bridged-style as claimed in claim 21 also comprises at least one second conductive projection, wherein first chip electrically connects by described second conductive projection and this support plate.
31. the multichip package structure of bridged-style as claimed in claim 21 also comprises at least one second conductive projection, wherein second chip electrically connects by described second conductive projection and this support plate.
CNB031562701A 2003-09-02 2003-09-02 Bridging type multi-chip packaging structure Expired - Lifetime CN100474581C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB031562701A CN100474581C (en) 2003-09-02 2003-09-02 Bridging type multi-chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB031562701A CN100474581C (en) 2003-09-02 2003-09-02 Bridging type multi-chip packaging structure

Publications (2)

Publication Number Publication Date
CN1591862A CN1591862A (en) 2005-03-09
CN100474581C true CN100474581C (en) 2009-04-01

Family

ID=34598366

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031562701A Expired - Lifetime CN100474581C (en) 2003-09-02 2003-09-02 Bridging type multi-chip packaging structure

Country Status (1)

Country Link
CN (1) CN100474581C (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7472287B2 (en) * 2019-12-13 2024-04-22 華為技術有限公司 Electronic element, circuit board with electronic element, and electronic device
CN111491489B (en) * 2020-04-10 2022-11-15 深圳国人无线通信有限公司 Printed board assembly

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198385A (en) * 1991-01-11 1993-03-30 Harris Corporation Photolithographic formation of die-to-package airbridge in a semiconductor device
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US6020597A (en) * 1997-03-05 2000-02-01 Lg Semicon Co., Ltd. Repairable multichip module
US6410983B1 (en) * 1999-05-26 2002-06-25 Fujitsu Limited Semiconductor device having a plurality of multi-chip modules interconnected by a wiring board having an interface LSI chip
US20020106893A1 (en) * 2001-02-07 2002-08-08 International Business Machines Corporation Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage
GB2373924A (en) * 1997-05-17 2002-10-02 Hyundai Electronics Ind IC device with a metal thermal conductive layer having an opening for evacuating air

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198385A (en) * 1991-01-11 1993-03-30 Harris Corporation Photolithographic formation of die-to-package airbridge in a semiconductor device
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US6020597A (en) * 1997-03-05 2000-02-01 Lg Semicon Co., Ltd. Repairable multichip module
GB2373924A (en) * 1997-05-17 2002-10-02 Hyundai Electronics Ind IC device with a metal thermal conductive layer having an opening for evacuating air
US6410983B1 (en) * 1999-05-26 2002-06-25 Fujitsu Limited Semiconductor device having a plurality of multi-chip modules interconnected by a wiring board having an interface LSI chip
US20020106893A1 (en) * 2001-02-07 2002-08-08 International Business Machines Corporation Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage

Also Published As

Publication number Publication date
CN1591862A (en) 2005-03-09

Similar Documents

Publication Publication Date Title
CN102543937B (en) Flip chip on-chip package and manufacturing method thereof
TWI404175B (en) Semiconductor package having electrical connecting structures and fabrication method thereof
US8304268B2 (en) Fabrication method of semiconductor package structure
TW201644024A (en) Chip packaging structure and manufacture method thereof
CN105977225B (en) Encapsulating structure and packaging method
JP3851797B2 (en) Ball grid array package and circuit board used therefor
US6864588B2 (en) MCM package with bridge connection
US6242283B1 (en) Wafer level packaging process of semiconductor
US7374969B2 (en) Semiconductor package with conductive molding compound and manufacturing method thereof
US20080308951A1 (en) Semiconductor package and fabrication method thereof
TWI227051B (en) Exposed pad module integrated a passive device therein
US6455355B1 (en) Method of mounting an exposed-pad type of semiconductor device over a printed circuit board
TW575931B (en) Bridge connection type of chip package and process thereof
US8471383B2 (en) Semiconductor package and fabrication method thereof
CN100474581C (en) Bridging type multi-chip packaging structure
CN101399246A (en) Package substrate structure and production method thereof
CN101145549A (en) Ball grid array packaging structure and packaging method thereof
JP2000058579A (en) Semiconductor device and method of manufacturing the same
CN203339142U (en) An underfill filled FCQFN package
KR19980025624A (en) Ball Grid Array Semiconductor Package
TWI427717B (en) A method of flip chip package
CN102130085B (en) Semiconductor package with electrical connection structure and manufacturing method thereof
CN101378023B (en) Semiconductor package and fabrication method thereof
CN203085511U (en) Re-wiring multi-chip AAQFN packaging device
JP2004014568A (en) Semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20090401