CN100470622C

CN100470622C - Signal separation circuit, light-emitting display using same, and driving method thereof

Info

Publication number: CN100470622C
Application number: CNB2005100921248A
Authority: CN
Inventors: 金阳完; 朴镕盛; 郑宝容
Original assignee: Samsung Mobile Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2004-08-25
Filing date: 2005-08-19
Publication date: 2009-03-18
Anticipated expiration: 2025-08-19
Also published as: CN1741109A; KR100581810B1; KR20060018766A

Abstract

A signal separation circuit, a light emitting display using the same, and a driving method thereof, in which the number of output lines provided in a data driver is reduced. The light-emitting display includes: a scan driver for sequentially supplying scan signals to the scan lines; a data driver provided with a plurality of output lines for providing a plurality of data signals to each output line while supplying the scan signals; a display part including a plurality of pixels located in an area divided by a scan line and a plurality of data lines; a plurality of demultiplexers each coupling a respective output line and comprising a plurality of data transistors, the data transistors adapted to provide respective data signals from respective output lines to more than one of the plurality of data lines; and a plurality of initializers comprising a plurality of each adapted to apply a predetermined voltage to the plurality of data lines initialization transistor.

Description

Demultiplexing circuit, the active display that uses it and driving method thereof

The application requires on August 25th, 2004 to the korean patent application 10-2004-0067283 of Korea S Department of Intellectual Property submission and 10-2004-0067285 number right of priority, quotes in full for your guidance hereby.

Technical field

The present invention relates to a kind of demultiplexing circuit (demultiplexing circuit), use its active display and driving method thereof, a kind of demultiplexing circuit of the output line quantity that provides in data driver, the active display that uses it and driving method thereof of wherein having reduced is provided.

Background technology

Recently, various flat-panel monitors have been developed and have replaced the cathode ray tube (CRT) display, because CRT monitor is heavy relatively.Flat-panel monitor can be LCD (LCD), electroluminescent display (FED), plasma display panel (PDP), active display (LED) etc.In flat-panel monitor, active display can come self luminous by electronics-hole recombination.The advantage of this active display is that the response time is very fast relatively, and power consumption is relatively low.Usually, the thin film transistor (TFT) that the active display utilization provides in each pixel (TFT) provides electric current corresponding to data-signal to luminescent device or diode (LED), thereby makes luminescent device luminous.

Fig. 1 is the planimetric map of traditional active display.

With reference to figure 1, traditional active display comprises: image display part 30, and it has adjacent to multi-strip scanning line S1 wherein to Sn and many a plurality of pixels 40 that data line D1 form to the cross one another zone of Dm; Scanner driver 10 is used for driven sweep line S1 to Sn; Data driver 20 is used for driving data lines D1 to Dm; With timing controller 50, be used for gated sweep driver 10 and data driver 20.

Scanner driver 10 responds from the scan control signal SCS of timing controller 50 transmissions and produces (or a plurality of) sweep signal, and provides (or a plurality of) sweep signal to sweep trace S1 successively to Sn.And, scanner driver 10 responding scanning control signal SCS and produce (or a plurality of) led control signal, and provide (or a plurality of) led control signal successively to En to light emitting control line E1.

Data driver 20 responds from the data controlling signal DCS of timing controller 50 transmissions and produces (or a plurality of) data-signal, and provides (or a plurality of) data-signal to data line D1 successively to Dm.Just, data driver 20 every horizontal cycles provide corresponding to a horizontal data-signal to Dm to data line D1.

Timing controller 50 response external synchronizing signals and produce data controlling signal DCS and scan control signal SCS.Here, data controlling signal DCS is sent to data driver 20, and scan control signal SCS is sent to scanner driver 10.And timing controller 50 rearranges external data Data, and it is provided to data driver 20.

Image display part 30 receives from outside first power supply (for example, first voltage) of first power supply (perhaps line) VDD with from the outside second source (for example, second voltage) of second source (perhaps line) VSS.Be provided to each pixel 40 from first power supply of the first power vd D with from the second source of second source VSS herein.Each pixel 40 reception data-signal and demonstration are corresponding to the image of this data-signal.In addition, control the fluorescent lifetime of pixel 40 according to led control signal.

In traditional active display, each pixel 40 be arranged in wherein sweep trace S1 to Sn and data line D1 to the cross one another zone of Dm.Herein, data driver 20 comprises m bar output line, be used for data-signal provide to m bar data line D1 to Dm.Just, the data driver 20 of traditional active display has the output line to the number of Dm with data line D1.Data driver 20 comprises a plurality of data integrated circuits that are used for m bar output line, and this increases the production cost of display.Particularly, the resolution of image display part 30 is high more and size is big more, and then the number of output lines increase of data driver 20 is many more.Therefore, the production cost of active display increases.

Summary of the invention

Therefore, embodiments of the invention provide a kind of demultiplexing circuit, use its active display and driving method thereof, and the number of output lines that provides in data driver wherein has been provided.

One embodiment of the present of invention provide a kind of active display.Described active display comprises: scanner driver is used for providing sweep signal successively to sweep trace; Be provided with the data driver of many output lines (perhaps first data line), be used for when sweep signal is provided, providing a plurality of data-signals to each bar output line; Image display part, it has a plurality of pixels that are arranged in the zone of being divided by sweep trace and many data lines (or second data line); A plurality of demultiplexers, a be coupled corresponding output line and comprise a plurality of data transistors of each demultiplexer, described data transistor be suitable for the corresponding data-signal from a corresponding output line offer in many data lines more than a data line; With a plurality of initializer (initializer), it has a plurality of initialization transistors that are suitable for predetermined voltage is applied to each bar of many data lines.

In one embodiment of the invention, each pixel comprises a plurality of pixel transistors, and at least one pixel transistor is connected to become diode.And in one embodiment, active display comprises the demultiplexer controller, is used for the control signal separation vessel, so that will offer many data lines from a plurality of data-signals of every data line.And in one embodiment, the quantity of the initialization transistor that provides on each initializer is provided the quantity of the data transistor that provides in each demultiplexer.And in one embodiment, when at least one sweep signal was provided, the demultiplexer controller provided control signal, so that a plurality of data transistors of conducting successively.And in one embodiment, before the data transistor in the corresponding demultiplexer of conducting, the demultiplexer controller provides initialization control signal, so that the initialization transistor in each initializer of conducting.

One embodiment of the present of invention provide a kind of demultiplexing circuit.Described demultiplexing circuit comprises: a plurality of demultiplexers that are coupled to many output lines of data driver respectively, and have a plurality of data transistors, described data transistor be suitable for each data-signal from each bar output line offer in many data lines more than a data line; With a plurality of initializer, it has a plurality of initialization transistors that are suitable for predetermined voltage is offered each bar of many data lines.

In one embodiment, the quantity of the initialization transistor that provides on each initializer is provided the quantity of the data transistor that provides in each demultiplexer.In addition, in one embodiment, be provided at the data transistor conducting successively in each demultiplexer, so that provide a plurality of data-signals to many data lines.And, in one embodiment, before the data transistor in the corresponding demultiplexer of conducting, the initialization transistor that provides in each initializer of conducting, and the initialization transistor that provides in each initializer constantly in difference.

One embodiment of the present of invention provide a kind of method of driven for emitting lights display.Described method comprises: provide sweep signal successively to the multi-strip scanning line; Each bar output line to data driver when sweep signal is provided provides a plurality of data-signals; Conducting is connected to a plurality of data transistors of each bar output line successively, so that provide a plurality of data-signals to many data lines; With before the conducting data transistor, conducting is connected to a plurality of initialization transistors of many data lines, so that initialize power is offered many data lines.

In one embodiment, initialization transistor ends constantly in difference.

Description of drawings

In conjunction with the drawings, from the following description of exemplary embodiment, these and/or other aspect of the present invention will become obviously and be more readily understood, wherein:

Fig. 1 is the planimetric map of traditional active display;

Fig. 2 is the planimetric map according to the active display of first embodiment of the invention;

Fig. 3 is the circuit diagram of the demultiplexer that provides in the active display according to first embodiment of the invention;

Fig. 4 is the circuit diagram of the pixel that provides in the active display according to first embodiment of the invention;

Fig. 5 is the connecting circuit figure between the pixel of the demultiplexer of Fig. 3 and Fig. 4;

The waveform of the drive signal of the demultiplexer that provides in the active display that is provided for according to first embodiment of the invention and pixel is provided Fig. 6;

Fig. 7 is the circuit diagram of the pixel that provides in the active display according to second embodiment of the invention;

Fig. 8 is the connecting circuit figure between the pixel of the demultiplexer of Fig. 3 and Fig. 7;

The waveform of the drive signal of the demultiplexer that provides in the active display that is provided for according to second embodiment of the invention and pixel is provided Fig. 9;

Figure 10 is the planimetric map according to the active display of third embodiment of the invention;

Figure 11 is the circuit diagram of the initializer that provides in the active display according to third embodiment of the invention;

Figure 12 is the initializer that provides in the active display according to third embodiment of the invention and the connecting circuit figure between the demultiplexer;

Figure 13 is the connecting circuit figure between initializer, demultiplexer and the pixel that provides in the active display according to third embodiment of the invention;

The waveform of the drive signal of the demultiplexer that provides in the active display that offers according to third embodiment of the invention and pixel is provided Figure 14;

Figure 15 is the connecting circuit figure between initializer, demultiplexer and the pixel that provides in the active display according to fourth embodiment of the invention;

Figure 16 is the figure corresponding to the channel width of the turn-on cycle of initialisation switch device;

Figure 17 illustrates the initialisation switch size of devices, and this size is inversely proportional to turn-on cycle and sets; With

The waveform of the drive signal of the demultiplexer, initializer and the pixel that provide in the active display that is provided for third and fourth embodiment according to the present invention is provided Figure 18.

Embodiment

Below, will describe with reference to the accompanying drawings according to exemplary embodiment of the present invention.Provide exemplary embodiment of the present invention so that those of ordinary skill in the art understands easily.

Fig. 2 is the planimetric map according to the active display of first embodiment of the invention.

With reference to figure 2, comprise scanner driver 110, data driver 120, image display part 130, timing controller 150, Signal Separation piece 160 and demultiplexer controller 170 according to the active display of first embodiment of the invention.

Image display part 130 comprises and is positioned at a plurality of pixels 140 to Sn and many second data line DL1 to the adjacent area of DLm definition by multi-strip scanning line S1.Each pixel 140 is sent the light corresponding to the data-signal that sends by the second data line DL.

The scan control signal SCS that scanner driver 110 response provides from timing controller 150 and produce (or a plurality of) sweep signal, and this (or a plurality of) sweep signal is provided successively to sweep trace S1 to Sn.And, scanner driver 110 responding scanning control signal SCS and produce (or a plurality of) led control signal, and this (or a plurality of) led control signal is provided successively to light emitting control line E1 to En.

The data controlling signal DCS that data driver 120 response provides from timing controller 150 and produce (or a plurality of) data-signal, and provide the bar first data line D1 to Dm/i at the most with this (or a plurality of) data-signal.Here, the first data line D1 to Dm/i is connected to each bar output line of data driver 120, and when sweep signal is provided, data driver 120 with i (wherein i be 2 or bigger natural number) individual data-signal provides to the first data line D1 to Dm/i.Just, data driver 120 each horizontal cycle provide i data-signal.

Data controlling signal DCS and scan control signal SCS that timing controller 150 produces corresponding to outer synchronous signal.The data controlling signal DCS that produces in timing controller 150 is provided to data driver 120, and the scan control signal SCS that produces in timing controller 150 is provided to scanner driver 110.In addition, timing controller 150 provides external data Data to data driver 120.

Demultiplexer piece 160 comprises m/i demultiplexer 162.In other words, demultiplexer piece 160 has the demultiplexer 162 to the number of Dm/i with the first data line D1, and wherein m/i demultiplexer 162 is connected respectively to the first data line D1 to Dm/i.

And each demultiplexer 162 is connected respectively to the i bar second data line DL.Therefore, demultiplexer 162 provides each horizontal cycle to the i bar second data line DL successively by the data-signal that the first data line D receives.Just, a demultiplexer 162 will provide to the i bar second data line DL by the data-signal that one first data line D receives.Because the data-signal that receives from one first data line D is provided for the i bar second data line DL, therefore can reduce the number of output lines that in data driver 120, provides.For example, when i was 3, the number of output lines that provides in data driver 120 had reduced 1/3, and the quantity of the data integrated circuit that therefore provides in data driver 120 has also reduced.Just,, utilize demultiplexer 162 will offer the i bar second data line DL, thereby reduce the production cost of active display from the data-signal of one first data line D according to embodiments of the invention.

Demultiplexer controller 170 each horizontal cycle provide i control signal to each demultiplexer 162.Just, demultiplexer controller 170 provides i control signal, thereby data-signal is provided to the i bar second data line DL from one first data line D.In this embodiment, demultiplexer controller 170 is provided at the outside of timing controller 150, and still, in another embodiment, the demultiplexer controller can be provided at the inside of timing controller 150.

Fig. 3 is the circuit diagram of the demultiplexer that provides in the active display according to first embodiment of the invention.Purpose for example only, i equals 3.And demultiplexer shown in Figure 3 is connected to the 1st first data line D1.

With reference to figure 3, each demultiplexer 162 comprises first switching device (perhaps transistor) T1, second switch device T2 and the 3rd switching element T 3.

First switching element T 1 is connected between article one first data line D1 and article one second data line DL1, and data-signal is sent to article one second data line DL1 from article one first data line D1.Here, first switching element T 1 is driven by the first control signal CS1 that provides from demultiplexer controller 170.

Second switch device T2 is connected between article one first data line D1 and the second second data line DL2, and data-signal is sent to the second second data line DL2 from article one first data line D1.Here, second switch device T2 is driven by the second control signal CS2 that provides from demultiplexer controller 170.

The 3rd switching element T 3 is connected between article one first data line D1 and the 3rd the second data line DL3, and data-signal is sent to the 3rd second data line DL3 from article one first data line D1.Here, the 3rd switching element T 3 is driven by the 3rd control signal CS3 that provides from demultiplexer controller 170.

For this configuration, the operation of demultiplexer 162 will be described in conjunction with the structure of pixel 140.

Fig. 4 is the circuit diagram of the pixel that provides in the active display according to first embodiment of the invention.In fact, the present invention can utilize various pixels, as long as it received initializing signal before receiving data-signal.Here, at least one transistor that provides in each pixel 140 is connected to become the function of diode.

With reference to figure 4, comprise luminescent device OLED and image element circuit 142 according to each pixel 140 of first embodiment of the invention.Image element circuit 142 is connected to the second data line DL, sweep trace S (for example, sweep trace Sn and/or sweep trace Sn-1) and luminous (emission) control line E (for example, light emitting control line En), and it is next luminous to be used for controlling light emitting device OLED.

Luminescent device OLED comprises the anode that is connected to image element circuit 142 and is connected to the negative electrode of second source line VSS.Second source line VSS has been applied in second voltage, and this second voltage is lower than first voltage that is applied to the first power lead VDD.For example, ground voltage can be applied to second source line VSS.Light corresponding to the electric current that provides from image element circuit 142 is provided luminescent device OLED.For this reason, luminescent device OLED comprises fluorescence and/or phosphorescence organic material.

Image element circuit 142 comprises: holding capacitor Cst and the 6th transistor M6, and they are connected between the first power lead VDD and the n-1 bar sweep trace Sn-1; Transistor seconds M2 and the 4th transistor M4, they are connected between the first power lead VDD and the data line DL; The 5th transistor M5, it is connected between luminescent device OLED and the light emitting control line En; The first transistor M1, it is connected between the first node N1 that the 5th transistor M5 and transistor seconds M2 and the 4th transistor M4 be connected jointly; With the 3rd transistor M3, it is connected between the gate terminal and drain electrode end of the first transistor M1.In Fig. 4, first to the 6th transistor M1 to M6 is that p type metal oxide semiconductor field effect is answered transistor (PMOSFET), but the present invention is not limited to this.

The drain electrode end of the source terminal that the first transistor M1 comprises the source terminal that is connected to first node N1, be connected to the 5th transistor M5 and be connected to the gate terminal of holding capacitor Cst.In addition, the first transistor M1 will offer luminescent device OLED corresponding to the electric current of the voltage that charges at holding capacitor Cst.

The 3rd transistor M3 comprise the gate terminal that is connected to the first transistor M1 drain electrode end, be connected to the first transistor M1 drain electrode end source terminal and be connected to the gate terminal of n bar sweep trace Sn.And, when sweep signal is sent to n bar sweep trace Sn, the 3rd transistor M3 conducting, thus make the first transistor M1 play diode.Just, when the 3rd transistor M3 conducting, the first transistor M1 plays diode.

Transistor seconds M2 comprises the source terminal that is connected to data line DL, be connected to the drain electrode end of first node N1 and be connected to the gate terminal of n bar sweep trace Sn.And, when sweep signal is sent to n bar sweep trace Sn, transistor seconds M2 conducting, thus data-signal is sent to first node N1 from data line DL.

The 4th transistor M4 comprises the drain electrode end that is connected to first node N1, be connected to the source terminal of the first power lead VDD and be connected to the gate terminal of light emitting control line En.And, when led control signal is not provided, the 4th transistor M4 conducting, thus the first power lead VDD is electrically connected with first node N1.

The 5th transistor M5 comprise the drain electrode end that is connected to the first transistor M1 source terminal, be connected to the drain electrode end of luminescent device OLED and be connected to the gate terminal of light emitting control line E.And, when led control signal is not provided, the 5th transistor M5 conducting, thus electric current is provided to luminescent device OLED from the first transistor M1.

The 6th transistor M6 comprises the source terminal that is connected to holding capacitor Cst and the drain electrode end and the gate terminal that are connected to (n-1) bar sweep trace Sn-1.And, when sweep signal is sent to (n-1) bar sweep trace Sn-1, the 6th transistor M6 conducting, thereby the gate terminal of initialization holding capacitor Cst and the first transistor M1.

Fig. 5 is the connecting circuit figure between the pixel of the demultiplexer of Fig. 3 and Fig. 4.Purpose shows demultiplexer and is connected with red (R), green (G) and blue (B) pixel for example, that is, i equals 3.The waveform of the drive signal of the sweep trace, data line and the demultiplexer that provide in the active display that is provided for according to first embodiment of the invention is provided Fig. 6.

With reference to figure 5 and 6, when sweep signal is sent to (n-1) bar sweep trace Sn-1, each the 6th transistor M6 conducting of

pixel

142R, 142G and 142B.Therefore, when the 6th transistor M6 conducting, the gate terminal of holding capacitor Cst and the first transistor M1 is connected to (n-1) bar sweep trace Sn-1.Just, when sweep signal is sent to (n-1) bar sweep trace Sn-1, sweep signal is provided to each holding capacitor Cst and the gate terminal of each the first transistor M1 of providing in

pixel

142R, 142G and 142B, thus the gate terminal of each holding capacitor Cst of initialization and each the first transistor M1.In this embodiment, sweep signal has the voltage level that is lower than data-signal.

When sweep signal was sent to (n-1) bar sweep trace Sn-1, first to the 3rd switching element T 1 was to T3 conducting successively, thereby data-signal is sent to three second data line DL3 of article one second data line DL1 to the.At this moment, transistor seconds M2 ends, thereby data-signal is not provided to

pixel

142R, 142G, 142B.

Then, sweep signal is sent to n bar sweep trace Sn.When sweep signal is sent to n bar sweep trace Sn, each transistor seconds M2 of

pixel

142R, 142G, 142B and each the 3rd transistor M3 conducting.After each transistor seconds M2 and each the 3rd transistor M3 conducting of

pixel

142R, 142G, 142B, first switching element T 1 is once more by the first control signal CS1 conducting.

When 1 conducting of first switching element T, data-signal is sent to the first node N1 of the first pixel 142R via first switching element T 1 from article one first data line D1.At this moment, because be applied to the sweep signal initialization that the voltage of the gate terminal of the first transistor M1 is sent to (n-1) bar sweep trace Sn-1, that is, be set to have the voltage level that is lower than the data-signal that is applied to first node N1, so the first transistor M1 conducting.Because the first transistor M1 conducting, so be applied to the data-signal of first node N1 is sent to holding capacitor Cst via the first transistor M1 and the 3rd transistor M3 a end.At this moment, with voltage holding capacitor Cst is charged corresponding to data-signal.And, except voltage, use corresponding to the threshold voltage according of the first transistor M1 holding capacitor Cst is charged corresponding to data-signal.

Then, first switching element T 1 is ended, and the second and the 3rd switching element T 2 and T3 conducting successively, thereby data-signal is sent to the second pixel 142G and the 3rd pixel 142B successively.

Therefore, according to embodiments of the invention, utilize demultiplexer 162 that data-signal is provided to the i bar second data line DL from one first data line D1.Yet in the active display according to first embodiment of the invention, that data-signal may not be provided to is predetermined (or expectation) pixel 142.

Particularly, and with reference to figure 5, when 1 conducting of first switching element T, with corresponding to the holding capacitor Cst charging of the voltage of aforesaid data-signal to the first pixel 142R.In this embodiment, when 1 conducting of first switching element T, each transistor seconds M2 of the second and the

3rd pixel

142G and 142B and each the 3rd transistor M3 also are sent to the sweep signal conducting of n bar sweep trace Sn.

When the second and the 3rd transistor M2 of the second pixel 142G and M3 conducting, the gate terminal of the first transistor M1 is electrically connected to the 2nd second data line DL2.In this embodiment, the 2nd second data line DL2 is connected with capacitor parasitics etc., thereby the voltage of the data-signal that provides during (preceding field or previous frame) is provided the previous cycle.Therefore, the voltage that is applied to the gate terminal of the first transistor M1 is changed to the voltage of the data-signal that sends during the cycle formerly.Just, be changed to the voltage of the data-signal that sends during the cycle formerly by the initialized voltage of sweep signal that sends to (n-1) bar sweep trace Sn-1.

Then, second switch device T2 is by the second control signal CS2 conducting.When second switch device T2 conducting, data-signal is sent to the 2nd second data line DL2 from the 1st first data line D1.Then, the transistor seconds M2 via the second pixel 142G is sent to first node N1 with data-signal from the 2nd second data line DL2.In this embodiment, first node N1 has been applied in corresponding to the current data voltage of signals, and the gate terminal of the first transistor M1 has been applied in corresponding to the past data voltage of signals.In this case, the first transistor M1 is conducting when the voltage that is applied to first node N1 is higher than the threshold voltage sum of past data voltage of signals and the first transistor M1 only, otherwise ends.

Similarly, according to the first embodiment of the present invention, when demultiplexer 162 operations, change the voltage of the gate terminal that each the first transistor M1 that provides is provided in the second and the

3rd pixel

142G and 142B, thereby data-signal may not have the voltage of expectation, therefore the desired images that is difficult to normally show.

Fig. 7 is the circuit diagram of the pixel that provides in the active display according to second embodiment of the invention.In Fig. 7, pixel 140 received initializing signal before receiving data-signal, and at least one transistor that provides in pixel 140 can be used as diode.

With reference to figure 7, comprise luminescent device OLED and image element circuit 144 according to each pixel 140 of second embodiment of the invention.Image element circuit 144 is connected to the second data line DL and sweep trace S (for example, sweep trace Sn and/or sweep trace Sn-1), and it is luminous to be used for controlling light emitting device OLED.

Luminescent device OLED comprises the anode that is connected to image element circuit 144 and is connected to the negative electrode of second source line VSS.Second source line VSS has been applied in second voltage, and this second voltage is lower than first voltage that is applied to the first power lead VDD.For example, ground voltage can be applied to second source line VSS.Light corresponding to the electric current that provides from image element circuit 144 is provided luminescent device OLED.For this reason, luminescent device OLED comprises fluorescence and/or phosphorescence organic material.

Image element circuit 144 comprises: the transistor seconds M2 that is connected to the second data line DL and n bar sweep trace Sn; Be connected the 3rd transistor M3 and the 4th transistor M4 between the transistor seconds M2 and the second initialization voltage line Vint2; Be connected the first transistor M1 and the 5th transistor M5 between the first power lead VDD and the luminescent device OLED; And be connected the source terminal of the first transistor M1 and the holding capacitor Cst between the gate terminal.In Fig. 7, first to fourth transistor M1 to M4 is PMOSFET, and the 5th transistor M5 is n type MOSFET (NMOSFET), but the present invention is not limited to this, and as long as the 5th transistor M5 is different from first to fourth transistor M1 to M4 and just can changes on type.

The drain electrode end of the source terminal that the first transistor M1 comprises the source terminal that is connected to the first power lead VDD, be connected to the 5th transistor M5 and be connected to the gate terminal of the gate terminal of the 3rd transistor M3.In addition, the first transistor M1 will offer luminescent device OLED corresponding to the electric current of the voltage that charges at holding capacitor Cst.

The 5th transistor M5 comprises the drain electrode end that is connected to luminescent device OLED and is connected to the gate terminal of (n-1) bar sweep trace Sn-1.And, when sweep signal is not provided to (n-1) bar sweep trace Sn-1, the 5th transistor M5 conducting, thus electric current is provided to luminescent device OLED from the first transistor M1.

Transistor seconds M2 comprises the gate terminal that is connected to n bar sweep trace Sn, be connected to the source terminal of the second data line DL and be connected to the drain electrode end of the source terminal of the 3rd transistor M3.And, when sweep signal is sent to n bar sweep trace Sn, transistor seconds M2 conducting, thus data-signal is sent to the 3rd transistor M3 from data line DL.

The 3rd transistor M3 comprises the drain electrode end of the source terminal that is connected to the 4th transistor M4.And drain electrode end and the gate terminal of the 3rd transistor M3 are interconnected with one another.Because drain electrode end and the gate terminal of the 3rd transistor M3 are interconnected with one another, so the 3rd transistor M3 plays diode.

The 4th transistor M4 comprises gate terminal that is connected to (n-1) bar sweep trace Sn-1 and the drain electrode end that is connected to the second initialization voltage line Vint2.And, when sweep signal is sent to (n-1) bar sweep trace Sn-1, the 4th transistor M4 conducting, thus second initialize power is provided to the 3rd transistor M3 from the second initialization voltage line Vint2.

Fig. 8 is the connecting circuit figure between the pixel of the demultiplexer of Fig. 3 and Fig. 7.Purpose shows a demultiplexer 162 and is connected with red (R), green (G) and blue (B) pixel for example; That is, i equals 3.And the waveform of the drive signal of the demultiplexer that provides in the active display that is provided for according to second embodiment of the invention and pixel is provided Fig. 9.

With reference to figure 8 and 9, when sweep signal is sent to (n-1) bar sweep trace Sn-1, each the 4th transistor M4 conducting of

pixel

144R, 144G and 144B.Therefore, when the 4th transistor M4 conducting, the gate terminal of the end of holding capacitor Cst, the gate terminal of the first transistor M1 and the 3rd transistor M3 is connected to the second initialization voltage line Vint2.Just, when the 4th transistor M4 conducting, the second initialization voltage line Vint2 is provided to the gate terminal of the gate terminal of an end, the first transistor M1 of holding capacitor Cst and the 3rd transistor M3 ' and to they initialization.In this embodiment, second initialize power of the second initialization voltage line Vint2 is set to has that the minimum voltage that is lower than by the data-signal that provides from data driver (for example, data driver 120) deducts the threshold voltage of the 3rd transistor M3 and the voltage of the voltage that obtains.

Then, sweep signal is sent to n bar sweep trace Sn.When sweep signal is sent to n bar sweep trace Sn, each transistor seconds M2 conducting of

pixel

144R, 144G, 144B.After each transistor seconds M2 conducting of

pixel

144R, 144G, 144B, first switching element T 1 is by the first control signal CS1 conducting.

When 1 conducting of first switching element T, data-signal is provided to the source terminal of the 3rd transistor M3 that provides among the first pixel 144R from the first data line D1 via first switching element T 1.At this moment, because the gate terminal of the 3rd transistor M3 just, is had the voltage level that is lower than source terminal by the second initialize power initialization of the second initialize power line Vint2, therefore the 3rd transistor M3 conducting.When the 3rd transistor M3 conducting, data-signal is provided for the gate terminal of the 3rd transistor M3,, is provided for the end of holding capacitor Cst that is.At this moment, with voltage each holding capacitor Cst is charged corresponding to data-signal.And, except voltage, use corresponding to the threshold voltage according of the first transistor M1 holding capacitor Cst is charged corresponding to data-signal.

Then, first switching element T 1 is ended, and second switch device T2 and the 3rd switching element T 3 conducting successively, thereby data-signal is provided successively to the second pixel 144G and the 3rd pixel 144B.

Therefore, according to a second embodiment of the present invention, utilize demultiplexer (for example, demultiplexer 162) to be provided to the i bar second data line DL with the data-signal separation and from one first data line D1.Yet the second embodiment of the present invention can provide desired data signal not to pixel 144.

Just, when 1 conducting of first switching element T, charging is corresponding to the voltage of data-signal in the holding capacitor Cst of the first pixel 144R.In this embodiment, when 1 conducting of first switching element T, each transistor M2 of the second and the

3rd pixel

144G and 144B also is sent to the sweep signal conducting of n bar sweep trace Sn.

When the transistor seconds M2 of second pixel 144G conducting, each gate terminal of the first and the 3rd transistor M1 and M3 is electrically connected to the 2nd second data line DL2.In this embodiment, the 2nd second data line DL2 is connected with capacitor parasitics etc., thereby the voltage of the data-signal that provides during (preceding field or previous frame) is provided the previous cycle.Therefore, the voltage that is applied to the gate terminal of the first and the 3rd transistor M1 and M3 is changed to the voltage of the data-signal that sends during the cycle formerly.Just, be changed to the voltage of the data-signal that sends during the cycle formerly by the initialized voltage of second initialize power of the second initialize power line Vint2.

Then, second switch device T2 is by the second control signal CS2 conducting.When second switch device T2 conducting, data-signal is sent to the 2nd second data line DL2 from the 1st first data line D1.Then, via the transistor seconds M2 of the second pixel 144G data-signal is sent to the source terminal of the 3rd transistor M3 from the 2nd second data line DL2.In this embodiment, the source terminal of the 3rd transistor M3 has been applied in corresponding to the current data voltage of signals, and gate terminal has been applied in corresponding to the past data voltage of signals.In this case, the 3rd transistor M3 is conducting when the current data voltage of signals is higher than the threshold voltage of past data voltage of signals and the 3rd transistor M3 only, otherwise ends.

Similarly, according to a second embodiment of the present invention, when demultiplexer (for example, when demultiplexer 162) operating, change the voltage of the gate terminal that each the 3rd transistor M3 that provides is provided in the second and the

3rd pixel

144G and 144B, thereby data-signal may not have the voltage of expectation, therefore is difficult to normally show desired images.In order to improve first and/or second exemplary embodiment, the invention provides active display as shown in figure 10.

Figure 10 is the planimetric map according to the active display of third embodiment of the invention.Below, identical numeral components identical.

With reference to Figure 10, comprise scanner driver 110, data driver 120, image display part 130, timing controller 150, Signal Separation piece 160, demultiplexer controller 170 and INIT block 200 according to the active display of third embodiment of the invention.

INIT block 200 comprises the initializer 202 of a plurality of i of being connected to bar second data line DL.Initializer 202 offered first initialize power every second data line DL before data-signal being sent to every second data line DL.

Shown in Figure 11 illustration, INIT block 200 comprises i initialisation switch device T4, T5 and T6, wherein i=3.Initialisation switch device T4, T5 and T6 are connected to the first initialize power line Vint1 jointly, and are connected to the corresponding second data line DL1, DL2 and DL3.And, in one embodiment, initialisation switch device T4, T5 and T6 conducting simultaneously, but end at different time each other, thus the first initialize power Vint1 is provided to the corresponding second data line DL1, DL2 and DL3.

A third embodiment in accordance with the invention, as shown in figure 12, initialisation switch device T4, T5 that provides in the initializer 202 and T6 can be adjacent to place with data switch device T1, T2 and T3 respectively.In this embodiment, no matter initialisation switch device T4, T5 and T6 whether respectively with data switch device T1, T2 and T3 is adjacent or from, all carry out identical operations.In this embodiment, purpose for example, initialisation switch device T4, T5 and T6 are shown as respectively and place adjacent to data switch device T1, T2 and T3.And therein under the situation that demultiplexer 162 and initializer 202 are arranged as shown in figure 12, demultiplexer 162 and initializer 202 can be referred to as hereinafter and be made demultiplexing circuit.

First switching element T 1 is provided between the 1st first data line D1 and the 1st the second data line DL1, and data-signal is provided to the 1st second data line DL1 from the first data line D1.And also with reference to Figure 14, first switching element T 1 is by the first control signal CS1 conducting (with reference to Figure 14) that provides from demultiplexer controller 170.

Second switch device T2 is provided between the 1st first data line D1 and the 2nd the second data line DL2, and data-signal is provided to the 2nd second data line DL2 from the 1st first data line D1.And second switch device T2 is by the second control signal CS2 conducting (with reference to Figure 14) that provides from demultiplexer controller 170.

The 3rd switching element T 3 is provided between the 1st first data line D1 and the 3rd the second data line DL3, and data-signal is provided to the 3rd second data line DL3 from the 1st first data line D1.And first switching element T 1 is by the 3rd control signal CS3 conducting (with reference to Figure 14) that provides from demultiplexer controller 170.

The 4th switching element T 4 is provided between the first initialize power line Vint1 and the 1st the second data line DL1, and first initialize power of the first initialize power line Vint1 is provided to the 1st second data line DL1.In this embodiment, the first initialize power line Vint1 has the voltage that is lower than the minimum voltage that can be applied to image display part 130.For example, be under the situation of 2V at the minimum voltage that can be applied to image display part 130, the first initialize power Vint1 is set to has the voltage that is lower than 2V.In fact, the first initialize power Vint1 is set to have and is lower than the voltage that the voltage that the transistorized threshold voltage that provides the pixel 140 obtains is provided by the minimum voltage from the data-signal that can be applied to image display part 130.Therefore, the 4th switching element T 4 is by the first initialization control signal Cb1 conducting (with reference to Figure 14) that provides from demultiplexer controller 170.

The 5th switching element T 5 is provided between the first initialize power line Vint1 and the 2nd the second data line DL2, and first initialize power of the first initialize power line Vint1 is provided to the 2nd second data line DL2.And the 5th switching element T 5 is by the second initialization control signal Cb2 conducting (with reference to Figure 14) that provides from demultiplexer controller 170.

The 6th switching element T 6 is provided between the first initialize power line Vint1 and the 3rd the second data line DL3, and first initialize power of the first initialize power line Vint1 is provided to the 3rd second data line DL3.And the 6th switching element T 6 is by the 3rd initialization control signal Cb3 conducting (with reference to Figure 14) that provides from demultiplexer controller 170.

In this embodiment, when sweep signal was sent to sweep trace S (for example, sweep trace Sn and sweep trace Sn-1), demultiplexer controller 170 was exported first, second and the 3rd control signal CS1, CS2 and CS3 successively.In Figure 14, the mistiming of wherein reserving L2 second round sends each control signal CS1 to CS3.And the first control signal CS1 falls behind period 1 L1 and is sent out after the sweep signal SS that sends sweep trace S (for example sweep trace Sn-1).And the 3rd control signal CS3 occurred early than period 1 L1 before the sweep signal SS of sweep trace (for example, sweep trace Sn-1) occurs.

When sending sweep signal SS, for synchronous with sweep signal SS, the demultiplexer 170 output first initialization control signal Cb1, second initialization control signal Cb2 and the 3rd initialization control signal Cb3.In Figure 14, the first initialization control signal Cb1 occurred before the first control signal CS1 is provided, thereby the first initialization control signal Cb1 and the first control signal CS1 are not overlapped.The second initialization control signal Cb2 occurred before the second control signal CS2 is sent out, thereby the second initialization control signal Cb2 and the second control signal CS2 are not overlapped.The 3rd initialization control signal Cb3 occurred before the 3rd control signal CS3 is sent out.Thus, before first to the 3rd switching element T 1, T2 and the T3 conducting that are connected respectively to the identical data line that is connected with T6 with the 4th to the 6th switching element T 4, T5, the 4th to the 6th switching element T 4, T5 and T6 end.

In Figure 11 and Figure 12, switching element T 1 to T6 is illustrated as p type switching device, but the invention is not restricted to p type switching device, in fact, switching element T 1 to T6 be set to have with pixel 140 in the identical type of transistor that provide and that be connected to the second data line DL.For example, be under the situation of p type at the transistor that is connected to the second data line DL, switching element T 1 to T6 also is formed p type switching device.On the other hand, be under the situation of n type at the transistor that is connected to the second data line DL, switching element T 1 to T6 also is formed n type switching device.

Figure 13 is the connecting circuit figure between the pixel of the initializer of Figure 12 and demultiplexer and Fig. 4.Purpose for example, a demultiplexer is depicted as with red (R), green (G) and blueness (B) pixel and is connected; Just, i equals 3.And the waveform of the drive signal of the sweep trace, data line and the demultiplexer that provide in the active display that offers according to third embodiment of the invention is provided Figure 14.

With reference to Figure 13 and 14, when sweep signal SS is sent to (n-1) sweep trace Sn-1, each the 6th transistor M6 conducting of

pixel

142R, 142G and 142B.Therefore, when the 6th transistor M6 conducting, the gate terminal of holding capacitor Cst and the first transistor M1 is connected to (n-1) sweep trace Sn-1.Just, when the 6th transistor M6 conducting, sweep signal SS is provided to the gate terminal of each holding capacitor Cst and each the first transistor M1, thus the gate terminal of each holding capacitor Cst of initialization and each the first transistor M1.

Then, sweep signal SS is sent to n bar sweep trace Sn.When sweep signal SS is sent to n bar sweep trace Sn, each transistor seconds M2 of

pixel

142R, 142G and 142B and each the 3rd transistor M3 conducting.And, synchronous with the sweep signal SS that is sent to n bar sweep trace Sn, send first to the 3rd initialization control signal Cb1, Cb2 and Cb3.Therefore, when sending first to the 3rd initialization control signal Cb1, Cb2 and Cb3, the 4th, the 5th and the 6th switching element T 4, T5 and T6 conducting.

When the 4th, the 5th and the 6th switching element T 4, T5 and T6 conducting, the voltage of first initialize power of the first initialize power line Vint1 is applied to the 1st to the 3rd second data line DL1, DL2 and DL3.Here, data line DL1, DL2 and DL3 are applied to each first node N1 of

pixel

142R, 142G and 142B from the 1st to the 3rd second with the voltage of the first initialize power Vint1.In this embodiment, because the gate terminal of each the first transistor M1 of

pixel

142R, 142G and 142B is sent to the sweep signal SS initialization of (n-1) bar sweep trace Sn-1, therefore kept voltage corresponding to sweep signal SS.

When first initialize power of the first initialize power line Vint1 is provided for first node N1, the first transistor M1 conducting or end.In fact, the voltage of the initialize power of power lead Vint1 is determined whether conducting or end of the first transistor M1.In this embodiment, the initialize power of power lead Vint1 is set to have and is lower than by deduct the voltage that the transistorized threshold voltage that provides obtains voltage in pixel 140 from the minimum voltage of the data-signal that can be applied to image display part 130.

For example, when the first transistor M1 conducting, the voltage that is applied to the gate terminal of the first transistor M1 is changed into the voltage of the initialize power of power lead Vint1.And when the first transistor M1 ended, the voltage that is applied to the gate terminal of the first transistor M1 remained on the voltage of sweep signal SS.

Then, send the first control signal CS1, thus conducting first switching element T 1.In this embodiment, before sending the first control signal CS1, interrupt the first initialization control signal Cb1.On the other hand, the second and the 3rd initialization control signal Cb2 and Cb3 continue with the first control signal CS1 overlapping.

Send the first control signal CS1, and therefore first switching element T, 1 conducting.When 1 conducting of first switching element T, data-signal is sent to first node N1 at the first pixel 142R from the 1st first data line D1 via transistor seconds M2.When the voltage corresponding to data-signal is applied to first node N1, the first transistor M1 conducting.In other words, the voltage that is applied to the gate terminal of the first transistor M1 is set to the voltage of initialize power of power lead Vint1 or the voltage of sweep signal, therefore the first transistor M1 conducting when data-signal is sent to first node N1.When the first transistor M1 conducting, data-signal is sent to the end of holding capacitor Cst via the first and the 3rd transistor M1 and M3 from first node N1.At this moment, use voltage that holding capacitor Cst is charged corresponding to data-signal.

Then, first switching element T 1 is ended, and second switch device T2 is by the second control signal CS2 conducting.In this embodiment, before sending the second control signal CS2, interrupt the second initialization control signal Cb2.On the other hand, the 3rd initialization control signal Cb3 continues with the second control signal CS2 overlapping.

Send the second control signal CS2, and therefore second switch device T2 conducting.When second switch device T2 conducting, data-signal is sent to first node N1 at the second pixel 142G from the 1st first data line D1 via transistor seconds M2.When the voltage corresponding to data-signal is applied to first node N1, the first transistor M1 conducting.In other words, the voltage that is applied to the gate terminal of the first transistor M1 is set to the voltage of initialize power of power lead Vint1 or the voltage of sweep signal, thus the first transistor M1 conducting when data-signal is sent to first node N1.When the first transistor M1 conducting, data-signal is sent to the end of holding capacitor Cst via the first and the 3rd transistor M1 and M3 from first node N1.At this moment, use voltage that holding capacitor Cst is charged corresponding to data-signal.

Then, second switch device T2 ends, and the 3rd switching element T 3 is by the 3rd control signal CS3 conducting.In this embodiment, before sending the 3rd control signal CS3, interrupt the 3rd initialization control signal Cb3.

Send the 3rd control signal CS3, and therefore the 3rd switching element T 3 conductings.When 3 conductings of the 3rd switching element T, data-signal is sent to first node N1 at the 3rd pixel 142B from the 1st first data line D1 via transistor seconds M2.When the voltage corresponding to data-signal is applied to first node N1, the first transistor M1 conducting.In other words, the voltage that is applied to the gate terminal of the first transistor M1 is set to the voltage of initialize power of power lead Vint1 or the voltage of sweep signal, thus the first transistor M1 conducting when data-signal is sent to first node N1.When the first transistor M1 conducting, data-signal is sent to the end of holding capacitor Cst via the first and the 3rd transistor M1 and M3 from first node N1.At this moment, use voltage that holding capacitor Cst is charged corresponding to data-signal.

As mentioned above, according to the present invention, data-signal when sending to i bar second data-signal, one first data line D1 is being utilized demultiplexer 162.And, additionally provide the initialisation switch device corresponding to the data switch device, and first initialize power of the first initialize power line Vint1 is provided, till data-signal is sent to every second data line DL, thereby show desired images.

Figure 15 is the connecting circuit figure between the pixel of the initializer of Figure 12 and demultiplexer and Fig. 7.Purpose for example, a demultiplexer is depicted as with red (R), green (G) and blueness (B) pixel and is connected.

Refer to figs. 14 and 15, when sweep signal SS is sent to (n-1) sweep trace Sn-1, each the 4th transistor M4 conducting of

pixel

144R, 144G and 144B.Therefore, when the 4th transistor M4 conducting, each gate terminal of the end of holding capacitor Cst and the first and the 3rd transistor M1 and M3 is connected to second initialize power of the second initialize power line Vint2.Just, when the 4th transistor M4 conducting, second initialize power of the second initialize power line Vint2 is provided to each gate terminal of an end and the first and the 3rd transistor M1 and the M3 of holding capacitor Cst, thus each gate terminal of the end of initialization holding capacitor Cst and the first and the 3rd transistor M1 and M3.In this embodiment, second initialize power of the second initialize power line Vint2 is set to the voltage with voltage that threshold voltage that transistor M3 is provided the minimum voltage that is lower than by the data-signal that provides from data driver 120 obtains.And second initialize power of the second initialize power line Vint2 is set to the voltage of voltage that has equaling or be different from first initialize power of the first initialize power line Vint1.

Then, sweep signal SS is sent to n bar sweep trace Sn.When sweep signal being sent to n bar sweep trace Sn, each transistor seconds M2 conducting of

pixel

144R, 144G and 144B.And, synchronous with the sweep signal SS that is sent to Sn bar sweep trace, send first to the 3rd initialization control signal Cb1, Cb2 and Cb3.When sending first to the 3rd initialization control signal Cb1, Cb2 and Cb3, the 4th, the 5th and the 6th switching element T 4, T5 and T6 conducting.

When the 4th, the 5th and the 6th switching element T 4, T5 and T6 conducting, the voltage of first initialize power of the first initialize power line Vint1 is applied to the 1st to the 3rd second data line DL1, DL2 and DL3.Here, each source terminal of the 3rd transistor M3 that provides among

pixel

144R, 144G and 144B is provided for data line DL1, DL2 and DL3 from the 1st to the 3rd second with the voltage of the first initialize power Vint1.In this embodiment, because the gate terminal of the 3rd transistor M3 by the second initialize power initialization of the second initialize power line Vint2, has therefore kept the voltage of second initialize power of the second initialize power line Vint2.

When first initialize power of the first initialize power line Vint1 is provided for the source terminal of the 3rd transistor M3, the 3rd transistor M3 conducting or end.In fact, the voltage of the initialize power of the first initialize power line Vint1 is determined whether conducting or end of the 3rd transistor M3.In this embodiment, when the 3rd transistor M3 conducting, the change in voltage that is applied to the gate terminal of the 3rd transistor M3 be the first initialize power line Vint1 the voltage of first initialize power.And when the 3rd transistor M3 ended, the voltage that is applied to the gate terminal of the 3rd transistor M3 remained the voltage of second initialize power with second initialize power line Vint2.

When 1 conducting of first switching element T, data-signal is sent to the source terminal of the 3rd transistor M3 that provides from the 1st first data line D1 among the first pixel 144R via first switching element T 1.At this moment, because the gate terminal of the 3rd transistor M3 is by the first or second initialize power initialization of the first or second initialize power line Vint1 or Vint2, therefore the 3rd transistor M3 conducting.When the 3rd transistor M3 conducting, data-signal is sent to the gate terminal of the 3rd transistor M3, just, the end of capacitor Cst.Simultaneously, use voltage that holding capacitor Cst is charged corresponding to data-signal.And, except voltage, use corresponding to the threshold voltage according of the first transistor M1 holding capacitor Cst is charged corresponding to data-signal.

When second switch device T2 conducting, data-signal is sent to the source terminal of the 3rd transistor M3 that provides from the 1st first data line D1 among the second pixel 144G via second switch device T2.At this moment, because the gate terminal of the 3rd transistor M3 is by the first or second initialize power initialization of the first or second initialize power line Vint1 or Vint2, therefore the 3rd transistor M3 conducting.When the 3rd transistor M3 conducting, data-signal is sent to the gate terminal of the 3rd transistor M3, just, the end of capacitor Cst.At this moment, use voltage that holding capacitor Cst is charged corresponding to data-signal.And, except voltage, use corresponding to the threshold voltage according of the first transistor M1 holding capacitor Cst is charged corresponding to data-signal.

When 3 conductings of the 3rd switching element T, data-signal is sent to the source terminal of the 3rd transistor M3 that provides from the 1st first data line D1 among the 3rd pixel 144B via the 3rd switching element T 3.At this moment, because the gate terminal of the 3rd transistor M3 is by the first or second initialize power initialization of the first or second initialize power line Vint1 or Vint2, therefore the 3rd transistor M3 conducting.When the 3rd transistor M3 conducting, data-signal is sent to the gate terminal of the 3rd transistor M3, just, the end of memory capacitor Cst.At this moment, use voltage that holding capacitor Cst is charged corresponding to data-signal.And, except voltage, use corresponding to the threshold voltage according of the first transistor M1 holding capacitor Cst is charged corresponding to data-signal.

As mentioned above, according to the present invention, data-signal when sending to i bar second data-signal, one first data line D1 is being utilized demultiplexer 162.And, additionally provide the initialisation switch device corresponding to the data switch device, and first initialize power of the first initialize power line Vint1 is provided, till data-signal is sent to every second data line DL, thereby stably shows desired images.

In addition, as shown in figure 14, when sweep signal SS was provided, initialisation switch device T4, T5 and T6 are set to had the turn-on cycle that differs from one another.In the middle of initialisation switch device T4, T5 and T6, initialisation switch device T4, the T5 and the T6 that have the logical cycle of short-range missile when sweep signal is provided should have the wideest channel width.

Figure 16 is the figure corresponding to the channel width of the turn-on cycle of initialisation switch device.In Figure 16, purpose for example, the 4th initialisation switch device T4 is depicted as has the shortest turn-on cycle, and simultaneously, the 6th initialisation switch device T6 is depicted as has the longest turn-on cycle.

With reference to Figure 16, in one embodiment of the invention, the 4th switching element T 4 with logical cycle of short-range missile has the channel width of about 60 μ m, so that first initialize power (perhaps voltage) of the first initialize power line Vint1 was provided in the expected time that is approximately 5 μ s.And, in one embodiment, have that the 6th switching element T 6 of long turn-on cycle has the channel width of about 10 μ m, so that first initialize power (perhaps voltage) of the first initialize power line Vint1 is provided in the expected time that is approximately 25 μ s.In addition, in one embodiment, the 5th switching element T 5 of middle turn-on cycle with turn-on cycle of the 4th and the 6th switching element T 4 and T6 has the channel width of about 20 μ m, so that first initialization voltage of the first initialize power line Vint1 was provided in the expected time that is approximately 13 μ s.

As shown in figure 16, initialisation switch device T4 to T6 should have first initialization voltage to the second data line DL that enough channel widths fully provide the first initialize power line Vint1, thereby guarantees stable operation.In one embodiment, have identical channel width in order to make all initialisation switch device T4 to T6, the 5th is adjusted to the 6th initialisation switch device T5 and T6 and has the channel width identical with the 4th switching element T 4.

Yet when initialisation switch device T4 to T6 had identical channel width, the space that initialisation switch device T4 to T6 occupies increased, thereby is difficult to freely design its circuit.In addition, because the space that occupies of initialisation switch device T4 to T6 increases, so the space that peripheral circuit occupies reduces, thereby damaged reliability.Therefore, according to embodiments of the invention, differently set initialisation switch size of devices (for example channel width) corresponding to the turn-on cycle of initialisation switch device T4 to T6.

For example, as shown in figure 17, the 4th switching element T 4 has maximum size, and it has the shortest turn-on cycle when sweep signal is provided.And the 6th switching element T 6 has minimum size, and it has the longest turn-on cycle when sweep signal is provided.Therefore, differently set the size of initialisation switch device T4 to T6 corresponding to the turn-on cycle of initialisation switch device T4 to T6, so the area that initialisation switch device T5 and T6 occupy reduces, thereby guaranteed the freedom of circuit design.In addition, owing to afterwards the initialisation switch size of devices that is switched on was reduced, therefore the voltage (perhaps electric current) that provides from the initialisation switch device descends, thereby has reduced power consumption.

Experimentally, with reference to Figure 18, when sweep signal SS was provided, the electric current that is provided for the pixel 140 that receives data-signal subsequently was higher than the electric current of the pixel 140 that is provided for previous reception data-signal.Therefore, suppose that each demultiplexer 162 is connected with red (R) pixel, green (G) pixel and blue (B) pixel, consider the luminescence efficiency of luminescent device OLED, the order that provides of first to the 3rd control signal CS1 to CS3 is provided as shown in figure 18.

More specifically, to charge corresponding to the voltage of data-signal holding capacitor Cst to the pixel 140 that when sweep signal SS is provided, receives data-signal in advance.Yet, when sweep signal SS is provided corresponding to the undertension of data-signal to be provided to the holding capacitor Cst of the pixel 140 that receives data-signal subsequently, therefore provide high relatively voltage to it.Just, even data-signal corresponding to same levels is provided, the pixel 140 that receives data-signal subsequently also receives higher electric current and is used for its luminescent device OLED.

In addition, set the luminescence efficiency of luminescent device OLED with the order of green light emitting device OLED, emitting red light device OLED and blue luminescent device OLED.Therefore, according to embodiments of the invention, as shown in figure 18, at first provide the second control signal CS2, thereby the green data signal at first is sent to the green light emitting device OLED with high relatively luminescence efficiency.And, provide the 3rd control signal CS3 at last, thereby data-signal is sent to the blue luminescent device OLED with low relatively luminescence efficiency at last.Therefore, when the data-signal that provides corresponding to same levels, minimum current is provided to the green light emitting device OLED with high relatively luminescence efficiency, but maximum current is provided to the blue luminescent device OLED with low relatively luminescence efficiency.Just, according to embodiments of the invention, consider that the luminescence efficiency of luminescent device OLED is provided by providing in proper order of first to the 3rd control signal CS1 to CS3, thereby come display image with the white balance of improving.

As mentioned above, the invention provides a kind of demultiplexing circuit, use its active display and driving method thereof, wherein utilize demultiplexer with data-signal from an output line offer i bar data line, thereby reduce production cost.And, each demultiplexer is provided i initialization transistor in addition, and initialization transistor keeps conducting, till the data transistor conducting that is connected to the identical data line that is connected with initialization transistor, thereby the desired data signal is offered pixel.And according to embodiments of the invention, the transistor that will provide in demultiplexer (for example, data transistor) is set at the order that has ON time or consider the luminescence efficiency of luminescent device, thereby with improved picture quality display image.

And, according to embodiments of the invention, differently set the initialisation switch size of devices according to ON time, therefore can reduce the initialisation switch size of devices, thereby guarantee the freedom of circuit design.And, reduced the initialisation switch size of devices, therefore the voltage (perhaps electric current) that provides via the initialisation switch device reduces, thereby has reduced power consumption.

Although illustrated and described embodiments of the invention, but those of ordinary skill in the art is to be understood that, under the condition that does not deviate from principle of the present invention and spirit, can change in these embodiments, scope of the present invention is by claim and equivalent definition thereof.

Claims

1. A light-emitting display comprising:

a scan driver, configured to sequentially provide scan signals to the scan lines;

a data driver provided with a plurality of output lines for providing a plurality of data signals to each output line while being supplied with a scan signal;

an image display part including a plurality of pixels located in an area divided by a scan line and a plurality of data lines;

a plurality of demultiplexers, each demultiplexer coupled to a corresponding one of the output lines and comprising a plurality of data transistors adapted to provide respective data signals from a corresponding one of the output lines to ones of the plurality of data lines more than one data line; and

a plurality of initializers including a plurality of initialization transistors adapted to apply a predetermined voltage to each of the plurality of data lines,

Wherein, each demultiplexer is connected with at least three data lines, and the at least three data lines are respectively connected to a red pixel including a red light emitting device, a green pixel including a green light emitting device, and a blue pixel including a blue light emitting device ,and

Wherein, the order of turning on the data transistors receiving a corresponding one of the data signals is set in priority to a selected one among the red light emitting device, the green light emitting device, and the blue light emitting device having relatively high light emitting efficiency.

2. The light emitting display of claim 1, wherein each pixel comprises a plurality of pixel transistors, and at least one pixel transistor is connected to act as a diode.

3. The light emitting display of claim 1, further comprising a demultiplexer controller for controlling the demultiplexer to provide a plurality of data signals from each output line to a plurality of data lines.

4. The light emitting display of claim 3, wherein the data transistors provided in each demultiplexer are equal in number to the initialization transistors provided in each initializer.

5. The light emitting display of claim 4, wherein the demultiplexer controller provides a control signal to sequentially turn on the plurality of data transistors while at least one scan signal is supplied.

6. The light emitting display of claim 5, wherein the demultiplexer controller provides an initialization control signal to turn on an initialization transistor in each demultiplexer before turning on a data transistor in a corresponding one of the demultiplexers .

7. The light emitting display of claim 6, wherein the demultiplexer controller provides an initialization control signal to turn off each initialization transistor in each initializer at different times.

8. The light emitting display of claim 7, wherein the at least one initialization transistor is turned off before a corresponding one of the data transistors connected to a corresponding one of the data lines connected to the at least one initialization transistor is turned on.

9. The light emitting display of claim 2, wherein the predetermined voltage is set to be supplied to at least one pixel transistor functioning as a diode, and to turn on the at least one pixel transistor functioning as a diode.

10. The emissive display of claim 2, wherein each pixel comprises:

Light emitting devices;

a first transistor for controlling current to be supplied to the light emitting device according to at least one data signal;

a storage capacitor connected to the first transistor for storing a corresponding voltage of at least one data signal; and

A second transistor connected to an n-th scan line of the scan lines and a corresponding one of the data lines for sending at least one data signal from the corresponding one of the data lines to the storage capacitor, where n is a natural number.

11. The light emitting display of claim 10, wherein the data transistor, initialization transistor, and second transistor are the same type of transistor.

12. The emissive display of claim 10, wherein each pixel further comprises:

a third transistor connected between the second transistor and the first transistor, having a gate terminal and a drain terminal connected to each other;

a fourth transistor controlled by the (n-1)th scan line of the scan lines, which is connected to the third transistor and the second initialization power supply line; and

A fifth transistor controlled by the (n-1)th scan line is connected to the light emitting device and the first transistor.

13. The emissive display of claim 10, wherein each pixel further comprises:

a third transistor controlled by the nth scan line, which is connected to the gate terminal and the drain terminal of the first transistor;

fourth and fifth transistors connected to the light emission control line; and

A sixth transistor having a gate terminal and a drain terminal connected to the (n-1)th scan line of the scan lines, and a source terminal connected to the gate terminal of the first transistor.

14. The light emitting display of claim 10, wherein the predetermined voltage is lower than a lowest voltage of at least one data signal supplied from the data driver.

15. The light-emitting display of claim 10, wherein the predetermined voltage is lower than the voltage provided in each pixel by subtracting the lowest voltage of at least one data signal provided by the data driver and connected to function as a diode. The voltage obtained by obtaining the threshold voltage of at least one pixel transistor.

16. The light emitting display of claim 7, wherein each initialization transistor is set to have a size corresponding to a turn-on period.

17. The light emitting display according to claim 16, wherein each initialization transistor includes a channel width, and the channel width of each initialization transistor is set to become narrower.

18. The light-emitting display according to claim 1, wherein the order of turning on the data transistors is set to firstly provide a corresponding one of the data signals to the green light-emitting device, and lastly provide a corresponding one of the data signals to the blue light-emitting device. device.

19. A signal separation circuit, comprising:

a plurality of demultiplexers coupled respectively to a plurality of output lines of the data driver and comprising a plurality of data transistors adapted to provide a data signal from each output line to more than one of the plurality of data lines ;and

a plurality of initializers including a plurality of initialization transistors adapted to provide a predetermined voltage to each of the plurality of data lines,

20. The demultiplexing circuit of claim 19, wherein the data transistors provided in each demultiplexer are equal in number to the initialization transistors provided in each initializer.

21. The demultiplexing circuit of claim 20, wherein the data transistors provided in each demultiplexer are sequentially turned on so as to supply a plurality of data signals to a plurality of data lines.

22. The demultiplexing circuit according to claim 21, wherein the initialization transistor provided in each initializer is turned on before the data transistor in a corresponding one of the demultiplexers is turned on, and the initialization transistor provided in each initializer is turned on. The initialization transistors of are turned off at different times.

23. The signal separation circuit of claim 22, wherein at least one initialization transistor is turned off before a corresponding one of the data transistors connected to a corresponding one of the data lines connected to the at least one initialization transistor is turned on.

24. The signal splitting circuit of claim 19, wherein the predetermined voltage is lower than a lowest voltage of at least one data signal supplied to at least one data line.

25. The signal separation circuit according to claim 23, wherein each initialization transistor includes a channel width, and the channel width of each initialization transistor is set to vary as a turn-on period of each initialization transistor becomes longer. narrower.

26. A method of driving a light-emitting display, the method comprising:

providing scanning signals to multiple scanning lines in sequence;

providing a plurality of data signals to each output line of the data driver while providing the scan signal;

sequentially turning on a plurality of data transistors connected to the respective output lines to provide a plurality of data signals to the plurality of data lines; and

turning on a plurality of initialization transistors connected to the plurality of data lines before turning on the data transistors so as to supply initialization power to the plurality of data lines,

wherein each data signal from a corresponding one of the output lines is provided to more than one of the plurality of data lines,

Wherein, each output line is connected to at least three data transistors, and the at least three data lines connected to the at least three data transistors are respectively connected to a red pixel including a red light-emitting device, a green pixel including a green light-emitting device, and a blue pixel including a green light-emitting device. the blue pixel connection of the light emitting device, and

Wherein, the turn-on sequence of at least the three data transistors is set based on the luminous efficiencies of the red light emitting device, the green light emitting device and the blue light emitting device, with higher luminous efficiency preceding lower luminous efficiency.

27. The method of claim 26, wherein the initialization transistors are turned off at different times.

28. The method of claim 27, wherein at least one initialization transistor is turned off before a corresponding one of the data transistors connected to a corresponding one of the data lines connected to the at least one initialization transistor is turned on.

29. The method according to claim 26, wherein the turn-on sequence of at least the three data transistors is set to firstly provide a corresponding one of the data signals to the green light-emitting device, and finally supply a corresponding one of the data signals to the green light emitting device. Give blue light emitting device.

30. The method of claim 26, wherein the plurality of data lines is larger in number than the plurality of output lines.