CN100470468C - Method for automatically converting high-order program language into hardware description language - Google Patents

Abstract

The invention relates to a method for automatically converting a high-level program language into a hardware description language, which can generate the corresponding hardware description language by converting functions described by the high-level program language through a three-stage conversion mechanism. In the first stage, the original program code of high-level program language is converted into extended active diagram, then the second stage converts the active diagram into hardware component diagram, and finally the third stage generates corresponding signal connection of VHDL component according to the on-line of the hardware component diagram, and outputs the entity and structure of VHDL to a file in character string mode to complete the whole conversion.

Description

Method for automatically converting high-level programming language into hardware description language

technical field

The invention relates to a method for automatically converting a high-level programming language into a hardware description language (VHDL), especially a method for converting an original program code (source code) into an extended activity diagram (Extended Activity Diagram, EAD). A method of converting the activity diagram into a hardware component graph (Hardware Component Graph, HCG) and converting the hardware component graph into a hardware description language, and automatically converting a high-level programming language into a hardware description language (VHDL).

Background technique

Traditional high-level programming languages (such as Java, C, C++, etc.) cannot directly convert the functions described in the source code into corresponding hardware description languages (such as VHDL). Since the traditional hardware description language (such as: VHDL) is not suitable for directly describing the program logic and execution flow of the high-level programming language, it is impossible to directly convert the functions described in the high-level programming language to the corresponding hardware description language, resulting in Design troubles. And because there are many kinds of high-level programming languages, even though the functions of the designed programs are the same, the complete execution process cannot be unified due to the characteristics of the programming languages, causing troubles in the design of hardware components. Therefore, known methods cannot combine high-level The functions described in the programming language are directly converted into the corresponding hardware description language, and there is a need for improvement.

Contents of the invention

The purpose of the present invention is to provide a method for automatically converting a high-level programming language into a hardware description language.

In order to achieve the above purpose. The method for automatically converting a high-level programming language into a hardware description language provided by the present invention comprises the following steps:

(A) reading the source code of a high-level programming language;

(B) converting the source code of the high-level programming language into an extended activity diagram, wherein step (B) includes the following sub-steps:

(B1) read the source code of a line of high-level programming language;

(B2) When the read source code is not a narrative instruction, convert the non-narrative instruction into a corresponding subactivity diagram, and then perform step (B1);

(B3) If the read source code is a narration command, and when there is a narration in front of the narration command, convert the narration into a sub-activity diagram;

(B4) generating a selection node;

(B5) generating two intermediary points, the two intermediary points connecting the selected node;

(B6) Converting the narrative into corresponding sub-activity diagrams;

(B7) generating a merge node to merge sub-activity diagrams;

(B8) Connect the sub-activity diagram generated by the conversion of the narrative to the right intermediate point;

(B9) connecting the sub-activity diagram generated by the transformation of the narrative to the merge node; and

(B10) judging whether there is still an instruction that has not been converted into a sub-activity diagram, if there is still, perform step (B1), otherwise, output a complete activity diagram;

(C) converting the extended activity diagram into a hardware component diagram;

(D) converting the hardware component diagram into a hardware description language; and

(E) Outputting the hardware description language.

The method for automatically converting a high-level programming language into a hardware description language, wherein the high-level programming language is Java, C, or C++ programming language.

In the method for automatically converting a high-level programming language into a hardware description language, the extended activity represents a flow control chart.

The method for automatically converting a high-level programming language into a hardware description language, wherein the extended activity diagram includes: start (start), end (end), intermediate point (curve point), micro-operation (micro-operation), branch Fork (fork), link (join), selection (select), merge (merge) a total of eight kinds of nodes.

In the method for automatically converting a high-level programming language into a hardware description language, the hardware component diagram is to represent hardware components and the connection relationship between hardware components.

In the method for automatically converting a high-level programming language into a hardware description language, the hardware component diagram includes three types: a start node, an end node and a component node.

The method for automatically converting a high-level programming language into a hardware description language, wherein the hardware description language is VHDL or Verilog.

The method for automatically converting a high-level programming language into a hardware description language, wherein in step (A3), the narration instructions include: for, while, do, if, and switch instructions.

The method for automatically converting a high-level programming language into a hardware description language, wherein step (C) includes the following sub-steps:

(C1) read a sub-activity diagram in the extended activity diagram, and when all the sub-activity diagrams in the extended activity diagram have been read, perform step (C5);

(C2) When it is judged that the type of the read sub-activity diagram is one of fork, link, or merge, directly convert it into a corresponding hardware component diagram, and execute step (C1);

(C3) When it is judged that the read sub-activity diagram is a micro-operation type, perform syntax analysis conversion on the micro-operation sub-activity diagram, and convert the micro-operation sub-activity diagram into a corresponding hardware component diagram, and then perform the steps (C1);

(C4) When it is judged that the read sub-activity diagram is a selection type, after analyzing the marks on the output terminals on the hardware component diagrams, then perform syntax analysis and conversion, and convert the selection sub-activity diagram into hardware After the component diagram, step (C1) is performed; and

(C5) Connecting the input and output ends of the hardware component diagrams to output a complete hardware component diagram.

The method for automatically converting a high-level programming language into a hardware description language, wherein step (D) includes the following sub-steps:

(D1) reading a hardware component diagram, wherein the hardware component diagram includes a plurality of sub-hardware component diagrams, converting the hardware component diagram into a modified hardware component diagram to perform hardware description language conversion;

(D2) finding a starting node of the hardware component graph to obtain a corresponding sub-hardware component graph;

(D3) analyzing the information of the start node to add input and output components to generate hardware description language entities until all start nodes are analyzed;

(D4) judging the type of the node in the hardware component diagram, generating a corresponding hardware description language object, and writing the relevant information into the architecture of the hardware description language;

(D5) According to the connection of the hardware component diagram, generate the signal connection of the corresponding hardware description language component; and

(D6) Outputting the entity and structure of the hardware description language to a file in the form of character strings.

In the method for automatically converting a high-level programming language into a hardware description language, in step (C4), a component calling method is used to generate a corresponding hardware description language object.

The method for automatically converting a high-level programming language into a hardware description language, wherein in step (C1), further includes converting the hardware component diagram into a revised hardware component diagram, so as to perform the hardware description language conversion.

The method that the high-level programming language (for example: Java, C, C ++) of the present invention is automatically converted into the hardware description language (VHDL) can be by the conversion mechanism of three stages, and the function described in the high-level programming language is directly converted into the corresponding It is not limited to the type of high-level programming language, and can unify the complete execution process without causing troubles in the design of hardware components.

Description of drawings

FIG. 1 is a three-stage conversion process of directly converting a high-level programming language into a hardware description language in a preferred embodiment of the present invention.

Fig. 2 is an activity diagram defined in UML of a preferred embodiment of the present invention.

Fig. 3 is an activity diagram defined in the EAD of a preferred embodiment of the present invention.

FIG. 4 is a flow chart of converting source code into EAD in a preferred embodiment of the present invention.

Fig. 5 is a complete conversion process of converting source code into EAD in a preferred embodiment of the present invention.

FIG. 6A is a JAVA program of a preferred embodiment of the present invention.

FIG. 6B is an EAD corresponding to a JAVA program in a preferred embodiment of the present invention.

FIG. 7A is a start node diagram of a preferred embodiment of the present invention.

Fig. 7B is an end node diagram of a preferred embodiment of the present invention.

FIG. 7C is a component node diagram of a preferred embodiment of the present invention.

FIG. 7D is a control path node of a preferred embodiment of the present invention.

FIG. 7E is a data path node of a preferred embodiment of the present invention.

FIG. 8 is a flowchart of EAD conversion and hardware components according to a preferred embodiment of the present invention.

Fig. 9 is a graph of HCG corresponding to EAD in a preferred embodiment of the present invention.

FIG. 10 is a flow chart of converting the hardware component graph (HCG) into VHDL hardware description language in a preferred embodiment of the present invention.

FIG. 11 is a schematic diagram of a Java adder in a preferred embodiment of the present invention.

FIG. 12 is a schematic diagram of a hardware component diagram corresponding to a Java adder in a preferred embodiment of the present invention.

13 , 14 , 15 , 16 , and 17 are schematic diagrams of the modification process of the hardware component diagram in a preferred embodiment of the present invention.

18 , 19 , 20 , 21 , 22 , 23 , 24 , and 25 are schematic diagrams of converting the hardware component diagrams of a preferred embodiment of the present invention into VHDL program codes.

Detailed ways

Because traditional methods cannot directly convert high-level programming languages into hardware description languages, the present invention proposes a three-stage conversion method. As shown in Figure 1, high-level programming languages (such as: Java, C, C++) The described function is converted into an extended activity diagram (Source code→EAD), an extended activity diagram is converted into a hardware component diagram (EAD→HCG), and a hardware component diagram is converted into a hardware description language (HCG→VHDL) through the original program code. Stage conversion, and the high-level programming language is automatically converted into a hardware description language. As shown in Figure 1, in the first stage (Sourcecode→EAD), first read the source code of a high-level programming language (step S101), and convert the original program code of the high-level programming language into an extended activity diagram (step S102), then, enter the second stage (EAD → HCG), convert the extended activity diagram into a hardware component diagram (step S103), and finally, carry out the third stage (HCG → VHDL), according to the connection of the hardware component diagram, generate the corresponding Corresponding hardware description language (signal connection of VHDL components) (step S104), and export the entity and structure of VHDL to a file in character string mode, generate corresponding hardware description language (for example: VHDL program code) (step S105 ).

As mentioned above, in the first stage, the original program code of the high-level programming language must be converted into an intermediate format—Activity Diagram (AD), AD is a description diagram of a process, please refer to Figure 2 Shown as the activity diagram defined in UML (Unified Modeling Language, UML), it contains five kinds of component diagrams: Action state, fork, join, select and merge, in the present invention, in order to keep the required information of some programs , therefore, some components of AD must be modified, and the activity diagram used is called Extended activity diagram (EAD), as shown in Figure 3.

As shown in Figure 3, EAD is a control graph used to convert the source code of a high-level language into a corresponding process, which is composed of a plurality of nodes (node), and different nodes are combined to form a sub-activity graph (sub -graph), each sub-activity graph contains three parts: start, execution and end. In this embodiment, a variety of different nodes are defined. The various nodes are described one by one below:

1. Start (start) node: indicates the beginning of a sub-activity graph;

2. End (end) node: indicates the end of a sub-activity graph;

3. Intermediate point (curve point) node: It represents the connection of two directional connection lines (edge), which has no actual impact on execution, and is usually used for temporary purposes to facilitate the conversion process;

4. Micro-operation node: represents the processing of an expression statement or expression;

5. Fork node: means parallel execution;

6. Join node: It means that only when all the micro-operations arrive, the output signal will be issued;

7. Select node: indicates that after decoding, an appropriate output signal will be selected and sent; and

8. Merge (merge) node: Indicates that the input signals are combined and then output.

Each of the above nodes is regarded as an object, and two data types are recorded in the object to represent the node (In-Node) connected to itself and the node (Out-Node) to be connected to itself, and the node type will be Changes with the grammar, when parsing each piece of grammar, a corresponding sub-activity diagram will be generated, and the In-Node and Out-Node of the sub-activity diagram will be recorded for the connection of other sub-activity diagrams. According to this connection method, the generation of sub-activity diagrams in each syntax also uses the same method. After connecting each sub-activity diagram, the program source code can be converted into a corresponding activity diagram, and the program logic and execution flow of the source code can be presented in a visual way.

Figure 4 shows the flow of automatic conversion of high-level programming language into extended activity diagrams. As shown in FIG. 4 , the JAVA program language is taken as an example to convert the JAVA program implementation into an extended activity diagram. It uses the Java standard grammar specification defined by JavaCC (Java Compiler Compiler, JavaCC) as the basis (using JDK (Java Development Kit) 1.5), and adds a Java program to the grammar file of JavaCC to generate a modified Java grammar file . And JavaCC generates the Java Parser (Java Parser) category and other categories that the Java Parser needs to use based on the Java grammar file, and the generated Java Parser category can provide conversion from Java source code to the corresponding EAD function. In this embodiment, the Java parser category is integrated in a computer-aided circuit design software, so that the software has the function of converting the Java source code to EAD, and then, the complete Java source code is imported into the Java Parser, and the Java Parser will According to different tokens in the program, corresponding to the newly generated EAD instructions in the grammar file, and then convert the EAD graphics.

The present invention proposes a complete conversion process, as shown in Figure 5, when the original code is automatically converted into a corresponding extended activity diagram, at first, read the original code of a line of high level language (step S501), then, determine whether the type of the source code is a statement instruction (step S502), in this embodiment, the statement instruction includes: for, while, do, if, switch instructions. When the type of the source code is not any of the above-mentioned narration instructions, the non-narration instruction is directly converted into a corresponding sub-activity diagram (step S503), and then the original code of the next line of high-level programming language is read again. code (step S501).

When step S502 judges that the original code is a narrative instruction, it is necessary to judge whether there is a narrative formula (statement) in front of the conditional expression (step S504). Corresponding sub-graph (step S505).

If there is no statement in front of the conditional expression, then directly generate a selection node (selectnode) (step S506); then, generate two intermediate points (curve point) (step S507), these two intermediate points are connected to the selection node; then, Then convert the narrative into a corresponding sub-activity diagram (step S508), and then generate a merge node (merge node) to merge the sub-activity diagrams (step S509); then connect the sub-activity generated by the conversion of the narrative Figure to the right intermediate point (step S510), connect the sub-activity diagram generated by the narrative formula to the merge node (step S511), and finally, judge whether there are still instructions that have not been converted into sub-activity diagrams (step S512), If there is still, then return to step S501 to re-read the source code of the next line of high-level programming language, if there is no instruction to be converted, then output a complete EAD (step S513).

Through the above steps, a complete piece of JAVA programming language is converted into the corresponding EAD, and the program logic and execution flow of the original code are presented in a visual way. Please refer to Figure 6. Figure 6A is the program written by using the If Statement. According to the above-mentioned conversion process and rules, it can be converted into the corresponding EAD, as shown in Figure 6B. In addition, the same program can also be converted into the corresponding EAD by using the above-mentioned conversion process and rules. Due to the different syntax of JAVA programs, the resulting EADs are also different.

After the above conversion, the first phase of conversion is completed, and then the second phase of conversion is performed to convert the extended activity diagram into a hardware component diagram (HCG), and HCG is used to represent the relationship between the high-level programming language and the hardware.

Please refer to the graphic specifications of the hardware component diagrams shown in Figures 7A to 7C. HCGs are divided into three types:

1. Start node (start node): as shown in Figure 7A, the start node records the class name, method name, parameter, local variable, global variable, returntype of the JAVA program; its definition is as follows:

i. Method (method) information, including the name of the method and its modifier (modifier);

ii. Information about the return value, including its type, bit size and name of the return value;

iii. Parameter information, including its type, bit size and parameter name;

iv. Local variable information, including type, bit size and local variable name.

2. End node: As shown in Figure 7B, the end node indicates that the method (method) has ended, and marks the variable to be returned; where the content of the end node is the name of the variable to be returned, if not Returns any variable, the keyword is VOID.

3. Component node (component node): As shown in Figure 7C, the component node marks the hardware components such as register, fork, adder..., and the nodes are connected with a directional line and marked from the starting object An output port of the target object is connected to an input port of the target object.

The component node can be subdivided into two main parts:

(1) Control path module (Control path module), refer to shown in Figure 7D, it comprises:

■Serial component (Q-element) indicates that its corresponding hardware must be executed sequentially during execution;

■ Parallel component (Fork-element) means that the corresponding hardware is executed in parallel;

■Synchronous component (Join-element) indicates that the corresponding hardware will only send out output signals when all relevant operations are completed;

■The conditional branch component (Decoder-element) indicates that the corresponding hardware will choose to send an appropriate output signal after decoding;

■Merge element means that the corresponding hardware will combine the input signals and output them;

(2) Data path module (Data path module), referring to shown in Figure 7E, it comprises:

■ Operational logic unit (ALU): AND-element, OR-element, XOR-element, ADD-element, SUB-element, MUL-element, DIV-element;

■Register: register-element;

■Multiplexer and demultiplexer: RMUXDEMUX-element, WMUXDEMUX-element;

■Constants: constant-element.

Among them, the content representation of the component node is divided into the following two items:

(1) Registers, constants, etc. need to be distinguished by labels:

Component name__variable name (Component name_variable name);

(2) The representations of MICROOP, CMP, MERGE, etc. that do not need to be distinguished by labels are:

Component name;

The representation of the connection between nodes is:

The output terminal of the starting point → the input terminal of the target point;

The EAD can be converted into a hardware component diagram that is more relevant to the hardware component by using the graphic specification diagram of the above hardware component diagram.

Fig. 8 shows the flow chart of extending activity diagram (EAD) conversion into and hardware component (HCG), at first, read a subactivity diagram (step S801) in this extension activity diagram, then, judge the subactivity diagram of this reading The type of the sub-activity diagram (step S802), when the type of the read sub-activity diagram is one of fork, join, or merge, it is directly converted into the corresponding hardware component diagram (step S803 ), after that, re-read a sub-activity diagram in the extended activity diagram until all the sub-activity diagrams have been read and converted into corresponding hardware component diagrams.

When step S802 judges that the sub-activity diagram read is a micro-operation (micro-operation) type, the micro-operation sub-activity diagram will be parsed and converted (step S804), and then the selected sub-activity diagram will be converted into a corresponding After the hardware component diagram (step S806 ), reread a subactivity diagram in the activity diagram until all the subactivity diagrams have been read and converted into corresponding hardware component diagrams.

When step S802 judges that the sub-activity diagram of this reading is a selection (select) type, earlier the mark (label) on the output terminals on such hardware component diagrams is analyzed (step S805), after that, select sub-activity Carry out grammatical analysis and conversion (step S804) to the figure, and then convert the selected subactivity diagram into a corresponding hardware component diagram (step S806), until all subactivity diagrams have been read and converted into corresponding hardware component diagrams ( After step S807), connecting lines are generated to connect the input and output ends of the hardware component diagrams (step S808), and finally, the complete hardware component diagram can be output (step S809).

Through the above steps, a complete EAD is converted into a corresponding hardware component graph (HCG) (as shown in Figure 9), wherein the top node is the start node (Start Node), and the start node records the JAVA program respectively. class information and method information; the bottom node in Figure 9 is the end node (end node), which indicates that the method has ended and requires a return value; the rest of the nodes in Figure 9 are marked register, micro-operation, Hardware components such as fork and adder, and nodes are marked with a directional connection line, connecting an output port of the starting object to an input port of the target object.

After the above conversion, the second stage of conversion is completed, and then, the third stage of conversion will be performed to generate the corresponding signal connection of the VHDL component according to the connection of the hardware component diagram, and the VHDL entity and The schema is exported to a file, completing the entire conversion.

Fig. 10 is a flowchart of converting the hardware component graph (HCG) into VHDL hardware description language according to the present invention. Firstly, read a hardware component graph (HCG) (step S1001), wherein the hardware component graph (HCG) includes a plurality of sub-hardware component graphs. Next, modify the hardware component diagram (step S1003), because there is no relationship between the hardware component diagram (HCG) and the actual hardware components, so the hardware component diagram (HCG) cannot be directly converted into VHDL hardware description language. Therefore, the hardware component diagram (HCG) needs to be revised first, so that the components in the revised hardware component diagram (HCG) can correspond to the components of the VHDL hardware description language.

This embodiment is described by taking a Java adder in FIG. 11 as an example, and FIG. 12 is a hardware component diagram (HCG) corresponding to the Java adder. First, find out the public method (public method) corresponding to the hardware component diagram (HCG) through the class information (class info) and the hardware component diagram (HCG), and put the public method (public method) part from the method start node ( method start node) and a line to the class start node. The connection line is labeled "method_namereq4p" to indicate that this public method will have an input signal named method_nameReq4p on the corresponding hardware interface. The input signal will be connected to a port named req4p of the method start node. And connect a line from the class start node to the method start node. The label of the connection line is "ack4p method_name", which means that a line will be connected from the ack4p port of the method start node (method startnode) to an output signal named method_nameAck4p on the hardware interface (as shown in Figure 13).

Since each return will send a piece of data, and send the end signal back to the start node, so when encountering a judgment expression, it is the case that there are different return values. In this case, it is necessary to merge multiple return nodes. It first puts all the values to be returned (return value) into a register (register), and the register (register) is named "retMethod_name", and then uses the merge component (Merge element) to connect the signal line to an end Node (end node), its label name is "return retMethod_name. Since the end node (end node) only represents the end of the process, it does not mean anything in hardware, and the end of execution in an asynchronous system means that there will be a return message The acknowledgment is sent back, so the end node (end node) is removed and connected back to the method start node (method start node) (as shown in Figure 14).

Through the class information (class info) and the hardware component graph (HCG), it can be known which parameters (parameter) and return value (return value) corresponding to the hardware component graph (HCG) are public. Connect the public parameters (parameter) and return value (retum value) to the class start node (class startnode), which means that these nodes will have corresponding hardware interfaces for external signal input and output. In the parameter part, an input signal will be connected from the class start node (class start node) to the parameter register node (register node), and its label is "parameter_name w", indicating that the data is input into the register from the hardware interface. And a signal line will be connected from the parameter register node to the hardware interface, and its volume label is "ack4p parameter_name", indicating that an acknowledgment signal is returned from the register to the hardware interface. The return value (return value) connects a line from the method start node (method start node) to the register node of the return value. But because the output port is the same as the port connected to the class start node, a fork node must be used to split the line connected to the class start node to the return buffer Node (return register node). The return register node (retum register node) will also connect a line to the class start node (class start node) to represent the output of the return value, and its label is "qretMethod_name" (as shown in Figure 15).

Collect its method information (class info) from the class information (class info), and collect its output/input connection lines (in/out edges) from the hardware component diagram (HCG) to generate method call information (method call info.) . Then use the method call information (method call info.) to change the connection line connected to the method call node (method call node) in the hardware component diagram (HCG) to connect to the method start node (method start node) to represent the method call (method call). It is necessary to add a multiplexer and demultiplexer to control the input and output (as shown in Figure 16) when processing the connection. Multiple registers often appear in a hardware component diagram (HCG). However, registers with the same label actually refer to the same register, so these registers with the same meaning need to be merged to form a modified HCG as shown in FIG. 17 .

Please refer to Fig. 10 again, after step S1001, after executing the revised hardware component diagram (step S1003), find out a starting node (StartNode) of the hardware component diagram (step S1005), to obtain the corresponding sub-hardware component picture. The start node (StartNode) in step S1005 refers to the method start node (method start node). At this time, since the modified HCG can correspond to the VHDL hardware description language object one by one, the method start node (method startnode) starts to convert into the VHDL hardware description language object.

Step S1007 analyzes the information of the method start node (method start node), so as to add input and output components, and generate hardware description language entities (entities), until all start nodes (Start Node) are analyzed.

Please refer to FIGS. 18-25 together. FIGS. 18-25 are VHDL program codes converted according to the hardware component diagram in FIG. 9 in this embodiment. In Figures 18-25, the name of the entity (entity) is the method start node (method start node), and the connection in the method start node (method start node) is now converted into the output/input of the entity (entity) port.

Step S1009 is to determine the type of the node (node) in the hardware component diagram, generate a corresponding hardware description language (VHDL) object, and write related information into the architecture (Architecture) of the hardware description language. Wherein, a component instantiation method is used to generate a corresponding hardware description language (VHDL) object.

Step S1011 generates signal connections corresponding to hardware description language (VHDL) components according to the connection of the revised hardware component diagram. In step S1013 , output the entity (entity) and architecture (Architecture) of the hardware description language (VHDL) in a character string as shown in FIGS. 18-25 . Wherein, the revised hardware component diagram can be in one-to-one correspondence with the VHDL component, so that it can be easily converted into VHDL program code. The problem that the hardware component diagram (HCG) cannot be converted into correct VHDL program code can be avoided.

Through the above steps, a complete HCG can be converted into a corresponding hardware description language in the third stage.

As can be seen from the above description, the method for automatically converting the high-level programming language (for example: Java, C, C++) of the present invention into a hardware description language (VHDL) can be converted into a function described in the high-level programming language by a three-stage conversion mechanism. It is directly converted to the corresponding hardware description language, which is not limited to the type of high-level programming language, and can unify the complete execution process without causing troubles in the design of hardware components.

The above-mentioned embodiments are only examples for convenience of description, and the scope of the claims claimed in the present invention should be based on the scope of the patent application, rather than limited to the above-mentioned embodiments.

Claims (12)

1. A method for automatically converting a high-level programming language into a hardware description language, comprising the following steps: (A) read the source code of a high-level programming language; (B) converting the source code of the high-level programming language into an extended activity diagram, wherein step (B) includes the following sub-steps: (B1) read the source code of a line of high-level programming language; (B2) When the read source code is not a narrative instruction, convert the non-narrative instruction into a corresponding subactivity diagram, and then perform step (B1); (B3) If the read source code is a narration command, and when there is a narration in front of the narration command, convert the narration into a sub-activity diagram; (B4) generating a selection node; (B5) generating two intermediary points, the two intermediary points connecting the selected node; (B6) Converting the narrative into corresponding sub-activity diagrams; (B7) generating a merge node to merge sub-activity diagrams; (B8) Connect the sub-activity diagram generated by the conversion of the narrative to the right intermediate point; (B9) connecting the sub-activity diagram generated by the transformation of the narrative to the merge node; and (B10) judging whether there is still an instruction that has not been converted into a sub-activity diagram, if there is still, perform step (B1), otherwise, output a complete activity diagram; (C) converting the extended activity diagram into a hardware component diagram; (D) converting the hardware component diagram into a hardware description language; and (E) Outputting the hardware description language. 2. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 1, wherein the high-level programming language is Java, C, or C++ programming language. 3. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 1, wherein the extended activity represents a flow control graph. 4. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 1, wherein the extended activity diagram includes: start (start), end (end), intermediate point (curve point) , micro-operation (micro-operation), fork (fork), link (join), selection (select), merge (merge) a total of eight types of nodes. 5. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 1, wherein the hardware component diagram is used to represent the connection relationship between hardware components and hardware components. 6. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 5, wherein the hardware component diagram includes three types: a start node, an end node and a component node. 7. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 1, wherein the hardware description language is VHDL or Verilog. 8. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 1, wherein in step (A3), the narration instructions include: for, while, do, if, switch instructions . 9. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 1, wherein step (C) comprises the following sub-steps: (C1) read a sub-activity diagram in the extended activity diagram, and when all the sub-activity diagrams in the extended activity diagram have been read, perform step (C5); (C2) When it is judged that the type of the read sub-activity diagram is one of fork, connection, or merging, it is directly converted into a corresponding hardware component diagram, and step (C1) is executed; (C3) When it is judged that the read sub-activity diagram is a micro-operation type, perform syntax analysis conversion on the micro-operation sub-activity diagram, and convert the micro-operation sub-activity diagram into a corresponding hardware component diagram, and then perform the steps (C1); (C4) When it is judged that the read sub-activity diagram is a selection type, after analyzing the marks on the output terminals on the hardware component diagrams, then perform syntax analysis and conversion, and convert the selection sub-activity diagram into hardware After the component diagram, step (C1) is performed; and (C5) Connecting the input and output ends of the hardware component diagrams to output a complete hardware component diagram. 10. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 1, wherein step (D) comprises the following sub-steps: (D1) reading a hardware component diagram, wherein the hardware component diagram includes a plurality of sub-hardware component diagrams, converting the hardware component diagram into a modified hardware component diagram to perform hardware description language conversion; (D2) finding a starting node of the hardware component graph to obtain a corresponding sub-hardware component graph; (D3) analyzing the information of the start node to add input and output components to generate hardware description language entities until all start nodes are analyzed; (D4) judging the type of the node in the hardware component diagram, generating a corresponding hardware description language object, and writing the relevant information into the architecture of the hardware description language; (D5) According to the connection of the hardware component diagram, generate the signal connection of the corresponding hardware description language component; and (D6) Outputting the entity and structure of the hardware description language to a file in the form of character strings. 11. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 10, wherein in the step (C4), the component is called to generate a corresponding hardware description language object. 12. The method for automatically converting a high-level programming language into a hardware description language as claimed in claim 10, wherein in step (C1), further comprising converting the hardware component diagram into a modified hardware component diagram, to perform hardware description language translation.

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