CN100468932C - Initial voltage establishing circuit for switching type voltage converter - Google Patents

Abstract

An initial voltage establishing circuit has a current supply circuit, a current regulating circuit, a charge/discharge control circuit and an oscillation signal generating circuit. The current supply circuit provides a charging current and a discharging current. The current regulating circuit regulates the charging current and the discharging current. The charge/discharge control circuit selectively allows the charging current and the discharging current to pass. The oscillation signal generating circuit generates an initial voltage establishing signal using the charging current and the discharging current, so that a duty ratio of the initial voltage establishing signal gradually increases. The initial voltage establishing signal is applied to a switching voltage converter to establish an initial output voltage.

Description

Initial voltage settling circuit for switching voltage converters

field of invention

The present invention relates to an initial voltage establishment circuit, in particular to an initial voltage establishment circuit for a switching voltage converter.

technical background

FIG. 1 shows a circuit diagram of a known switched-mode voltage converter 10 . The switching voltage converter 10 is a boost type, that is, it converts a lower input voltage V _in into a higher output voltage V _out . The inductor L is coupled between the input voltage _Vin and the switching node SN. The upper switch SH is coupled between the switching node SN and the output terminal O, and the lower switch SL is coupled between the switching node SN and the ground potential. In addition, the output capacitor C _o is coupled to the output terminal O to filter the output voltage V _out . In the example shown in FIG. 1, the upper switch SH is realized by a PMOS transistor and the lower switch SL is realized by an NMOS transistor. The switching control circuit 11 applies a switching control signal CS to the driving circuit 12 to generate an upper driving signal PH and a lower driving signal PL. The upper drive signal PH determines whether the upper switch SH is turned on or not, and the lower drive signal PL determines whether the lower switch SL is turned on or not.

Specifically, the switching control circuit 11 determines the duty cycle (Duty Cycle) of the switching control signal CS based on the feedback of the output voltage V _out , so as to adjust the output voltage V _out to a target value. The switching control circuit 11 has a feedback circuit 13 , an error amplifier 14 , a PWM comparator 15 , a reference voltage generating circuit 16 and an oscillation signal generating circuit 17 , and these components are coupled with each other to form a structure as shown in the figure. When the output voltage V _out is lower than the target value, the switching control signal CS output from the switching control circuit 11 provides a larger duty ratio to increase the output voltage V _out . When the output voltage V _out is higher than the target value, the switching control signal CS output from the switching control circuit 11 provides a smaller duty ratio to reduce the output voltage V _out .

When the switching voltage converter 10 is just started, because the output voltage V _out of the output terminal O has not yet been established and is at zero potential, the gap between the output voltage V _out and the target value is the largest, so the switching control output from the switching control circuit 11 The duty cycle of signal CS is extended to a maximum value. This maximum duty ratio causes the lower side switch SL to be turned on for a long time, resulting in a large amount of inrush current, thus easily causing circuit damage.

Contents of the invention

In view of the aforementioned problems, the object of the present invention is to provide an initial voltage establishment circuit for establishing an initial output voltage at the output terminal of the switching voltage converter, so as to avoid circuit damage caused by a large amount of inrush current.

According to an aspect of the present invention, an initial voltage establishment circuit for a switch mode voltage converter is provided. A switching voltage converter converts an input voltage into an output voltage. The initial voltage establishment circuit has: a current supply circuit, a current adjustment circuit, a charging/discharging circuit and an oscillation signal generating circuit. The current supply circuit provides a charging current and a discharging current. The current adjustment circuit adjusts the charging current and the discharging current. The charging/discharging control circuit selectively allows the charging current and the discharging current to pass. The oscillating signal generation circuit uses the charging current and the discharging current to generate an initial voltage establishment signal, so that the duty ratio of the initial voltage establishment signal gradually increases, and the duty ratio is the sum of the charging current, the charging current and the discharging current ratio. The initial voltage establishment signal is applied to the driving circuit in the switching mode voltage converter to establish an initial voltage.

According to another aspect of the present invention, there is provided a switching voltage converter for converting an input voltage into an output voltage, the switching voltage converter has: a switching circuit, an initial voltage establishing circuit, a switching control circuit and a Signal selection circuit. The switching circuit has a first switch, a second switch and an inductor. The first switch, the second switch and the inductor are commonly coupled to a switching node. The initial voltage establishment circuit generates an initial voltage establishment signal. In response to the output voltage, the switching control circuit generates a switching control signal. When the switch-mode voltage converter starts up, the signal selection circuit allows the initial voltage establishment signal to be applied to the switching circuit to control the first switch and the second switch, so that the output voltage rises to a predetermined initial output voltage. After the output voltage reaches the predetermined initial output voltage, the signal selection circuit allows the switching control signal to be applied to the switching circuit to control the first switch and the second switch to adjust the output voltage to a predetermined target value.

The following description and accompanying drawings will make the aforementioned and other objects, features and advantages of the present invention more apparent.

Description of drawings

FIG. 1 shows a circuit diagram of a known switched-mode voltage converter.

Fig. 2 shows a circuit diagram of a switched-mode voltage converter provided with an initial voltage establishment circuit according to the invention.

Fig. 3 shows a detailed circuit diagram of the initial voltage establishment circuit according to the present invention.

FIG. 4 shows a waveform timing diagram of the operation method of the initial voltage establishing circuit according to the present invention.

Description of main component symbols

10 Switch Mode Voltage Converter

11 switch control circuit

12 drive circuit

13 Feedback circuit

14 Error Amplifier

15 PMW comparators

16 Reference voltage generating circuit

17 Oscillating signal generating circuit

18 Initial voltage establishment circuit

19 Signal selection circuit

31 Current adjustment circuit

32 current supply circuit

33 Charge/discharge control circuit

34 Oscillating signal generating circuit

A, B endpoint

SH upper side switch

SL lower side switch

SN switch node

O output

L inductor

V _in input voltage

V _out output voltage

_Vp peak voltage

C _o output capacitance

C _osc oscillation capacitor

PH upper side drive signal

PL lower side drive signal

CS switching control signal

ES initial voltage establishment signal

K1～K12 Inverter

CT counter

Q ₀ ~Q _(n-1) byte output signal

S1～S8 Current adjustment signal

P1～P8 PMOS transistors

N1, N2 NMOS transistors

P _chg charging transistor

N _dis discharge transistor

I _chg charging current

I _dis discharge current

Detailed ways

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 shows a circuit diagram of a switched-mode voltage converter 20 according to the invention, in which an initial voltage establishment circuit 18 is provided. Referring to FIG. 2 , the switch-mode voltage converter 20 is a boost type, that is, it converts a lower input voltage V _in into a higher output voltage V _out . The inductor L is coupled between the input voltage _Vin and the switching node SN. The upper switch SH is coupled between the switching node SN and the output terminal O, and the lower switch SL is coupled between the switching node SN and the ground potential. In addition, the output capacitor C _o is coupled to the output terminal O to filter the output voltage V _out . In the example shown in FIG. 2, the upper switch SH is realized by a PMOS transistor and the lower switch SL is realized by an NMOS transistor. Whether the upper switch SH is turned on or not is determined by the upper driving signal PH, and whether the lower switch SL is turned on or not is determined by the lower driving signal PL.

As mentioned above, in the known switch-mode voltage converter 10 shown in FIG. The switching control circuit 11 generates.

However, in the switching mode voltage converter 20 according to the present invention shown in FIG. 2 , the initial voltage establishment providing circuit provides an initial voltage establishment signal ES. When the switching mode voltage converter 20 starts up, the signal selection circuit 19 allows the terminal A to be coupled to the driving circuit 12 , so that the initial voltage setup signal ES is applied to the driving circuit 12 to generate the upper driving signal PH and the lower driving signal PL. The initial voltage setup signal ES is a pulse signal with a gradually increasing duty ratio. Specifically, the initial voltage setup signal ES initially provides a small duty ratio, and then gradually increases the duty ratio, so that the output voltage V _out of the output terminal O gradually rises from zero potential to a predetermined initial output voltage. Since the initial voltage setup signal ES initially provides a small duty ratio, it can effectively prevent a large amount of inrush current when the switch-mode voltage converter 20 starts up.

After the output voltage V _out of the input terminal O reaches the predetermined initial output voltage, the signal selection circuit 19 in turn allows the terminal B to be coupled to the driving circuit 12, so that the switching control signal CS is applied to the driving circuit 12 to generate the upper side driving signal PH and lower side drive signal PL. In this phase, the operation of the switching mode voltage converter 20 becomes like the known operation of the switching mode voltage controller 10 described above. In other words, the switching control circuit 11 has a feedback circuit 13 , an error amplifier 14 , a PWM comparator 15 , a reference voltage generating circuit 16 and an oscillation signal generating circuit 17 , and these components are coupled with each other to form a structure as shown in the figure. When the output voltage V _out is lower than the target value, the switching control signal CS output from the switching control circuit 11 provides a larger duty ratio to increase the output voltage V _out . When the output voltage V _out is higher than the target value, the switching control signal CS output from the switching control circuit 11 provides a smaller duty ratio to reduce the output voltage V _out . Since the output voltage V _out of the output terminal O has been raised to the predetermined initial output voltage by the initial voltage setup signal ES, the duty ratio of the switching control signal CS will not expand to a maximum value. Therefore, the switch-mode voltage converter 20 according to the present invention effectively prevents circuit damage caused by the inrush current.

FIG. 3 shows a detailed circuit diagram of the initial voltage establishment circuit 18 according to the present invention. As shown, the initial voltage establishing circuit 18 has a current regulating circuit 31 , a current supply circuit 32 , a charge/discharge control circuit 33 and an oscillation signal generating circuit 34 . Under the control of the current regulation circuit 31 , the current supply circuit 32 provides a charging current I _chg and a discharging current I _dis . The magnitudes of the charging current I _chg and the discharging current I _dis are determined by the current adjustment circuit 31 . The charging/discharging control circuit 33 selectively allows the charging current I _chg and the discharging current I _dis to pass. In the charging phase, the charging/discharging control circuit 33 allows the charging current I _chg to charge the oscillation signal generating circuit 34 . In the discharging phase, the charging/discharging control circuit 33 allows the oscillation signal generating circuit to discharge via the discharging current _Idis . By using the charging current I _chg and the discharging current I _dis , the oscillation signal generating circuit 34 provides the initial voltage establishment signal ES, the duty ratio of which is determined by the charging current I _chg and the discharging current I _dis . In response to the initial voltage setup signal ES, the current adjustment circuit 31 adjusts the charging current I _chg and the discharging current I _dis provided by the current supply circuit 32 .

The current adjustment circuit 31 mainly uses a counter CT to count the number of pulses of the initial voltage establishment signal ES, and accordingly generates current adjustment signals S1 to S8 to be applied to the current supply circuit 32 . The counter CT is an n-byte counting logic circuit, and its input terminal IN receives the pulse number of the initial voltage establishment signal. In an embodiment according to the present invention, the largest four byte signals Q(n-4) to Q(n-1) are used to generate the first to eighth current adjustment signals S1 to S8. The first current adjustment signal S1 is generated by the fourth byte signal Q(n-4) through inverters K5 and K6, and the second current adjustment signal S2 is inverted by the fourth byte signal Q(n-4). Phase device K5 generates. Therefore, the phase difference between the first and second current adjustment signals S1 and S2 is 180 degrees. The third current adjustment signal S3 is generated by the third byte signal Q(n-3) through inverters K7 and K8, and the fourth current adjustment signal S4 is inverted by the third byte signal Q(n-3). Phase device K7 generates. Therefore, the phase difference between the third and fourth current adjustment signals S3 and S4 is 180 degrees. The fifth current adjustment signal S5 is generated by the second byte signal Q(n-2) through inverters K9 and K10, and the sixth current adjustment signal S6 is inverted by the second byte signal Q(n-2). Phase device K9 generates. Therefore, the fifth and sixth current adjustment signals S5 and S6 are 180 degrees out of phase with each other. The seventh current adjustment signal S7 is generated by the first byte signal Q(n-1) through inverters K11 and K12, and the eighth current adjustment signal S8 is inverted by the first byte signal Q(n-1). Phase device K11 generates. Therefore, the phase difference between the seventh and eighth current adjustment signals S7 and S8 is 180 degrees.

The current supply circuit 32 basically has seven current sources I ₀ to I ₆ . The current source I ₀ is constantly applied to the charging transistor P _chg of the charging/discharging control circuit 33 as a part of the charging current I _chg . The current source _I5 is mirrored by transistors N1 and N2 to the discharge transistor _Ndis of the charge/discharge control circuit 33, thus being fixed together with the current source _I6 as a part of the discharge current _Idis . However, the current sources I ₁ to I ₄ are determined to be applied to the charge transistor P _chg or the discharge transistor N _dis based on the selection control of the first to eighth current adjustment signals S1 to S8 .

The first current adjustment signal S1 is applied to the gate of the PMOS transistor P1, and the second current adjustment signal S2 is applied to the gate of the PMOS transistor P2. When the transistor P1 is turned on, the current source _I1 is used as a part of the charging current _Ichg , and when the transistor P2 is turned on, the current source _I1 is used as a part of the discharging current _Idis . The third current adjustment signal S3 is applied to the gate of the PMOS transistor P3, and the fourth current adjustment signal S4 is applied to the gate of the PMOS transistor P4. When the transistor P3 is turned on, the current source _I2 is used as a part of the charging current _Ichg , and when the transistor P4 is turned on, the current source _I2 is used as a part of the discharging current _Idis . The fifth current adjustment signal S5 is applied to the gate of the PMOS transistor P5, and the sixth current adjustment signal S6 is applied to the gate of the PMOS transistor P6. When the transistor P5 is turned on, the current source _I3 is used as a part of the charging current _Ichg , and when the transistor P6 is turned on, the current source _I3 is used as a part of the discharging current _Idis . The seventh current adjustment signal S7 is applied to the gate of the PMOS transistor P7, and the eighth current adjustment signal S8 is applied to the gate of the PMOS transistor P8. When the transistor P7 is turned on, the current source _I4 is used as a part of the charging current _Ichg , and when the transistor P8 is turned on, the current source _I4 is used as a part of the discharging current _Idis .

The operation method of the initial voltage establishing circuit 18 according to the present invention will now be described in detail with reference to FIGS. 3 and 4 as follows. In the embodiment shown in FIG. 4, the n-byte counter CT uses a seven-byte counter, which generates seven output signals Q0 to Q6 to represent seven bytes from small to large. The output signal Q6 represents the first byte and is used to generate the seventh and eighth current adjustment signals S7 and S8. The output signal Q5 represents the second byte and is used to generate the fifth and sixth current adjustment signals S5 and S6. The output signal Q4 represents the third byte and is used to generate the third and fourth current adjustment signals S3 and S4. The output signal Q3 represents the third byte and is used to generate the first and second current adjustment signals S1 and S2.

When the initial voltage establishing circuit 18 starts to operate, the clear terminal CLR of the seven-byte counter CT is activated, so that the initial states of the seven output signals Q0 to Q6 are all set to a high level H. Therefore, the first, third, fifth and seventh current adjustment signals S1, S2, S5 and S7 are all at high level H, while the second, fourth, sixth and eighth current adjustment signals S2, S4 and S6 Both S8 and S8 are low level L. As a result, the transistors P1 , P3 , P5 and P7 are all turned on, and the transistors P2 , P4 , P6 and P8 are all turned on. In this case, the charging current I _chg is equal to I ₀ , and the discharging current I _dis is equal to (I ₁ +I ₂ +I ₃ +I ₄ +I ₅ +I ₆ ). The low potential L of the initial voltage setup signal ES turns on the charging transistor P _chg to allow the charging current I _chg to be applied to the oscillation signal generating circuit 34 , causing the oscillation voltage V _osc on the oscillation capacitor C _osc to continuously increase. After the oscillating voltage V _osc reaches the peak voltage V _p and triggers the inverter K1 with hysteresis effect, the initial voltage establishment signal ES changes to a high potential H, turning on the discharge transistor N _dis and allowing the oscillating signal generating circuit 34 to discharge The current I _dis continuously reduces the oscillating voltage V _osc on the oscillating capacitor C _osc . Therefore, during time t ₀ to t ₁ of FIG. 4 , the duty ratio D ₀ is equal to (I ₀ /I _total ), where I _total =(I _chg +I _dis )=(I ₀ +I ₁ +I ₂ +I ₃ +I ₄ +I ₅ +I ₆ ).

When the seven-byte counter CT receives the eighth pulse of the initial voltage setup signal ES, the output signal [Q3, Q4, Q5, Q6] is converted to [L, H, H, H]. The transition of the output signal Q3 from a high potential H to a low potential L causes the transistor P1 to be turned on and the transistor P2 to be turned off. As a result, the charging current I _chg increases to (I ₀ +I ₁ ), and the discharging current I _dis decreases to (I ₂ +I ₃ +I ₄ +I ₅ +I ₆ ). Thus, in time t ₁ to t ₂ of FIG. 4 , duty ratio D ₁ is equal to [(I ₀ +I ₁ )/I _total ], which is slightly increased relative to D ₀ of the previous stage.

Subsequently, when the seven-byte counter CT receives the 16th pulse of the initial voltage setup signal ES, the output signal [Q3, Q4, Q5, Q6] is converted into [H, L, H, H]. The transition of the output signal Q4 from a high potential H to a low potential L causes the transistor P3 to be turned on and the transistor P4 to be turned off. As a result, the charging current I _chg increases to (I ₀ +I ₂ ), and the discharging current I _dis decreases to (I ₁ +I ₃ +I ₄ +I ₅ +I ₆ ). . Thus, in time t ₂ to t ₃ of FIG. 4 , duty ratio D ₂ is equal to [(I ₀ +I ₂ )/I _total ], which is slightly increased relative to D ₁ of the previous stage.

Subsequently, when the seven-byte counter CT receives the 24th pulse of the initial voltage setup signal ES, the output signal [Q3, Q4, Q5, Q6] is converted into [L, L, H, H]. As a result, the charging current I _chg increases to (I ₀ +I ₁ +I ₂ ), and the discharging current I _dis decreases to (I ₃ +I ₄ +I ₅ +I ₆ ). Thus, in time t ₄ to t ₅ of FIG. 4 , duty ratio D ₃ is equal to [(I ₀ +I ₁ +I ₂ )/I _total ], slightly increased compared to D ₂ of the previous stage.

In this way, the above-mentioned operation mode continues, the charging current I _chg gradually increases and the discharging current I _dis gradually decreases, resulting in a gradual increase in the generated duty ratio...<D ₃ <D ₄ <D ₅ <D ₆ < .... Finally, during time _t15 to _t16 in FIG. 4, the output signal [Q3, Q4, Q5, Q6] changes to [L, L, L, L]. As a result, the charging current I _chg increases to (I ₀ +I ₁ +I ₂ +I ₃ +I ₄ ), and the discharging current I _dis decreases to (I ₅ +I ₆ ). Therefore, the duty ratio D ₁₅ is equal to [(I ₀ +I ₁ +I ₂ +I ₃ +I ₄ )/I _total ].

In the foregoing embodiments, assuming that the current source _I0 is used as the reference current, the current source _I1 is set equal to the current source _I0 ; the current source _I2 is set equal to twice the current source _I0 ; the current source _I3 is set is set to be equal to four times the current source _I0 ; the current source _I4 is set to be equal to eight times the current source _I0 ; the current source _I5 is set to be equal to four times the current source _I0 ; and the current source _I6 is set to is equal to four times the current source I ₀ . Under such assumption conditions, the charging current I _{chg(i) =} (1+i ₎ *I ₀ and the discharging current I _dis(i) =(23- i)*I ₀ , wherein i is an integer from 0 to 15. Therefore, the period T _ES(i) =C _osc *V _p *[(1/I _chg(i) )+(1/I _dis(i) )], and the resulting duty ratio is D _i =I _{chg( i)} /(I _chg(i) +I _dis(i) )=(1+i)/24.

Therefore, the initial voltage setup signal ES initially provides a small duty ratio, and then gradually increases the duty ratio, so that the output voltage V _{out of} the output terminal O gradually rises from zero potential to a predetermined initial output voltage. Since the initial voltage setup signal ES initially provides a small duty ratio, it effectively prevents a large amount of inrush current from being generated. Since the output voltage V _out of the output terminal O has increased to the predetermined initial output voltage, the duty ratio of the switching control signal CS output from the switching control circuit 11 will not expand to the maximum value. Therefore, circuit damage caused by inrush current is effectively prevented.

While the present invention has been described by way of illustration of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of protection claimed by the patent application shall be construed in the broadest way to encompass all such modifications and similar arrangements.

Claims (9)

1, a kind of initial voltage establishing circuit is used for a switch type electric voltage converter, and this switch type electric voltage converter is used for converting an input voltage to an output voltage, and this initial voltage establishing circuit comprises:

A current providing circuit is used to provide a charging current and a discharging current;

A matrix current adjustment circuit is used to adjust this charging current and this discharging current;

A charging/discharging control circuit is used for optionally allowing this charging current and this discharging current to pass through; And

An oscillating signal generating circuit, utilize this charging current and this discharging current to produce an initial voltage and set up signal, the work ratio that makes this initial voltage set up signal increases gradually, wherein thereby this initial voltage is set up the drive circuit that signal is applied in this switch type electric voltage converter and is set up an initial output voltage, and this work is than being the ratio of this charging current with this charging current and this discharging current sum.

2, initial voltage establishing circuit as claimed in claim 1, wherein:

This matrix current adjustment circuit is set up signal based on this initial voltage and is adjusted this charging current and this discharging current.

3, initial voltage establishing circuit as claimed in claim 1, wherein:

This matrix current adjustment circuit increases this charging current gradually and this discharging current is reduced gradually.

4, initial voltage establishing circuit as claimed in claim 1, wherein:

This oscillating signal generating circuit comprises:

An oscillating capacitance has been striden an oscillating voltage on it, when this charging current was charged to this oscillating capacitance, this oscillating voltage raise gradually, and when this oscillating capacitance discharged via this discharging current, this oscillating voltage reduced gradually, and

An inverter is used for producing this initial voltage in response to this oscillating voltage and sets up signal.

5, initial voltage establishing circuit as claimed in claim 1, wherein:

This matrix current adjustment circuit has a counter, is used to calculate the pulse number that this initial voltage is set up signal, so that this matrix current adjustment circuit is adjusted this charging current and this discharging current according to this pulse number.

6, a kind of switch type electric voltage converter is used for converting an input voltage to an output voltage, comprising:

A commutation circuit has one first switch, a second switch and an inductor, and wherein this first switch, this second switch and this inductor coupled in common are in a switching node;

An initial voltage establishing circuit comprises:

A current providing circuit is used to provide a charging current and a discharging current;

A matrix current adjustment circuit is used to adjust this charging current and this discharging current;

A charging/discharging control circuit is used for optionally allowing this charging current and this discharging current to pass through; And

An oscillating signal generating circuit, utilize this charging current and this discharging current to produce an initial voltage and set up signal, the work ratio that makes this initial voltage set up signal increases gradually, wherein thereby this initial voltage is set up the drive circuit that signal is applied in this switch type electric voltage converter and is set up an initial output voltage, and this work is than being the ratio of this charging current with this charging current and this discharging current sum;

A control switching circuit is used for producing a switch-over control signal in response to this output voltage; And

A signal selecting circuit, when this switch type electric voltage converter begins to start, this signal selecting circuit allows this initial voltage to set up signal and is applied to this commutation circuit to control this first switch and this second switch, make this output voltage rise to a predetermined initial voltage, and after this output voltage reaches this predetermined initial output voltage, this signal selecting circuit allows this switch-over control signal to be applied to this commutation circuit to control this first switch and this second switch, in order to regulate this output voltage in a predetermined target value.

7, switch type electric voltage converter as claimed in claim 6, wherein:

This matrix current adjustment circuit is set up signal based on this initial voltage and is adjusted this charging current and this discharging current, so that this charging current increases gradually and this discharging current is reduced gradually.

8, switch type electric voltage converter as claimed in claim 6, wherein:

This oscillating signal generating circuit comprises:

An oscillating capacitance has been striden an oscillating voltage on it, when this charging current was charged to this oscillating capacitance, this oscillating voltage raise gradually, and when this oscillating capacitance discharged via this discharging current, this oscillating voltage reduced gradually, and

An inverter is used for producing this initial voltage in response to this oscillating voltage and sets up signal.

9, switch type electric voltage converter as claimed in claim 6, wherein:

This matrix current adjustment circuit has a counter, is used to calculate the pulse number that this initial voltage is set up signal, so that this matrix current adjustment circuit is adjusted this charging current and this discharging current according to this pulse number.

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