CN100468657C - Three-dimensional multi-gate element and manufacturing method thereof - Google Patents

Abstract

The invention provides a three-dimensional multi-gate element and a manufacturing method thereof. The three-dimensional multi-gate device comprises a fin-shaped silicon, a gate structure and a stress adjustment layer. The grid structure is contacted with two side faces of the fin-shaped silicon to form a three-dimensional multi-grid structure, and the stress adjusting layer covers the grid structure to provide stress parallel to the length direction of the channel for the grid structure. The stress can improve the electron mobility of a channel region below the gate structure, and effectively improve the driving current characteristics of the three-dimensional multi-gate element.

Description

Three-dimensional multi-gate element and its manufacturing method

technical field

The invention relates to a three-dimensional multi-gate element and its manufacturing method, in particular to a three-dimensional multi-gate element with a stress adjustment layer and its manufacturing method.

Background technique

As the size of semiconductor devices shrinks, maintaining the performance of small-sized semiconductor devices is a major goal of the industry. In order to improve the performance of semiconductor devices, various three-dimensional multi-gate devices have been gradually developed. The three-dimensional multi-gate device has the following advantages. Firstly, the process of the three-dimensional multi-gate device can be integrated with the traditional logic device process, so it has considerable process compatibility; secondly, due to its special structure, it is not necessary to use the traditional shallow trench isolation (shallow trench isolation) technology to electrically isolate components; moreover, because the three-dimensional structure increases the contact area between the gate and the substrate, it can increase the gate's control over the charge in the channel region, thereby reducing the leakage induction barrier caused by small-sized components Reduce (Drain Induced Barrier Lowering, DIBL) effect and short channel effect (short channel effect); in addition, because the gate of the same length has a larger channel width, it can also increase the amount of current between the source and drain .

The existing three-dimensional multi-gate structure still has room for development in terms of electron mobility. Therefore, the present invention improves the existing three-dimensional multi-gate device to further enhance the performance of the device.

Contents of the invention

The invention discloses a three-dimensional multi-gate element and its manufacturing method. By forming a stress adjustment layer on the gate structure, the performance of the three-dimensional multi-gate element can be effectively improved.

According to the present invention, a silicon fin disposed on a silicon-on-insulator substrate is provided, and the silicon fin has an upper surface and two side surfaces parallel to each other. Then a gate structure is formed on the fin-shaped silicon, and the gate structure covers the upper surface and part of the two sides of the fin-shaped silicon. Then an ion implantation process is performed on the fin-shaped silicon to form the source/drain regions of the three-dimensional multi-gate device. Finally, a stress adjustment layer covering at least the gate structure is formed. Wherein the hard mask oxide layer used to form the fin-shaped silicon is not removed in subsequent steps, a gate dielectric layer is formed on both sides of the fin-shaped silicon, and the thickness of the hard mask oxide layer is greater than that of the gate electrode. The thickness of the dielectric layer.

Compared with the prior art, the three-dimensional multi-gate element manufactured by the present invention has a stress adjustment layer. The stress adjustment layer can provide stress parallel to the length direction of the gate structure and the channel, and improve the electron mobility of the channel region under the gate structure, effectively improving the electrical performance of the three-dimensional multi-gate device.

Description of drawings

1 to 9 are schematic diagrams of a method for manufacturing a three-dimensional multi-gate element according to a preferred embodiment of the present invention;

Fig. 10 shows the current comparison diagram of the present invention and the existing three-dimensional multi-gate element;

Figure 11 shows the difference in electron mobility between the three-dimensional multi-gate element of the present invention and the channel region of the existing three-dimensional multi-gate element;

FIG. 12 shows the difference in DIBL performance between the three-dimensional multi-gate device of the present invention and the conventional three-dimensional multi-gate device.

Description of main component symbols

120 Silicon substrate 134b Silicon nitride layer

122 insulating layer 136, 138 source/drain region

124 Monocrystalline silicon layer 142 Self-aligned metal silicide layer

125 Oxide layer 144 Self-aligned metal silicide layer

126 Hard mask oxide layer 146 Salicide layer

127 finned silicon 150 stress adjustment layer

128 sacrificial layer 152 interlayer dielectric layer

130 oxynitride layer 154 contact hole

132 polysilicon layer 156 patterned copper layer

133 polysilicon gate structure A side

134 Side wall substructure B side

134a offset oxide layer C upper surface

Detailed ways

The invention provides a three-dimensional multi-gate element and a manufacturing method thereof. Please refer to Figure 1 to Figure 9. 1 to 9 are schematic diagrams of a method for fabricating a three-dimensional multi-gate device according to a preferred embodiment of the present invention, and FIG. 9 also shows the structure of a three-dimensional multi-gate device according to a preferred embodiment of the present invention.

Please refer to Fig. 1 at first, as shown in Fig. 1, the method of the present invention is to first provide a silicon-on-insulator (silicon-on-insulator, SOI) substrate, which comprises a silicon substrate 120, a silicon substrate 120 An insulating layer 122 on it, and a single crystal silicon layer 124 overlying the insulating layer 122 . First, an oxidation process is performed on the single crystal silicon layer 124 to oxidize the upper surface C of the single crystal silicon layer 124 to form an oxide layer 125 . In this embodiment, after the oxide layer 125 is formed, the thickness T of the single crystal silicon layer 124 is maintained between 50 and 100 nanometers (nm). Next, as shown in FIG. 2, a photoresist layer (not shown) is formed on the oxide layer 125, and a photolithography and etching process is performed to remove the oxide layer 125 in a part of the region to form a patterned hard layer. The mask oxide layer 126 is used to cover the places where the silicon fins are planned to be formed. Next, the monocrystalline silicon layer 124 is etched by using the hard mask oxide layer 126 as a hard mask, so as to form a silicon fin 127 , as shown in FIG. 3 . Of course, the single crystal silicon layer 124 can also be formed into fin-shaped silicon 127 by other methods. After the silicon fin 127 is formed, a sacrificial layer 128 is subsequently formed on the two sides A, B of the silicon fin 127 . Next, ion doping is performed on the fin-shaped silicon 127 (as shown by the arrow in FIG. 3 ), for example, doping with boron (B) ions or arsenic (As) ions, so as to adjust the threshold voltage of the three-dimensional multi-gate element ( Threshold Voltage, V _TH ), and immediately remove the sacrificial layer 128 , wherein the function of the sacrificial layer 128 is to make the two sides A, B of the fin-shaped silicon 127 have a good lattice arrangement.

)左右。在形成氮氧化层130后，接着进行一沉积工艺，以于绝缘层122与鳍状硅127上形成一多晶硅层132。接着如图5所示，于多晶硅层132上形成一光致抗蚀剂层(未图示)，并进行一光刻及蚀刻工艺去除部分区域的多晶硅层132以形成一与鳍状硅127近乎正交且长度约在80纳米的多晶硅栅极结构133，其中值得注意的是在本实施例中氮氧化层130并未被移除而仍保留于多晶硅栅极结构133的侧壁，当作此立体多栅极元件的栅极介电层使用。另外，位于鳍状硅127上的硬掩模氧化层126在蚀刻多晶硅层132时作为蚀刻停止层之用，藉此保护鳍状硅127不致于在蚀刻多晶硅层132的过程中受损。Next, as shown in FIG. 4 , an oxynitride layer 130 is formed on both sides A and B of the fin-shaped silicon 127 . The formation of the oxynitride layer 130 can be achieved by forming an oxide layer (not shown) on the two sides A and B of the fin-like silicon 127 , and then nitriding the oxide layer by plasma. In this embodiment, the thickness of the oxynitride layer 130 is about 14 Angstroms (

)about. After forming the oxynitride layer 130 , a deposition process is then performed to form a polysilicon layer 132 on the insulating layer 122 and the fin silicon 127 . Next, as shown in FIG. 5, a photoresist layer (not shown) is formed on the polysilicon layer 132, and a photolithography and etching process is performed to remove the polysilicon layer 132 in a part of the region to form a fin-like silicon 127. Orthogonal polysilicon gate structure 133 with a length of about 80 nanometers, where it is worth noting that in this embodiment the oxynitride layer 130 is not removed but remains on the sidewall of the polysilicon gate structure 133, as this The gate dielectric layer of the three-dimensional multi-gate device is used. In addition, the hard mask oxide layer 126 on the fin silicon layer 127 is used as an etch stop layer when etching the polysilicon layer 132 , thereby protecting the fin silicon layer 127 from being damaged during the etching process of the polysilicon layer 132 .

Please refer to Fig. 6, which is a cross-sectional view of Fig. 5 along the 6-6' axis. As shown in FIG. 6, an ion implantation process is performed on the polysilicon gate structure 133, and high-concentration phosphorus (P) ions or boron (B) ions are doped into the polysilicon gate structure 133 so that the polysilicon gate structure 133 has a good conductivity. Next, an offset oxide layer 134a and a silicon nitride layer 134b are sequentially formed on the polysilicon gate structure 133, the hard mask oxide layer 126 and the insulating layer 122, wherein in this embodiment, the offset oxide layer The thicknesses of layer 134a and silicon nitride layer 134b are 100 angstroms and 500 angstroms, respectively. As shown in FIG. 7, part of the silicon nitride layer 134b and the offset oxide layer 134a are subsequently etched away in order to form sidewall substructures 134 on both sides of the polysilicon gate structure 133. , remove the hard mask oxide layer 126 not covered by the sidewall substructure 134 at the same time, so as to facilitate subsequent formation of source/drain regions. Next, a high-concentration ion implantation process is performed to dope ions into the fin-shaped silicon 127, so as to form source/ Drain regions 136,138. For example, in this embodiment, arsenic (As) ions and phosphorus ions are doped into the fin-shaped silicon 127 to form an N-type three-dimensional multi-gate device.

)至2000埃之间，且优选在400埃至1800埃之间。通过此高厚度的应力调整层150可提供立体多栅极元件在X-X’方向的高拉伸应力或是高压缩应力。As shown in FIG. 8 , a self-aligned silicide process is performed to form a self-aligned silicide layer 142 on the source/drain regions 136 , 138 and the polysilicon gate structure 133 respectively. , 144, 146. The salicide layers 142 , 144 , 146 can be cobalt (Co) salicide layers or other salicide layers such as nickel (Ni), titanium (Ti) or platinum (Pt). Then, a chemical vapor deposition (CVD) process is performed to form a stress adjustment layer 150 on the polysilicon gate structure 133 and the fin silicon 127 . The stress adjustment layer 150 can be a silicon nitride layer, and can be achieved by injecting a nitrogen precursor, such as bis(tertiary-butylamino)silane (BTBAS), in a CVD process. Of course, other processes, such as atmospheric pressure chemical vapor deposition process, low pressure chemical vapor deposition process, and plasma enhanced chemical vapor deposition process, etc., and other materials can also be used to fabricate the stress adjustment layer 150 . The thickness of the stress adjustment layer 150 is in the range of 100 Angstroms (

) to 2000 angstroms, and preferably between 400 angstroms to 1800 angstroms. The high-thickness stress-adjusting layer 150 can provide high tensile stress or high compressive stress in the XX′ direction of the three-dimensional multi-gate device.

Next, as shown in FIG. 9 , continue to form at least one interlayer dielectric (ILD) 152 on the stress adjustment layer 150 . The interlayer dielectric layer 152 may be a silicon monoxide layer, and may be un-doped silicon glass formed by atmospheric pressure chemical vapor deposition (APCVD). Alternatively, tetraethyl orthosilicate chemical vapor deposition (TEOS-CVD) can also be used to form phosphosilicate glass with phosphorus as a dopant as an interlayer Dielectric layer 152 . Certainly, other processes and other materials may also be used to fabricate the interlayer dielectric layer 152 . After the fabrication of the interlayer dielectric layer 152 is completed, a plurality of contact holes 154 are formed in the interlayer dielectric layer 152 , and metal tungsten (W) is filled in the contact holes 154 as contact plugs. Next, the metal interconnection is fabricated. For example, a patterned copper layer 156 is formed on the interlayer dielectric layer 152 to be electrically connected to the contact plug as an external electrical connection. There may be a titanium nitride (TiN) layer (not shown) or a tantalum nitride (TaN) layer between the metal tungsten and the wall of the contact hole 154, and between the patterned copper layer 156 and the interlayer dielectric layer 152. (not shown) layer acts as a diffusion barrier to block the diffusion of the metal.

Since the three-dimensional multi-gate element produced by the method of the present invention has a stress adjustment layer, it can effectively improve the electron mobility and driving current characteristics of the channel region when the element is turned on. It is worth noting that the above embodiment is an example of an N-type three-dimensional multi-gate device, so the stress adjustment layer is made of silicon nitride that can provide high tensile stress (Tensile Stress); If it is a P-type three-dimensional multi-gate element, the stress adjustment layer can also be made of other materials that can provide high compressive stress. For example, the material of the stress adjustment layer can also be silicon oxide or silicon oxynitride.

In addition, FIG. 10 to FIG. 12 show the difference in performance between the three-dimensional multi-gate device of the present invention and the conventional three-dimensional multi-gate device without a stress adjustment layer. Please refer to FIG. 10 . FIG. 10 shows a current comparison diagram of the present invention and the conventional three-dimensional multi-gate device. As shown in FIG. 10 , the present invention has a higher on-off current ratio (I _on /I _off ). According to FIG. 10 , the present invention has a current gain of about 26% compared to the existing three-dimensional multi-gate device. Next, please refer to FIG. 11. FIG. 11 shows the difference in electron mobility between the three-dimensional multi-gate element of the present invention and the existing three-dimensional multi-gate element channel region. It can be found from FIG. 11 that the three-dimensional multi-gate element of the present invention is in The performance of electron mobility is obviously better than that of existing three-dimensional multi-gate devices. Please refer to FIG. 12. FIG. 12 shows the difference in DIBL performance between the three-dimensional multi-gate element of the present invention and the existing three-dimensional multi-gate element. According to FIG. 12, when the gate length is shorter, the DIBL of the present invention is relatively slight. In other words, compared with the existing three-dimensional multi-gate device without the stress adjustment layer, the present invention has superior device operation performance, that is, the stress adjustment layer can indeed increase the performance of the multi-gate device.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (20)

1. a method of making three-dimensional multi-gate element, the method may further comprise the steps: (a) providing a semiconductor substrate, and forming a silicon fin on the semiconductor substrate, the silicon fin has an upper surface and two side surfaces; (b) forming a gate structure on the silicon fin, the gate structure covering part of the upper surface and part of the side surfaces of the silicon fin; (c) forming two doped regions in the fin silicon on both sides of the gate structure and not covered by the gate structure; and (d) forming a stress adjustment layer covering the gate structure, Wherein, the hard mask oxide layer used to form the fin silicon in step (a) is not removed in subsequent steps, After step (a), a gate dielectric layer is formed on both sides of the fin-shaped silicon, and the thickness of the hard mask oxide layer is greater than the thickness of the gate dielectric layer. 2. The method of claim 1, wherein the semiconductor substrate is a silicon-on-insulator substrate. 3. The method of claim 1, further comprising forming sidewall substructures on the two sides of the gate structure before step (c). 4. The method of claim 1, further comprising forming a salicide layer on the gate structure and the two doped regions respectively after step (c). 5. The method of claim 1, wherein the stress adjustment layer also covers the fin silicon. 6. The method of claim 1, wherein the stress adjustment layer has a thickness ranging from 100 angstroms to 2000 angstroms. 7. The method of claim 1, wherein the stress adjustment layer comprises a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer. 8. The method of claim 7, wherein the silicon nitride layer is formed by performing a chemical vapor deposition process. 9. The method of claim 8, wherein the precursor of the silicon nitride layer is bis(t-butylamino)silane. 10. The method of claim 1, further comprising forming at least one dielectric layer on the stress adjustment layer after step (d). 11. The method of claim 10, further comprising forming a plurality of contact holes in the dielectric layer and the stress adjustment layer. 12. A three-dimensional multi-gate element structure, comprising: a semiconductor substrate; A fin-shaped silicon is arranged on the semiconductor substrate, and the fin-shaped silicon has an upper surface and two side surfaces, a hard mask oxide layer is formed on the fin-shaped silicon, and gate dielectrics are arranged on the two sides of the fin-shaped silicon layer, the thickness of the hard mask oxide layer is greater than the thickness of the gate dielectric layer; a gate structure disposed on the silicon fin, and the gate structure covers part of the upper surface and part of the side surfaces of the silicon fin; two doped regions are disposed in the fin silicon under both sides of the gate structure; and A stress adjustment layer covers the gate structure. 13. The three-dimensional multi-gate device structure as claimed in claim 12, further comprising a plurality of salicide layers respectively disposed on the gate structure and the doped regions. 14. The three-dimensional multi-gate device structure as claimed in claim 13, wherein the salicide layers comprise a cobalt, nickel, titanium or platinum salicide layer. 15. The three-dimensional multi-gate device structure as claimed in claim 12, wherein the stress adjustment layer comprises a silicon nitride layer, a silicon oxide layer or an oxynitride layer. 16. The three-dimensional multi-gate device structure as claimed in claim 12, wherein the stress adjustment layer has a thickness ranging from 100 angstroms to 2000 angstroms. 17. The three-dimensional multi-gate device structure as claimed in claim 12, further comprising at least one dielectric layer disposed on the stress adjustment layer. 18. The three-dimensional multi-gate device structure as claimed in claim 17, further comprising a plurality of contact holes penetrating through the dielectric layer and the stress adjustment layer. 19. The three-dimensional multi-gate device structure as claimed in claim 12, wherein the three-dimensional multi-gate device structure is N-type, and the stress adjustment layer provides a tensile stress. 20. The three-dimensional multi-gate device structure as claimed in claim 12, wherein the three-dimensional multi-gate device structure is P-type, and the stress adjustment layer provides a compressive stress.

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