CN100466480C - Method for determining output signal of Viterbi decoder and output selector thereof - Google Patents

Abstract

The present invention provides a method for determining an output signal of a Viterbi decoder, which comprises the following steps: (a) receiving a digital signal obtained by decoding an input signal by the Viterbi decoder and outputting the digital signal through a path memory module of the Viterbi decoder; (b) comparing the digital signal received in step (a) with a preset value; and (c) determining an output result according to the comparison result of step (b).

Description

A method of determining the output signal of Viterbi decoder and its output selector

technical field

The present invention refers to a method for determining the output signal of a Viterbi decoder and an output selector thereof, in particular to a method for comparing the sum of a plurality of digital signals output by a path memory module of the Viterbi decoder with the Viterbi One-half of the number of states of the decoder to judge the output signal of the Viterbi decoder.

Background technique

The technology of maximum similarity sequence estimation has been widely used in various digital decoding, among which the Viterbi detector is a kind of method to estimate a sequence of convolution codes with the maximum similarity sequence. circuit. As known in the industry, there are additive white Gaussian noise (AWGN) or other sources of interference in general communication channels, and in order to reduce the probability of errors in signal detection, most communication systems will The data to be transmitted is encoded first, for example, a special algorithm is used to convolute the data to be transmitted, so that the number of bits of the transmitted data increases. Before the receiver decodes, it can use the characteristics of the algorithm to detect whether the received data is correct, and even restore the erroneous bits.

Please refer to FIG. 1 , which is a functional block diagram of a conventional Viterbi decoder 10 . The Viterbi decoder 10 includes a branch input unit 12 , an addition comparison selector 14 , a path memory module 18 , a path metric value memory module 16 and an output selector 20 . The branch input unit 12 can receive a sequence signal DTi and divide the sequence signal DTi into a plurality of branch paths according to the preset state of the Viterbi decoder 10 and input them to the addition comparison selector 14; the addition comparison selector 14 can use the Viterbi algorithm According to the maximum similarity sequence estimation (Maximum LikelihoodSequence Estimation, MLSE), the path metric value (Path Metric) of the sequence signal DTi output by the branch input device 12 is calculated and the calculated path metric value is output to the path metric value memory module 16; at the same time, add and compare the selector 14 and calculate a plurality of state values to be input to the path memory module 18. The output selector 20 can determine a sequence of output signals DTo according to the signal output by the path memory module 18 . The operation of the Viterbi decoder 10 is known in the industry, so it will not be described in detail herein. As for the configuration of the output selector 20 in the known Viterbi decoder 10, the partial channel response PR(1, 2, 2, 2, 1) is taken as an example below, please refer to FIG. 2 . FIG. 2 is a configuration diagram of an output selector 30 of a known Viterbi decoder whose number of states is 10. Referring to FIG. The output selector 30 includes a minimum selector 32 and an output module 33; the minimum selector 32 includes ten input terminals I0-I9 and ten output terminals O0-O9, for receiving by the input terminals I0-I9 The digital signals output by the memory module are output to the output module 33 through the output terminals O0-O9. Please continue to refer to Table 1, which is a list of output signals of the minimum selector 32 in FIG. 2 . In Table 1, the second row represents various situations of the minimum selector 32, and the first row represents output signals corresponding to various states of the second row. Besides, in FIG. 2 , the output module 33 includes ten AND gates 34 and three OR gates 36 .

Therefore, from the output selector 30, a Viterbi decoder with a known state number of 10 can output reliable results. However, as shown in FIG. 2 and Table 1, it is known that the output selector 30 requires quite complex hardware implementation, and it is bound to consume considerable resources to meet the system requirements. Especially as the length of the sequence signal input to the Viterbi decoder increases, the circuit of the output selector will become more complex, resulting in increased system resources and production costs.

Table 1

O9-O0 Condition 0000000001 For 10=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10) 0000000010 For 11=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10) 0000000100 For 12=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10) 0000001000 For 13=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10) 0000010000 For 14=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10) 0000100000 For 15=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10) 0001000000 For 16=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10) 0010000000 For 17=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10) 0100000000 For 18=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10) 1000000000 For 19=min(19, 18, 17, 16, 15, 14, 13, 12, 11, 10)

Contents of the invention

Therefore, the main purpose of the present invention is to provide a method for determining an output signal of a Viterbi decoder and an output selector thereof, which greatly reduces circuit complexity, thereby reducing waste of system resources.

The present invention discloses a method for determining the output of a Viterbi decoder, characterized in that it comprises the following steps:

(a) receiving a digital signal decoded by the Viterbi decoder from an input signal and output through a path memory module of the Viterbi decoder;

(b) comparing the sum of the digital signals received in step (a) with one-half of the number of states of the Viterbi decoder; and

(c) determining an output result according to the comparison result of step (b).

Wherein in step (c), when the comparison result of step (b) shows that the sum of the digital signals received by step (a) is less than 1/2 of the state number of this Viterbi decoder, then the output result is equal to digital 0.

Wherein in step (c), when the comparison result of step (b) shows that the sum of the digital signals received by step (a) is greater than 1/2 of the state number of this Viterbi decoder, then the output result is equal to digital 1.

The output selector of a kind of Viterbi decoder of the present invention is characterized in that, it comprises:

a receiving module for receiving the digital signal output by the path memory module of the Viterbi decoder;

A judging module for comparing the sum of the digital signals received by the receiving module with half of the state number of the Viterbi decoder; and

An output module is used for outputting an output result according to the comparison result of the judging module.

Wherein when the comparison result of the judging module shows that the sum of the digital signals received by the receiving module is less than the half of the state number of the Viterbi decoder, the output module judges that the output result is equal to digital 0.

Wherein when the comparison result of the judging module shows that the sum of the digital signals received by the receiving module is greater than the half of the state number of the Viterbi decoder, the output module judges that the output result is equal to digital 1.

Description of drawings

In order to further illustrate the technical content of the present invention, the following detailed description is as follows in conjunction with the embodiments and accompanying drawings, wherein:

FIG. 1 is a schematic functional block diagram of a known Viterbi decoder.

FIG. 2 is a schematic diagram of a configuration of an output selector of a known ten-state Viterbi decoder.

FIG. 3 is a schematic diagram of the output selector of the Viterbi decoder of the present invention.

FIG. 4 is a schematic diagram of the output judgment flow of the Viterbi decoder of the present invention.

Detailed ways

Please refer to FIG. 3 , which is a schematic diagram of the output selector 40 of the Viterbi decoder of the present invention. The output selector 40 includes a receiving module 42 , a judging module 44 and an output module 46 . The receiving module 42 is used to receive N digital signals S1-SN output by the path memory module 41 of the Viterbi decoder, wherein, N represents the state number of the Viterbi decoder; the output module 46 can The result output by group 44 produces a binary output signal DTo. For the operation of the judgment module 44 , please refer to FIG. 4 . FIG. 4 is a schematic diagram of an output signal judgment process 50 of the Viterbi decoder of the present invention. Process 50 includes the following steps:

Step 500: start;

Step 502: Receive digital signals S1-SN;

Step 504: Compare the sum of the digital signals S1-SN with one-half of the state number N; if the sum of the digital signals S1-SN is greater than one-half of the state number N, the process 50 proceeds to step 506, otherwise, then Go to step 508;

Step 506: the output signal is digital 1;

Step 508: the output signal is digital 0;

Step 510: end.

In short, the process 50 compares the N digital signals S1 ˜SN output by the path memory module with half of the state number N (ie N/2) to determine the output signal. For example, for a Viterbi decoder of a high-density multi-functional digital disc player (HD-DVD Drive), it includes ten states, so it only needs to compare the ten digital signals S1～S10 output by its path memory module It can be judged that when the sum of the digital signals S1-S10 is greater than 5, the output signal is a digital 1, otherwise it is a digital 0.

That is to say, when more than half of the digital signals of S1～S10 are digital 1, the sum of S1～S10 must be greater than 5 (that is, N/2); since most of the digital signals are digital 1, therefore We can judge that the possibility of the output signal being the number 1 is the greatest. Conversely, when more than half of the digital signals of S1～S10 are digital 0, the sum of S1～S10 must be less than 5 (that is, N/2); since most of the digital signals are digital 0, we can The possibility of judging that the output signal is a digital 0 is the greatest. The way of judging in this way also conforms to the rule of maximum similarity sequence estimation. Wherein, when the sum of S1-S10 is equal to 5 (that is, N/2); it can be judged as a number 1 or a coefficient number 0 according to the system design.

As mentioned above, N/2 is the best embodiment; we can also make it N/2+1, when the sum of the digital signals of S1～S10 is greater than 6 (that is, N/2+1), it means S1 At least 6 of the digital signals of ~S10 are digital 1; therefore, we can judge that the possibility of the output signal being digital 1 is the greatest. Otherwise, it is judged as the number 0.

From the process 50 , the judging module 44 can judge the output signal and output it to a system through the output module 46 . From the above, it can be seen that the output selector 40 designed according to the process 50 of the present invention greatly reduces the required system resources, and because the process 50 compares the sum of the output digital signals of the path memory module and one-half of the number of states, therefore The judgment module 44 of the present invention only needs one adder and one comparator to judge the signal DTo and output it to the system by the output module 46 .

Compared with the known technology, the present invention greatly reduces circuit complexity, thereby reducing waste of system resources. Furthermore, as mentioned above, as the length of the input signal increases, the states of the known Viterbi decoder will increase, so that the circuit complexity of the output selector will increase. However, the judging module of the output selector in the present invention only needs to use one adder and one comparator to judge the output signal regardless of the length of the input signal, which improves the shortcomings of the known technology.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Claims (6)

1. A method for determining the output of a Viterbi decoder, characterized in that it comprises the following steps: (a) receiving a digital signal decoded by the Viterbi decoder from an input signal and output through a path memory module of the Viterbi decoder; (b) comparing the sum of the digital signals received in step (a) with one-half of the number of states of the Viterbi decoder; and (c) determining an output result according to the comparison result of step (b). 2. The method for determining the output of a Viterbi decoder as claimed in claim 1, wherein in step (c), when the comparison result of step (b) shows that the digital signal received by step (a) When the sum of is less than one-half of the number of states of the Viterbi decoder, the output is equal to the number 0. 3. The method for determining the output of a Viterbi decoder as claimed in claim 1, wherein in step (c), when the comparison result of step (b) shows that the digital signal received by step (a) When the sum of is greater than one-half of the number of states of the Viterbi decoder, the output is equal to the number 1. 4. an output selector of a Viterbi decoder, characterized in that it comprises: a receiving module for receiving the digital signal output by the path memory module of the Viterbi decoder; A judging module for comparing the sum of the digital signals received by the receiving module with half of the state number of the Viterbi decoder; and An output module is used for outputting an output result according to the comparison result of the judging module. 5. The output selector of Viterbi decoder as claimed in claim 4, is characterized in that, wherein when the comparison result of this judging module shows that the sum of the digital signals that this receiving module receives is less than that of this Viterbi decoder When the number of states is one-half, the output module judges that the output result is equal to the number 0. 6. The output selector of the Viterbi decoder as claimed in claim 4, wherein when the comparison result of the judging module shows that the sum of the digital signals received by the receiving module is greater than that of the Viterbi decoder When the number of states is one-half, the output module judges that the output result is equal to the number 1.

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