CN100464413C - Circuit and chip for inter-changing chip pin function - Google Patents
Circuit and chip for inter-changing chip pin function Download PDFInfo
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- CN100464413C CN100464413C CNB2004101025498A CN200410102549A CN100464413C CN 100464413 C CN100464413 C CN 100464413C CN B2004101025498 A CNB2004101025498 A CN B2004101025498A CN 200410102549 A CN200410102549 A CN 200410102549A CN 100464413 C CN100464413 C CN 100464413C
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Abstract
The circuit is used in switching the function of first pin and second pin. It at least consists a switching unit that can control the interchange selecting terminal switching between first pin and second pin, and first, second, third and fourth signal terminal. When the interchange selection terminal is at first level, the first signal terminal gets through the third signal terminal; the third signal terminal gets through the fourth signal terminal. The chip consists of multi pins, inner circuit unit, and switching unit used in switching functions of first pin and second pin. The switching unit consists of interchange selection terminal, and first, second, third and fourth signal terminal. Two of signal terminals are separately connected with first and second pin. The other two are separately connected with inner circuit unit.
Description
Technical field
The present invention relates to realize the circuit of exchange function, relate in particular to a kind of circuit and chip thereof of realizing that chip pin function exchanges.
Background technology
Figure 1 shows that chip exterior pin and internal circuit unit corresponding relation schematic diagram, the external terminal A of chip is communicated with by signal end 1 with the internal circuit of chip, and the external terminal B of chip is communicated with by signal end 2 with the internal circuit of chip.The input signal of pin A is handled by the internal circuit that signal end 1 is input to chip, and the output signal of pin A is produced by the internal circuit of chip, outputs to pin A through signal end 1; The input signal of pin B is handled by the internal circuit that signal end 2 is input to chip, and the output signal of pin B is produced by the internal circuit of chip, outputs to pin B through signal end 2.
In the design process of chip, need update the design of chip, may have different versions with a kind of chip, the pin arrangement mode of the same a kind of chip between different editions is also not quite identical sometimes.
Because the applied environment of chip might not the change along with the edition upgrading of chip, therefore occur sometimes in actual applications because of the chip application environmental limit causes chip pin to be arranged can't compatible problem.
Summary of the invention
The object of the present invention is to provide and a kind ofly realize the circuit that chip pin function exchanges and have the chip that pin exchanges function, with solve in the prior art because of the chip application environmental limit causes chip pin to be arranged can't compatible problem.
For addressing the above problem, the invention provides following technical scheme:
A kind of circuit of realizing that chip pin function exchanges, this circuit comprises crosspoint at least, this crosspoint has:
The exchange selecting side of control chip pin function exchange;
First, second, third, fourth signal end is used for input and/or output signal;
When described exchange selecting side was first level, described first signal end was communicated with the 3rd signal end, and described secondary signal end is communicated with described the 4th signal end; When described exchange selecting side was second level, described first signal end was communicated with described the 4th signal end, and described secondary signal end is communicated with described the 3rd signal end;
Wherein:
Described crosspoint comprises first, second identical gate; The signal of described first signal end is imported the second input (S of first gate respectively
2) and the first input end (S of second gate
1), the signal of described secondary signal end is imported the first input end (S of first gate respectively
1) and the second input (S of second gate
2), the gating output (D) of first gate is connected with the 4th signal end, and the gating output (D) of second gate is connected with the 3rd signal end, and the control end of first, second gate (C) is connected with the exchange selecting side respectively;
When described exchange selecting side is first level, the first input end (S of described first, second gate
1) respectively by gating; When described exchange selecting side is second level, the second input (S of described first, second gate
2) respectively by gating.
A kind of circuit of realizing that chip pin function exchanges, this circuit comprises crosspoint at least, this crosspoint has:
The exchange selecting side of control pin function exchange;
First, second, third, fourth signal end is used for input and/or output signal;
When described exchange selecting side was first level, described first signal end was communicated with the 3rd signal end, and described secondary signal end is communicated with described the 4th signal end; When described exchange selecting side was second level, described first signal end was communicated with described the 4th signal end, and described secondary signal end is communicated with described the 3rd signal end;
Wherein:
Described crosspoint comprises the first, second, third and the 4th identical gate, and a plurality of buffers that are used to isolate input, output signal;
The input signal of described first signal end is imported of first gate respectively by the 5th buffer (5)
The input signal of described first signal end is imported the second input (S of first gate respectively by first buffer (5)
2) and the first input end (S of second gate
1), the signal of described secondary signal end is imported the first input end (S of first gate respectively by second buffer (8)
1) and the second input (S of second gate
2), the gating output (D) of first gate is connected with the 4th signal end by the 3rd buffer (9), and the gating output (D) of second gate is connected with the 3rd signal end by the 4th buffer (11); The input signal of described the 3rd signal end is imported the second input (S of the 3rd gate respectively by the 5th buffer (12)
2) and the first input end (S of the 4th gate
1), the input signal of described the 4th signal end is imported the first input end (S of the 3rd gate respectively by hex buffer (10)
1) and the second input (S of the 4th gate
2), the gating output (D) of the 3rd gate is connected with the secondary signal end by the 7th buffer (6), the gating output (D) of the 4th gate is connected with first signal end by the 8th buffer (7), and the control end of first, second, third, fourth gate (C) is connected with the exchange selecting side respectively;
When described exchange selecting side is first level, the first input end (S of described first, second, third, fourth gate
1) respectively by gating; When described exchange selecting side is second level, the second input (S of described first, second, third, fourth gate
2) respectively by gating.
A kind of chip with pin exchange function comprises a plurality of pins, the internal circuit unit that is connected with pin; This chip also comprises the crosspoint that is used to exchange first pin and second pin function, and this crosspoint has:
Control the exchange selecting side of first pin and second pin function exchange;
The first, second, third and the 4th signal end, wherein two signal ends connect first and second pins respectively, and two other signal end connects the internal circuit unit respectively;
When described exchange selecting side was first level, described first signal end was communicated with described the 3rd signal end, and described secondary signal end is communicated with described the 4th signal end; When described exchange selecting side was second level, described first signal end was communicated with described the 4th signal end, and described secondary signal end is communicated with described the 3rd signal end;
Wherein:
Described first, second pin is the one way signal input pin, and described first, second signal end is connected with described first, second pin respectively, and described the 3rd, the 4th signal end is connected with described internal circuit unit; Perhaps, described first, second pin is the one way signal output pin, and described the 3rd, the 4th signal end is connected with described first, second pin respectively, and described first, second signal end is connected with described internal circuit unit;
Described crosspoint comprises first, second identical gate; The signal of described first signal end is imported the second input (S of first gate respectively
2) and the first input end (S of second gate
1), the signal of described secondary signal end is imported the first input end (S of first gate respectively
1) and the second input (S of second gate
2), the gating output (D) of first gate is connected with the 4th signal end, and the gating output (D) of second gate is connected with the 3rd signal end, and the control end of first, second gate (C) is connected with the exchange selecting side respectively;
When described exchange selecting side is first level, the first input end (S of described first, second gate
1) respectively by gating; When described exchange selecting side is second level, the second input (S of described first, second gate
2) respectively by gating.
A kind of chip with pin exchange function comprises a plurality of pins, the internal circuit unit that is connected with pin; This chip also comprises the crosspoint that is used to exchange first pin and second pin function, and this crosspoint has:
Control the exchange selecting side of first pin and second pin function exchange;
The first, second, third and the 4th signal end, wherein two signal ends connect first and second pins respectively, and two other signal end connects the internal circuit unit respectively;
When described exchange selecting side was first level, described first signal end was communicated with described the 3rd signal end, and described secondary signal end is communicated with described the 4th signal end; When described exchange selecting side was second level, described first signal end was communicated with described the 4th signal end, and described secondary signal end is communicated with described the 3rd signal end;
Wherein:
Described first, second pin is the two-way signaling pin, and described first, second signal end is connected with described first, second pin respectively, and described the 3rd, the 4th signal end is connected with described internal circuit unit respectively;
Described crosspoint comprises the first, second, third and the 4th identical gate, and a plurality of buffers that are used to isolate input, output signal; The input signal of described first signal end is imported the second input (S of first gate respectively by first buffer (5)
2) and the first input end (S of second gate
1), the signal of described secondary signal end is imported the first input end (S of first gate respectively by second buffer (8)
1) and the second input (S of second gate
2), the gating output (D) of first gate is connected with the 4th signal end by the 3rd buffer (9), and the gating output (D) of second gate is connected with the 3rd signal end by the 4th buffer (11); The input signal of described the 3rd signal end is imported the second input (S of the 3rd gate respectively by the 5th buffer (12)
2) and the first input end (S of the 4th gate
1), the input signal of described the 4th signal end is imported the first input end (S of the 3rd gate respectively by hex buffer (10)
1) and the second input (S of the 4th gate
2), the gating output (D) of the 3rd gate is connected with the secondary signal end by the 7th buffer (6), the gating output (D) of the 4th gate is connected with first signal end by the 8th buffer (7), and the control end of first, second, third, fourth gate (C) is connected with the exchange selecting side respectively;
When described exchange selecting side was first level, described first pin was communicated with the internal circuit unit by the first, the 3rd signal end, and described second pin is communicated with the internal circuit unit by the second, the 4th signal end; When described exchange selecting side was second level, described first pin was communicated with the internal circuit unit by the first, the 4th signal end, and described second pin is communicated with the internal circuit unit by second, third signal end.
Because the present invention has adopted above technical scheme, so have the following advantages:
Circuit that realization chip pin function of the present invention exchanges and chip adopt crosspoint will need the input signal and the output signal of two pins of switch to exchange respectively, solved in the prior art because of the chip application environmental limit causes chip pin to be arranged can't compatible problem, circuit structure of the present invention is simple, design ingeniously, just determine whether carrying out pin function by the level that exchanges the selecting side and exchange.
Description of drawings
Fig. 1 is prior art chips external terminal and internal circuit corresponding relation schematic diagram;
Fig. 2 is the circuit theory diagrams of chip pin function interchange circuit;
Fig. 3 has the structure principle chart that pin exchanges the chip of function;
The principle schematic that Fig. 4 is made of two gates for crosspoint;
Fig. 5, Fig. 6 are the chip structure schematic diagram that comprises crosspoint shown in Figure 4;
Fig. 7 is the chip structure schematic diagram that comprises the crosspoint with four gates.
Want the A of switch, the handshaking of two pins of B, A, B pin whether carry out exchange function by exchange the selecting side receive power supply or bring in and select.
As shown in Figure 2, pin function switched circuit of the present invention is used for the function of the pin A and the pin B of exchange chip, this circuit comprises crosspoint at least, and this crosspoint has exchange selecting side and first, second, third, fourth signal end that is used to control pin A and the exchange of pin B function.
When the exchange selecting side was low level, shown in solid line among Fig. 2, first signal end of crosspoint was communicated with the 3rd signal end, and the secondary signal end is communicated with the 4th signal end; When the exchange selecting side was high level, as shown in phantom in Figure 2, first signal end of crosspoint was communicated with the 4th signal end, and the secondary signal end is communicated with the 3rd signal end.
Have pin exchange function chip structure as shown in Figure 3, this chip has pin A and pin B, its structure comprises crosspoint and internal circuit unit at least, pin A is connected with crosspoint by a signal end respectively with pin B, is connected by two signal ends between crosspoint and the internal circuit unit.
As shown in Figure 4, when the signal that first, second, third, fourth signal end is transmitted was one way signal, crosspoint had adopted two identical gates, and the signal of first signal end is imported the input S of gate 1 respectively
2Input S with gate 2
1, the signal of secondary signal end is imported the input S of gate 1 respectively
1Input S with gate 2
2, the gating output D of gate 1 is connected with the 4th signal end, and the gating output D of gate 2 is connected with the 3rd signal end, and the control end C of gate 1 and gate 2 is connected with the exchange selecting side respectively.
As shown in Figure 5, if when the signal of pin A and pin B is unidirectional input signal, first signal end is connected with pin A, and the secondary signal end is connected with pin B, and the 3rd, the 4th signal end is connected with the internal circuit unit.In this case, when the exchange selecting side was connected with the ground end VSS of chip, the exchange selecting side was a low level, and the C end of gate 1 and gate 2 is low level, the input S of gate 1 and gate 2
1By gating, the gating output D of gate 1 is input to the 4th signal end with the input signal of pin B respectively, and the gating output D of gate 2 is input to the 3rd signal end with the input signal of pin A; When the exchange selecting side was connected with the power pin VDD of chip, the exchange selecting side was a high level, and the C end of gate 1 and gate 2 is high level, the input S of gate 1 and gate 2
2By gating, the gating output D of gate 1 is input to the 4th signal end with the input signal of pin A respectively, and the gating output D of gate 2 is input to the 3rd signal end with the input signal of pin B.
As shown in Figure 6, if when the signal of pin A and pin B is unidirectional output signal, the 3rd signal end is connected with pin A, and the 4th signal end is connected with pin B, and first, second signal end is connected with the internal circuit unit.In this case, when the exchange selecting side was connected with the ground end VSS of chip, the exchange selecting side was a low level, and the C end of gate 1 and gate 2 is low level, the input S of gate 1 and gate 2
1By gating, the gating output D of gate 1 is input to the 4th signal end with the input signal of secondary signal end respectively, and the gating output D of gate 2 is input to the 3rd signal end with the input signal of first signal end; When the exchange selecting side was connected with the power pin VDD of chip, the exchange selecting side was a high level, and the C end of gate 1 and gate 2 is high level, the input S of gate 1 and gate 2
2By gating, the gating output (D) of gate 1 is input to the 4th signal end with the signal of first signal end respectively, and the gating output D of gate 2 is input to the 3rd signal end with the input signal of secondary signal end.
As shown in Figure 7, when the signal that first, second, third, fourth signal end is transmitted is two-way signaling, in this case, crosspoint has adopted four identical gates and some buffers, first, second signal end is connected with first, second pin respectively, and the 3rd, the 4th signal end is connected with the internal circuit unit respectively.
The input signal of first signal end is imported the input S of gate 1 respectively by buffer 5
2Input S with gate 2
1, the signal of secondary signal end is imported the input S of gate 1 respectively by buffer 8
1Input S with gate 2
2, the gating output D of gate 1 is connected with the 4th signal end by buffer 9, and the gating output D of gate 2 is connected with the 3rd signal end by buffer 11; The input signal of the 3rd signal end is imported the input S of gate 3 respectively by buffer 12
2Input S with gate 4
1, the input signal of the 4th signal end is imported the input S of gate 3 respectively by buffer 10
1Input S with gate 4
2, the gating output D of gate 3 is connected with the secondary signal end by buffer 6, and the gating output D of gate 4 is connected with first signal end by buffer 7, and the control end C of first, second, third, fourth gate is connected with the exchange selecting side respectively.
When the exchange selecting side was connected with the ground end VSS of chip, the exchange selecting side was a low level, and the C end of gate 1～4 is low level, the input S of gate 1～4
1By gating, the gating output D of gate 2 is input to the 3rd signal end with the input signal of pin A, signal is inputed to the internal circuit unit of chip by the 3rd signal end respectively; The gating output D of gate 1 is input to the 4th signal end with the input signal of pin B, signal is inputed to the internal circuit unit of chip by the 4th signal end; The gating output D of gate 3 is with the input signal input secondary signal end of the 4th signal end, input to pin B by the secondary signal end, the gating output D of gate 3 inputs to first signal end with the input signal of the 3rd signal end, inputs to pin A by the 3rd signal end.
When the exchange selecting side was connected with the power pin VDD of chip, the exchange selecting side was a high level, and the C end of gate 1～4 is high level, the input S of gate 1～4
2Respectively by gating, the gating output D of gate 1 is input to the 4th signal end with the input signal of pin A, signal is imported the internal circuit unit of chip by the 4th signal end, the gating output D of gate 2 is input to the 3rd signal end with the input signal of pin B, signal is imported the internal circuit unit of chip by the 3rd signal end; The gating output D of gate 4 is input to first signal end with the input signal of the 4th signal end, by first signal end this signal is inputed to pin A, the gating output D of gate 3 is input to the secondary signal end with the input signal of the 3rd signal end, by the 3rd signal end this signal is inputed to pin B.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (4)
1. a circuit of realizing that chip pin function exchanges is characterized in that this circuit comprises crosspoint at least, and this crosspoint has:
The exchange selecting side of control chip pin function exchange;
First, second, third, fourth signal end is used for input and/or output signal;
When described exchange selecting side was first level, described first signal end was communicated with the 3rd signal end, and described secondary signal end is communicated with described the 4th signal end; When described exchange selecting side was second level, described first signal end was communicated with described the 4th signal end, and described secondary signal end is communicated with described the 3rd signal end;
Wherein:
Described crosspoint comprises first, second identical gate; The signal of described first signal end is imported the second input (S of first gate respectively
2) and the first input end (S of second gate
1), the signal of described secondary signal end is imported the first input end (S of first gate respectively
1) and the second input (S of second gate
2), the gating output (D) of first gate is connected with the 4th signal end, and the gating output (D) of second gate is connected with the 3rd signal end, and the control end of first, second gate (C) is connected with the exchange selecting side respectively;
When described exchange selecting side is first level, the first input end (S of described first, second gate
1) respectively by gating; When described exchange selecting side is second level, the second input (S of described first, second gate
2) respectively by gating.
2. a circuit of realizing that chip pin function exchanges is characterized in that this circuit comprises crosspoint at least, and this crosspoint has:
The exchange selecting side of control pin function exchange;
First, second, third, fourth signal end is used for input and/or output signal;
When described exchange selecting side was first level, described first signal end was communicated with the 3rd signal end, and described secondary signal end is communicated with described the 4th signal end; When described exchange selecting side was second level, described first signal end was communicated with described the 4th signal end, and described secondary signal end is communicated with described the 3rd signal end;
Wherein:
Described crosspoint comprises the first, second, third and the 4th identical gate, and a plurality of buffers that are used to isolate input, output signal;
The input signal of described first signal end is imported the second input (S of first gate respectively by first buffer (5)
2) and the first input end (S of second gate
1), the signal of described secondary signal end is imported the first input end (S of first gate respectively by second buffer (8)
1) and the second input (S of second gate
2), the gating output (D) of first gate is connected with the 4th signal end by the 3rd buffer (9), and the gating output (D) of second gate is connected with the 3rd signal end by the 4th buffer (11); The input signal of described the 3rd signal end is imported the second input (S of the 3rd gate respectively by the 5th buffer (12)
2) and the first input end (S of the 4th gate
1), the input signal of described the 4th signal end is imported the first input end (S of the 3rd gate respectively by hex buffer (10)
1) and the second input (S of the 4th gate
2), the gating output (D) of the 3rd gate is connected with the secondary signal end by the 7th buffer (6), the gating output (D) of the 4th gate is connected with first signal end by the 8th buffer (7), and the control end of first, second, third, fourth gate (C) is connected with the exchange selecting side respectively;
When described exchange selecting side is first level, the first input end (S of described first, second, third, fourth gate
1) respectively by gating; When described exchange selecting side is second level, the second input (S of described first, second, third, fourth gate
2) respectively by gating.
3. one kind has the chip that pin exchanges function, comprises a plurality of pins, the internal circuit unit that is connected with pin; It is characterized in that this chip also comprises the crosspoint that is used to exchange first pin and second pin function, this crosspoint has:
Control the exchange selecting side of first pin and second pin function exchange;
The first, second, third and the 4th signal end, wherein two signal ends connect first and second pins respectively, and two other signal end connects the internal circuit unit respectively;
When described exchange selecting side was first level, described first signal end was communicated with described the 3rd signal end, and described secondary signal end is communicated with described the 4th signal end; When described exchange selecting side was second level, described first signal end was communicated with described the 4th signal end, and described secondary signal end is communicated with described the 3rd signal end;
Wherein:
Described first, second pin is the one way signal input pin, and described first, second signal end is connected with described first, second pin respectively, and described the 3rd, the 4th signal end is connected with described internal circuit unit; Perhaps, described first, second pin is the one way signal output pin, and described the 3rd, the 4th signal end is connected with described first, second pin respectively, and described first, second signal end is connected with described internal circuit unit;
Described crosspoint comprises first, second identical gate; The signal of described first signal end is imported the second input (S of first gate respectively
2) and the first input end (S of second gate
1), the signal of described secondary signal end is imported the first input end (S of first gate respectively
1) and the second input (S of second gate
2), the gating output (D) of first gate is connected with the 4th signal end, and the gating output (D) of second gate is connected with the 3rd signal end, and the control end of first, second gate (C) is connected with the exchange selecting side respectively;
When described exchange selecting side is first level, the first input end (S of described first, second gate
1) respectively by gating; When described exchange selecting side is second level, the second input (S of described first, second gate
2) respectively by gating.
4. one kind has the chip that pin exchanges function, comprises a plurality of pins, the internal circuit unit that is connected with pin; It is characterized in that,
This chip also comprises the crosspoint that is used to exchange first pin and second pin function, and this crosspoint has:
Control the exchange selecting side of first pin and second pin function exchange;
The first, second, third and the 4th signal end, wherein two signal ends connect first and second pins respectively, and two other signal end connects the internal circuit unit respectively;
When described exchange selecting side was first level, described first signal end was communicated with described the 3rd signal end, and described secondary signal end is communicated with described the 4th signal end; When described exchange selecting side was second level, described first signal end was communicated with described the 4th signal end, and described secondary signal end is communicated with described the 3rd signal end;
Wherein:
Described first, second pin is the two-way signaling pin, and described first, second signal end is connected with described first, second pin respectively, and described the 3rd, the 4th signal end is connected with described internal circuit unit respectively;
Described crosspoint comprises the first, second, third and the 4th identical gate, and a plurality of buffers that are used to isolate input, output signal; The input signal of described first signal end is imported the second input (S of first gate respectively by first buffer (5)
2) and the first input end (S of second gate
1), the signal of described secondary signal end is imported the first input end (S of first gate respectively by second buffer (8)
1) and the second input (S of second gate
2), the gating output (D) of first gate is connected with the 4th signal end by the 3rd buffer (9), and the gating output (D) of second gate is connected with the 3rd signal end by the 4th buffer (11); The input signal of described the 3rd signal end is imported the second input (S of the 3rd gate respectively by the 5th buffer (12)
2) and the first input end (S of the 4th gate
1), the input signal of described the 4th signal end is imported the first input end (S of the 3rd gate respectively by hex buffer (10)
1) and the second input (S of the 4th gate
2), the gating output (D) of the 3rd gate is connected with the secondary signal end by the 7th buffer (6), the gating output (D) of the 4th gate is connected with first signal end by the 8th buffer (7), and the control end of first, second, third, fourth gate (C) is connected with the exchange selecting side respectively;
When described exchange selecting side was first level, described first pin was communicated with the internal circuit unit by the first, the 3rd signal end, and described second pin is communicated with the internal circuit unit by the second, the 4th signal end;
When described exchange selecting side was second level, described first pin was communicated with the internal circuit unit by the first, the 4th signal end, and described second pin is communicated with the internal circuit unit by second, third signal end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004101025498A CN100464413C (en) | 2004-12-24 | 2004-12-24 | Circuit and chip for inter-changing chip pin function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004101025498A CN100464413C (en) | 2004-12-24 | 2004-12-24 | Circuit and chip for inter-changing chip pin function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1645603A CN1645603A (en) | 2005-07-27 |
| CN100464413C true CN100464413C (en) | 2009-02-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100416533C (en) * | 2006-09-13 | 2008-09-03 | 四川长虹电器股份有限公司 | Chip pin extension circuit |
| CN100459128C (en) * | 2007-05-14 | 2009-02-04 | 北京中星微电子有限公司 | Wafer for realizing the chip pin compatibility and method |
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| US6281590B1 (en) * | 1997-04-09 | 2001-08-28 | Agere Systems Guardian Corp. | Circuit and method for providing interconnections among individual integrated circuit chips in a multi-chip module |
| US6548910B2 (en) * | 1998-11-20 | 2003-04-15 | Sony Computer Entertainment Inc. | Integrated circuit element, printed circuit board and electronic device having input/output terminals for testing and operation |
| CN2750476Y (en) * | 2004-12-24 | 2006-01-04 | 北京中星微电子有限公司 | Circuit realizing chip pin function switching and chip |
-
2004
- 2004-12-24 CN CNB2004101025498A patent/CN100464413C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281590B1 (en) * | 1997-04-09 | 2001-08-28 | Agere Systems Guardian Corp. | Circuit and method for providing interconnections among individual integrated circuit chips in a multi-chip module |
| US6548910B2 (en) * | 1998-11-20 | 2003-04-15 | Sony Computer Entertainment Inc. | Integrated circuit element, printed circuit board and electronic device having input/output terminals for testing and operation |
| CN2750476Y (en) * | 2004-12-24 | 2006-01-04 | 北京中星微电子有限公司 | Circuit realizing chip pin function switching and chip |
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| CN1645603A (en) | 2005-07-27 |
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