CN100463158C - Thin film flip chip package structure and multi-layer circuit tape structure thereof - Google Patents
Thin film flip chip package structure and multi-layer circuit tape structure thereof Download PDFInfo
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- CN100463158C CN100463158C CNB2006101112777A CN200610111277A CN100463158C CN 100463158 C CN100463158 C CN 100463158C CN B2006101112777 A CNB2006101112777 A CN B2006101112777A CN 200610111277 A CN200610111277 A CN 200610111277A CN 100463158 C CN100463158 C CN 100463158C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
The invention relates to a film flip-chip packaging structure and a multilayer circuit tape structure thereof, wherein the multilayer circuit tape structure mainly comprises a first dielectric layer, a plurality of first layer pins formed on the first dielectric layer, a second dielectric layer covering the first layer pins, a plurality of second layer pins formed on the second dielectric layer, and a solder mask layer covering the solder mask layer of the second layer pins. The first layer of pins and the second layer of pins are respectively provided with a plurality of corresponding first bump joint ends and second bump joint ends which are formed in a flip chip joint area and exposed outside the solder mask layer, so that the resolution or the performance of the chip-on-film packaging product can be improved. Preferably, the first bump joint end and the second bump joint end are strip-shaped and have the height protruding out of the solder mask layer, so that the cost of the solder mask layer can be reduced.
Description
Technical field
The present invention relates to a kind of membrane of flip chip encapsulation (Chip-On-Film packaging) technology, particularly relate to a kind of thin-film flip-chip packaging construction and multilayer circuit rewinding structure thereof.
Background technology
Membrane of flip chip encapsulation (Chip-On-Film, COF packaging) be a kind ofly can replace winding carrying encapsulation (Tape Carrier Package, TCP) technology of new generation, except the progress of wafer joining technique, all the other processing procedures are roughly the same, also can move the circuit coiling tape that is suitable for the membrane of flip chip encapsulation to winding transmission (reel-to-reel) mode with winding.Usually need the wafer of membrane of flip chip encapsulation to have more small size and the projection of greater number (i.e. output/input electrode end), yet the circuit coiling tape of membrane of flip chip encapsulation only is the structure of individual layer circuit usually, promptly all pins all are to be arranged in same one deck, so the design space of pin is limited in the winding, and being subject to the board precision can not unrestrictedly dwindle pin-pitch, therefore can only strengthen the size of change wafer, or the display that only can encapsulate than low-res drives wafer.
Seeing also shown in Figure 1ly, is the schematic cross-section of existing known thin-film flip-chip packaging construction.Existing known thin-film flip-chip packaging construction is to have on wafer 10 chip bonding to the individual layer circuit coiling tapes 100 of projection 11 one, and makes an adhesive body 30 be formed between this wafer 10 and this individual layer circuit coiling tape 100, to seal these projections 11.
See also Fig. 2 and shown in Figure 3, Fig. 2 is the schematic cross-section of the circuit coiling tape structure of existing known thin-film flip-chip packaging construction, and Fig. 3 is the perspective diagram that the circuit coiling tape structure of existing known thin-film flip-chip packaging construction combines with wafer.This individual layer circuit coiling tape 100, have a plurality of single pins 120 that are positioned at 101 both sides, a chip bonding district, these pins 120 be formed on the dielectric layer 110 and by a welding resisting layer 130 the part cover, these pins 120 are revealed in the position of this welding resisting layer 130 then as the bump bond end 121 that engages for these projections 11, and its joint is that Jin-Jin (Au-Au) bonding is comparatively common usually.Because these bump bond ends 121 are to be lower than this welding resisting layer 130, so this welding resisting layer 130 must have the perforate 131 (as shown in Figure 3) that a size is slightly larger than this chip bonding district 101, to appear these all bump bond ends 121, otherwise this welding resisting layer 130 time can flow into this chip bonding district 101 and pollutes to these bump bond ends 121 in printing, and can cause when chip bonding these projections 11 and these bump bond ends 121 bonding smoothly.Therefore, the position that these pins 120 are positioned at this chip bonding district 101 is all exposed by this perforate 131, and long more when development length, it is also many more to appear the position, these pins 120 in encapsulation procedure, take place easily electrical bridge joint with by the problem of particle contamination., have the problem of the wafer that can't encapsulate high-res and high-performance COF product so but the design space of these pins 120 is limited.
TaiWan, China patent announcement No. 505315 " thin-film flip-chip packaging construction " has promptly disclosed a kind of individual layer circuit coiling tape of membrane of flip chip encapsulation, still can meet with above-mentioned identical problem.In addition, TaiWan, China patent announcement No. 483076 " manufacture method of the flexible circuit board of multi-ply construction " has disclosed a kind of multi-layer soft circuit board for chip bonding, the metal wiring of different layers is to electrically connect mutually with the interior metal protuberance that buries, the metal tunicle that the surface of confession wafer bump bond appears is still and is lower than one at the most surperficial welding resisting layer, the distribution complexity causes the cost of integral multi-layered flexible circuit board very high, and also not good for the bonding force of projection.Moreover, the novel patent of TaiWan, China M269571 number " polycrystalline sheet film packaging construction and pliability multilayer circuit board thereof " has disclosed a kind of multi-layer soft circuit board, two line layers in a dielectric layer upper and lower surface can engage with routing for the chip bonding of a plurality of wafers respectively, can't integrate chip bonding, still can't engage bump wafer with arranged or the above arrangement of two rows as single wafer.
This shows that the circuit coiling tape structure of above-mentioned existing membrane of flip chip encapsulation obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new thin-film flip-chip packaging construction and multilayer circuit rewinding structure thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that the circuit coiling tape structure of above-mentioned existing membrane of flip chip encapsulation exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new thin-film flip-chip packaging construction and multilayer circuit rewinding structure thereof, can improve the circuit coiling tape structure of general existing membrane of flip chip encapsulation, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the defective of the circuit coiling tape structure existence of existing membrane of flip chip encapsulation, and the multilayer circuit rewinding structure that provides a kind of new membrane of flip chip to encapsulate, technical problem to be solved is the projection that its arranged that can engage a wafer or many rows (more than two rows) are arranged, in the reducible processing procedure ability of interior pin-pitch, can in the chip bonding district, increase the quantity or the spacing of bump bond end, under existing winding pin making ability, make this multilayer circuit rewinding structure can be applied to more high-res or more high performance membrane of flip chip encapsulation (COF) product, thereby be suitable for practicality more.
Of the present invention time a purpose is, the multilayer circuit rewinding structure that provides a kind of new membrane of flip chip to encapsulate, technical problem to be solved is to make wherein the first bump bond end and the second bump bond end at the different layers pin be strip and all have the height that protrudes in welding resisting layer, make anti-welding can simply the printing form and do not need exposure imaging (no gold-tinted processing procedure) or do not need to use the hole contraposition of attaching, so can reach the low cost of this welding resisting layer forms, the different layers pin respectively is connected with the first outstanding bump bond end and the second bump bond end, the joint that when chip bonding, helps projection, thus be suitable for practicality more.
Another object of the present invention is to, the multilayer circuit rewinding structure that provides a kind of new membrane of flip chip to encapsulate, technical problem to be solved is to make wherein that these ground floor pins and these second layer pins respectively have a plurality of first outer engagement ends and the second outer engagement end, also be revealed in same surface outside the welding resisting layer as the first bump bond end and the second bump bond end, and can drive wafer, thereby be suitable for practicality more for encapsulation high density display.
An also purpose of the present invention is, overcome the defective that existing thin-film flip-chip packaging construction exists, and a kind of new thin-film flip-chip packaging construction, technical problem to be solved are provided is to make its circuit coiling tape have the multilayer pin, with the chip bonding that reaches the little spacing of high density on circuit film.
The object of the invention to solve the technical problems realizes by the following technical solutions.The multilayer circuit rewinding structure that a kind of membrane of flip chip that proposes according to the present invention encapsulates, its upper surface definition has a chip bonding district, and this multilayer circuit rewinding structure comprises: one first dielectric layer; A plurality of ground floor pins, it is formed on this first dielectric layer; One second dielectric layer, it is formed on this first dielectric layer and covers these ground floor pins; A plurality of second layer pins, its be formed on this second dielectric layer and with these ground floor pins be electrical isolation; And a welding resisting layer, it is formed on this second dielectric layer and covers these second layer pins; Wherein, the first bump bond end that most of ground floor pin has a correspondence, the second bump bond end that most of second layer pin has a correspondence, these first bump bond ends and these second bump bond ends are formed in this chip bonding district and are revealed in outside this welding resisting layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The multilayer circuit rewinding structure of aforesaid membrane of flip chip encapsulation, wherein said these first bump bond ends and these second bump bond ends are strip and all have the height that protrudes in this welding resisting layer.
The multilayer circuit rewinding structure of aforesaid membrane of flip chip encapsulation, wherein said most of ground floor pin has one first outer engagement end, most of second layer pin has one second outer engagement end, and these first outer engagement ends and these second outer engagement ends are revealed in outside this welding resisting layer.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of thin-film flip-chip packaging construction that the present invention proposes, it comprises: a multilayer circuit rewinding structure, and its upper surface definition has a chip bonding district; One wafer, it has a plurality of projections and is engaged to this chip bonding district; And an adhesive body, it is formed between this multilayer circuit rewinding structure and this wafer; Wherein, this multilayer circuit rewinding structure comprises: one first dielectric layer; A plurality of ground floor pins, it is formed on this first dielectric layer; One second dielectric layer, it is formed on this first dielectric layer and covers these ground floor pins; A plurality of second layer pins, its be formed on this second dielectric layer and with these ground floor pins be electrical isolation; And a welding resisting layer, it is formed on this second dielectric layer and covers these second layer pins; Wherein, the first bump bond end that most of ground floor pin has a correspondence, the second bump bond end that most of second layer pin respectively has a correspondence, these first bump bond ends and these second bump bond ends are formed in this chip bonding district and are revealed in outside this welding resisting layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid thin-film flip-chip packaging construction, wherein said these first bump bond ends and these second bump bond ends are strip, and all have the height that protrudes in this welding resisting layer.
Aforesaid thin-film flip-chip packaging construction, wherein said most of ground floor pin has one first outer engagement end, most of second layer pin has one second outer engagement end, and these first outer engagement ends and these second outer engagement ends are revealed in outside this welding resisting layer.
The present invention compared with prior art has tangible advantage and beneficial effect.As known from the above, for achieving the above object, multilayer circuit rewinding structure according to a kind of membrane of flip chip encapsulation of the present invention, its upper surface definition has a chip bonding district, a plurality of ground floor pins are formed on one first dielectric layer, one second dielectric layer is formed on this first dielectric layer and covers these ground floor pins, a plurality of second layer pins be formed on this second dielectric layer and with these ground floor pins be electrical isolation, a welding resisting layer is formed on this second dielectric layer and covers these second layer pins.Wherein, these ground floor pins respectively have a plurality of first corresponding bump bond ends and the second bump bond end with these second layer pins, and it is formed in this chip bonding district and is revealed in outside this welding resisting layer.
By technique scheme, the multilayer circuit rewinding structure of membrane of flip chip encapsulation of the present invention has following advantage at least:
1, the multilayer circuit rewinding structure of membrane of flip chip encapsulation of the present invention, utilize a plurality of ground floor pins of a dielectric layer electrical isolation and a plurality of second layer pin, and these ground floor pins respectively have a plurality of first corresponding bump bond ends and the second bump bond end with these second layer pins, it is formed in the chip bonding district and is revealed in outside the welding resisting layer, so can engage the arranged of a wafer or the projection that many rows (more than two rows) arrange, in the reducible processing procedure ability of interior pin-pitch, can in the chip bonding district, increase the quantity or the spacing of bump bond end, under existing winding pin making ability, can make this multilayer circuit rewinding structure can be applied to more high-res or more high performance membrane of flip chip encapsulation (COF) product, be very suitable for practicality.
2, the multilayer circuit rewinding structure of membrane of flip chip encapsulation of the present invention, wherein the first bump bond end and the second bump bond end at the different layers pin is strip and all has the height that protrudes in welding resisting layer, make welding resisting layer simply to print to form and do not need exposure imaging (no gold-tinted processing procedure) or do not need to use the hole contraposition of attaching, when chip bonding, help engaging of projection again so the connection different layers pin and the outstanding first bump bond end and the second bump bond end can reach the low cost formation of this welding resisting layer.
3, the multilayer circuit rewinding structure of membrane of flip chip encapsulation of the present invention, wherein these ground floor pins and these second layer pins respectively have a plurality of first outer engagement ends and the second outer engagement end, also be revealed in same surface outside the welding resisting layer as the first bump bond end and the second bump bond end, can drive wafer for encapsulation high density display.
4, thin-film flip-chip packaging construction of the present invention, utilize a plurality of ground floor pins of a dielectric layer electrical isolation and a plurality of second layer pin to form multilayer circuit rewinding structure, each layer pin respectively is connected with to be given prominence at one of same welding resisting layer surface bump bond end, to reach the chip bonding of the little spacing of high density.
In sum, the present invention is the multilayer circuit rewinding structure of relevant a kind of membrane of flip chip encapsulation, consists predominantly of one first dielectric layer, a plurality of ground floor pin, that is formed on one first dielectric layer and covers the welding resisting layer that second dielectric layer of these ground floor pins, a plurality of second layer pins and that are formed on this second dielectric layer cover these second layer pin welding resisting layers.Wherein, these ground floor pins respectively have a plurality of first corresponding bump bond ends and the second bump bond end with these second layer pins, it is formed in the chip bonding district and is revealed in outside this welding resisting layer, and can promote the resolution or the performance of membrane of flip chip encapsulating products.Preferably, the first bump bond end and the second bump bond end are strip and all have the height that protrudes in welding resisting layer, can reduce the cost of welding resisting layer.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, be a significant progress in technology, and produced handy and practical effect, and the multilayer circuit rewinding structure of more existing membrane of flip chip encapsulation has the outstanding effect of enhancement, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation is the general introduction of technical solution of the present invention only, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the schematic cross-section that has known thin-film flip-chip packaging construction now.
Fig. 2 is the schematic cross-section that has the circuit coiling tape structure of known thin-film flip-chip packaging construction now.
Fig. 3 is the perspective diagram that the circuit coiling tape structure of existing known thin-film flip-chip packaging construction combines with wafer.
Fig. 4 is according to a preferred embodiment of the present invention, a kind of schematic cross-section of multilayer circuit rewinding structure of thin-film flip-chip packaging construction.
Fig. 5 is according to a preferred embodiment of the present invention, the perspective diagram that this multilayer circuit rewinding structure combines with a wafer.
Fig. 6 is that a kind of thin-film flip-chip packaging construction uses the schematic cross-section of this multilayer circuit rewinding structure according to a preferred embodiment of the present invention.
10: wafer 11: projection
20: wafer 21: projection
30: adhesive body 40: adhesive body
100: individual layer circuit coiling tape 101: the chip bonding district
110: dielectric layer 120: pin
121: bump bond end 130: welding resisting layer
131: perforate 200: multilayer circuit rewinding structure
201: 210: the first dielectric layers in chip bonding district
220: 221: the first bump bond ends of ground floor pin
230: the second dielectric layers of 222: the first outer engagement ends
240: 241: the second bump bond ends of second layer pin
242: the second outer engagement ends 250: welding resisting layer
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, its embodiment of multilayer circuit rewinding structure, structure, feature and the effect thereof of the membrane of flip chip encapsulation that foundation the present invention is proposed, describe in detail as after.
According to a specific embodiment of the present invention, see also Fig. 4, shown in Figure 5, Fig. 4 is a kind of schematic cross-section of multilayer circuit rewinding structure of thin-film flip-chip packaging construction, Fig. 5 is the perspective diagram that this multilayer circuit rewinding structure combines with a wafer.
See also shown in Figure 5, the multilayer circuit rewinding structure 200 of the concrete preferred embodiment of the present invention, the surface is that definition has a chip bonding district 201 thereon, the active surface (as shown in Figure 6) of same wafer 20 such as its size is rough.And please shown in Figure 4 in conjunction with consulting, this multilayer circuit rewinding structure 200 includes one first dielectric layer 210, a plurality of ground floor pin 220, one second dielectric layer 230, a plurality of second layer pin 240 and a welding resisting layer 250; Wherein:
This first dielectric layer 210 and this second dielectric layer 230, as the carrier of these ground floor pins 220 with these second layer pins 240, its material can be polyimides (polyimide, PI).
These ground floor pins 220 are to be formed on this first dielectric layer 210, and each most ground floor pin 220 has one first bump bond end 221 and one first outer engagement end 222.
This second dielectric layer 230 is to be formed on this first dielectric layer 210 and to cover these ground floor pins 220.
These second layer pins 240 are to be formed on this second dielectric layer 230, and make these second layer pins 240 and these ground floor pins 220 be electrical isolation by the interval of this second dielectric layer 230.Wherein, Da Bufen each second layer pin 240 has one second bump bond end 241 and one second outer engagement end 242.
This welding resisting layer 250 is to be formed on this second dielectric layer 230, and covers these second layer pins 240.
Wherein, these first bump bond ends 221 and these second bump bond ends 241 all are to be formed in this chip bonding district 201, and are revealed in outside this welding resisting layer 250.
In addition, in the present embodiment, above-mentioned these first outer engagement ends 222 and these second outer engagement ends 242, be that the fan-out shape disperses and is revealed in outside this welding resisting layer 250, all be emerging in the upper surface of this multilayer circuit rewinding structure 200 so as these first bump bond ends 221 and these second bump bond ends 241, drive wafer 20 for encapsulation high density display.
Please consult shown in Figure 4 again, preferably, these first bump bond ends 221 are strip and all have the height that protrudes in this welding resisting layer 250 with these second bump bond ends 241, for example can utilize electroplating process to form the outstanding position that thickens of these first bump bond ends 221 and these second bump bond ends 241.Therefore, this welding resisting layer 250 can be selected the non-conductive printing ink of non-photosensitive for use, simply be formed at the upper surface (being chip bonding face) of this multilayer circuit rewinding structure 200 in modes such as screen printing or steel plate printings, do not need exposure imaging (no gold-tinted processing procedure) to form perforate (as shown in Figure 5), or do not need to use the hole contraposition of attaching mode, these first bump bond ends 221 and these second bump bond ends 241 that can appear predetermined area, and the bridge joint that can prevent 241 at these first bump bond ends 221 and these second bump bond ends causes electrical short circuit, and the telecommunications that can avoid particle contamination to this chip bonding district 201 to cause is disturbed.Connect different layers pin and the outstanding first bump bond end 221 and the second bump bond end 241 so utilize, nature can be exposed at the surface of this welding resisting layer 250 outward, the engineering that does not need exposure imaging, and the interior pin that can help projection 21 when chip bonding engages, form so can reach the low cost of this welding resisting layer 250.
See also Fig. 5 and shown in Figure 6, Fig. 5 is according to a preferred embodiment of the present invention, the perspective diagram that this multilayer circuit rewinding structure combines with a wafer, Fig. 6 are that a kind of thin-film flip-chip packaging construction uses the schematic cross-section of this multilayer circuit rewinding structure according to a preferred embodiment of the present invention.One wafer 20, it is projection 21 with arranged or many rows (more than two rows) arrangement, but chip bonding is in this chip bonding district 201 of this multilayer circuit rewinding structure 200, and these projections 21 are to be engaged to these to be connected in different layers pin and the outstanding first bump bond end 221 and the second bump bond end 241.In the present embodiment, these first bump bond ends 221 are short strip shape with the outstanding position of thickening of these second bump bond ends 241, and its length can be slightly larger than these projections 21, and its width is to be slightly less than these projections 21.
And, can spot printing or alternate manner one adhesive body 40 is formed between this multilayer circuit rewinding structure 200 and this wafer 20, to make a thin-film flip-chip packaging construction (as shown in Figure 6).Therefore, in the reducible processing procedure ability of interior pin-pitch, can in chip bonding district 201, increase the quantity or the spacing of bump bond end 221,241, promptly in the zone in same chip bonding district 201, can hold the quantity of more bump bond ends 221,241, and make this multilayer circuit rewinding structure 200 can be applied to more high-res or more high performance COF (membrane of flip chip encapsulation) product.Perhaps, when the fixed amount of projection 21 abutting ends, it is big that the pin design space becomes, so utilize the ground floor pin 220 and second layer pin 240 that are positioned at different layers, can make these the first bump bond ends 221 and the interval of these second bump bond ends 241 also become big thereupon, do not need to use the high accuracy board can carry out the chip bonding operation, be very suitable for practicality.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (6)
1. the multilayer circuit rewinding structure of a membrane of flip chip encapsulation is characterized in that its upper surface definition has a chip bonding district, and this multilayer circuit rewinding structure comprises:
One first dielectric layer;
A plurality of ground floor pins, it is formed on this first dielectric layer;
One second dielectric layer, it is formed on this first dielectric layer and covers these ground floor pins;
A plurality of second layer pins, its be formed on this second dielectric layer and with these ground floor pins be electrical isolation; And
One welding resisting layer, it is formed on this second dielectric layer and covers these second layer pins;
Wherein, the first bump bond end that most of ground floor pin has a correspondence, the second bump bond end that most of second layer pin has a correspondence, these first bump bond ends and these second bump bond ends are formed in this chip bonding district and are revealed in outside this welding resisting layer.
2. the multilayer circuit rewinding structure of membrane of flip chip encapsulation according to claim 1 is characterized in that wherein said these first bump bond ends and these second bump bond ends are strip and all have the height that protrudes in this welding resisting layer.
3. the multilayer circuit rewinding structure of membrane of flip chip encapsulation according to claim 1, it is characterized in that wherein said most of ground floor pin has one first outer engagement end, most of second layer pin has one second outer engagement end, and these first outer engagement ends and these second outer engagement ends are revealed in outside this welding resisting layer.
4. thin-film flip-chip packaging construction is characterized in that it comprises:
One multilayer circuit rewinding structure, its upper surface definition has a chip bonding district;
One wafer, it has a plurality of projections and is engaged to this chip bonding district; And
One adhesive body, it is formed between this multilayer circuit rewinding structure and this wafer;
Wherein, this multilayer circuit rewinding structure comprises:
One first dielectric layer;
A plurality of ground floor pins, it is formed on this first dielectric layer;
One second dielectric layer, it is formed on this first dielectric layer and covers these ground floor pins;
A plurality of second layer pins, its be formed on this second dielectric layer and with these ground floor pins be electrical isolation; And
One welding resisting layer, it is formed on this second dielectric layer and covers these second layer pins;
Wherein, the first bump bond end that most of ground floor pin has a correspondence, the second bump bond end that most of second layer pin has a correspondence, these first bump bond ends and these second bump bond ends are formed in this chip bonding district and are revealed in outside this welding resisting layer.
5. thin-film flip-chip packaging construction according to claim 4 is characterized in that wherein said these first bump bond ends and these second bump bond ends are strip, and all has the height that protrudes in this welding resisting layer.
6. thin-film flip-chip packaging construction according to claim 4, it is characterized in that wherein said most of ground floor pin has one first outer engagement end, most of second layer pin has one second outer engagement end, and these first outer engagement ends and these second outer engagement ends are revealed in outside this welding resisting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101112777A CN100463158C (en) | 2006-08-21 | 2006-08-21 | Thin film flip chip package structure and multi-layer circuit tape structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101112777A CN100463158C (en) | 2006-08-21 | 2006-08-21 | Thin film flip chip package structure and multi-layer circuit tape structure thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101131987A CN101131987A (en) | 2008-02-27 |
| CN100463158C true CN100463158C (en) | 2009-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006101112777A Expired - Fee Related CN100463158C (en) | 2006-08-21 | 2006-08-21 | Thin film flip chip package structure and multi-layer circuit tape structure thereof |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101983374B1 (en) * | 2012-11-06 | 2019-08-29 | 삼성디스플레이 주식회사 | Chip on film, display pannel, display device including thereof |
| CN106255310A (en) * | 2016-08-17 | 2016-12-21 | 京东方科技集团股份有限公司 | A kind of COF flexible PCB, display device |
| CN110323201B (en) * | 2019-05-10 | 2021-10-26 | 颀中科技（苏州）有限公司 | Flexible circuit board and chip on film packaging structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004207550A (en) * | 2002-12-26 | 2004-07-22 | Hitachi Cable Ltd | Tape carrier for semiconductor device |
| CN1184683C (en) * | 2000-04-07 | 2005-01-12 | 夏普公司 | Semiconductor device and liquid crystal module using semiconductor device |
| US20050224939A1 (en) * | 2004-04-08 | 2005-10-13 | Toshiharu Seko | Semiconductor device and method for manufacturing same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1184683C (en) * | 2000-04-07 | 2005-01-12 | 夏普公司 | Semiconductor device and liquid crystal module using semiconductor device |
| JP2004207550A (en) * | 2002-12-26 | 2004-07-22 | Hitachi Cable Ltd | Tape carrier for semiconductor device |
| US20050224939A1 (en) * | 2004-04-08 | 2005-10-13 | Toshiharu Seko | Semiconductor device and method for manufacturing same |
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| CN101131987A (en) | 2008-02-27 |
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