CN100463124C

CN100463124C - Manufacturing method for enhancing primitive cell density of MOS grid control transistor

Info

Publication number: CN100463124C
Application number: CNB200710130914XA
Authority: CN
Inventors: 张景超; 刘利峰; 赵善麒
Original assignee: Jiangsu Macmic Science & Technology Co Ltd
Current assignee: Jiangsu Macmic Science & Technology Co Ltd
Priority date: 2007-08-31
Filing date: 2007-08-31
Publication date: 2009-02-18
Anticipated expiration: 2027-08-31
Also published as: CN101118858A

Abstract

The present invention relates to a manufacturing method for increasing the MOS gate controlling transistor primitive cell density. firstly, Gate oxidation; secondly, multi-crystal silicon deposition; thirdly, the multi-crystal silicon intermingles to form a conducting layer; fourthly, a first layer of an insulation medium layer is formed; fifthly, the first layer of the insulation medium layer and the multi-crystal silicon layer are photoengraved and etched to form windows, the width of the window is from 1.2 micro meters to 4 micro meters; sixthly, ions are filled in and diffused to form a first impurity layer; seventhly, ions are filled in and diffused to form a second impurity layer; eighthly, the second layer of the insulation medium layer is deposited; ninthly, the second layer of the insulation medium layer is etched; tenthly, the second impurity layer is etched to form a source hole or an emitter hole; eleventhly, metal layers deposit to form electrodes. The present invention can increase the number of primitive cells within the unit area of the active area, so as to increase the electric current density in the active area, thereby the pipe core can be made smaller under the situation that various parameters of the element is unchanged.

Description

Increase the manufacture method of mos gate oxide-semiconductor control transistors primitive unit cell density

Technical field

The present invention relates to a kind of manufacture method of power semi-conductor discrete device, especially relate to a kind of manufacture method that increases mos gate oxide-semiconductor control transistors primitive unit cell density.

Background technology

At present in the manufacturing process of power MOSFET, IGBT, MCT constant power device, active area structure is deposit polysilicon on gate oxide normally, then to the polysilicon photoetching, in the window that etches, inject first kind of foreign ion, diffuse to form first kind of impurity layer, the ion that carries out second kind of impurity again injects and diffusion, deposit insulating medium layer, last photoetching source hole or emitter hole.Because source hole or emitter hole are the centre positions that is positioned at window, the distance between source hole or emitter hole and the polysilicon is subjected to the restriction of photoetching alignment deviation, and the distance between source hole or emitter hole aperture and the polysilicon is more than 1.5 μ m.The size of source hole or emitter hole is subjected to the etching condition restriction again in addition, therefore the aperture width of source hole or emitter hole is usually more than 2 μ m, add the deviation of Twi-lithography process window, make the window pitch between the polysilicon in fact often surpass 6 μ m, cause primitive unit cell quantity minimizing in the active area unit are, current density reduces.

Summary of the invention

The purpose of this invention is to provide a kind of manufacture method that can increase primitive unit cell quantity in the mos gate oxide-semiconductor control transistors active area unit are.

The present invention is that the technical scheme that achieves the above object is: a kind of manufacture method that increases mos gate oxide-semiconductor control transistors primitive unit cell density is characterized in that; Carry out according to the following steps:

(1), gate oxidation: the silicon chip after the clean is carried out gate oxidation form gate oxide, gate oxide thickness exists

(2), polysilicon deposit: deposit polysilicon layer on gate oxide, the polysilicon layer THICKNESS CONTROL exists

(3), ion doping: to the polysilicon layer formation conductive layer that mixes;

(4), form the ground floor insulating medium layer: the polysilicon layer surface after doping forms the ground floor insulating medium layer, and the THICKNESS CONTROL of ground floor insulating medium layer exists

(5), photoetching: photoetching and etching ground floor insulating medium layer and polysilicon layer, form window, window width is controlled at 1.2 μ m～4 μ m;

(6), first foreign ion injects and diffusion: first kind of foreign ion injected in the window, diffuse to form first impurity layer under 1000 ℃～1250 ℃ temperature;

(7), second foreign ion injects and diffusion: second kind of foreign ion injected in the window, under 900 ℃～1100 ℃ temperature, diffuse to form second impurity layer and diffuse to form second impurity layer, and the type of this second kind of foreign ion is different with first kind of foreign ion type;

(8), the deposit and the backflow of second layer insulating medium layer: at silicon chip surface deposit second layer insulating medium layer, the THICKNESS CONTROL of second layer insulating medium layer exists

Carry out reflow treatment then;

(9), second layer insulating medium layer etching: anisotropic etching second layer insulating medium layer forms second layer dielectric side wall layer;

(10), source region silicon etching: etching second impurity layer forms source hole or emitter hole, and the degree of depth of source hole or emitter hole surpasses second kind of impurity layer;

(11), metal level deposit: silicon chip sputter or evaporated metal layer are formed electrode.

The present invention generates the ground floor insulating medium layer after the polysilicon deposit, deposit second layer insulating medium layer behind etching polysilicon, by the ground floor insulating medium layer follow-up polysilicon upper surface and source metal or emitter metal are isolated, second layer dielectric side wall layer is then isolated follow-up polysilicon sidewall and source metal or emitter metal, therefore can directly form source hole or emitter hole by etching technics.The present invention since not light requirement carve source hole or emitter hole, window width can be controlled between 1.2um～4um, can increase the quantity of primitive unit cell in the active area unit are, current density on the active area unit are is increased more than 10%, and that therefore tube core can be done under the constant situation of device parameters is littler.The present invention has cancelled source hole or emitter hole photoetching process, and its size is not subjected to the restriction of craft precision, also is not subjected to the restriction of photoetching alignment deviation, and technology is simpler, can reduce cost of manufacture.

Embodiment

The present invention increases the manufacture method of mos gate oxide-semiconductor control transistors primitive unit cell density, carries out according to the following steps,

(1), gate oxidation: the silicon chip after the clean is put into high temperature furnace, carry out gate oxidation under 950 ℃～1050 ℃ conditions, form gate oxide, the thickness of gate oxide exists

(2), polysilicon deposit: silicon chip is put into the deposit stove, utilize low pressure chemical vapor deposition (LPCVD) deposit polysilicon layer on gate oxide, the THICKNESS CONTROL of polysilicon layer exists

This thickness generally can be controlled in Can determine the concrete thickness of polysilicon layer according to the designing requirement of device.

(3), ion doping: silicon chip is put into diffusion furnace, at 900 ℃～1000 ℃ to the polysilicon layer formation conductive layer that mixes.

(4), form the ground floor insulating medium layer: the polysilicon layer surface after doping forms the ground floor insulating medium layer, and the THICKNESS CONTROL of insulating medium layer exists This ground floor insulating medium layer is that silicon chip is put into high temperature furnace, under 950 ℃～1150 ℃, polysilicon layer after mixing is carried out oxidation form oxide layer, follow-up polysilicon upper surface and source metal or emitter metal are isolated, preferably this thickness of oxide layer exists

Ground floor insulating medium layer of the present invention can also be earlier silicon chip to be put into high temperature furnace, under 950 ℃～1150 ℃, the polysilicon layer after mixing is carried out oxidation form oxide layer, and oxidated layer thickness exists Silicon chip is put into the deposit stove, with plasma-reinforced chemical vapour deposition (PECVD), deposition insulating layer on oxide layer, the thickness of insulating barrier exists again

Be preferably in

This insulating barrier can adopt conventional phosphorosilicate glass or boron-phosphorosilicate glass, can guarantee between polysilicon layer and the insulating barrier good bonding force is arranged by this oxide layer.

(5), photoetching: technology applies photoresist, mask, development, etching ground floor insulating medium layer and polysilicon layer at the ground floor insulating medium layer routinely, forms window, and this window width is controlled at 1.2 μ m～4 μ m.

(6), first foreign ion injects and diffusion: first kind of foreign ion injected in the window by ion implantor, this first kind of foreign ion can adopt boron ion or phosphonium ion, it injects energy at 30KeV～120KeV when adopting the boron ion, and implantation dosage is at 5E12～5E14; If when adopting phosphonium ion, it injects energy at 30KeV～180KeV, and implantation dosage diffuses to form first impurity layer at 1000 ℃～1250 ℃ then at 5E12～5E14.

(7), second foreign ion injects and diffusion: second kind of foreign ion injected in the window by ion implantor, the type of this second kind of foreign ion is different with first kind of foreign ion type, can adopt phosphonium ion or arsenic ion, or employing boron ion or boron difluoride ion etc., again silicon chip is put into diffusion furnace, under 900 ℃～1100 ℃ temperature, diffuse to form second impurity layer.

(8), deposit of second layer insulating medium layer and backflow: silicon chip is put into the deposit stove, with plasma-reinforced chemical vapour deposition (PECVD), at silicon chip surface deposit second layer insulating medium layer, this second layer insulating medium layer adopts conventional phosphorosilicate glass or boron-phosphorosilicate glass, make second layer dielectric laminar surface comparatively smooth when reaching reflow treatment, preferably select boron-phosphorosilicate glass for use, second layer dielectric layer thickness exists

Be preferably in

By control to second layer dielectric layer thickness, can stop the movable charge pickup, can guarantee the precision of source hole or emitter hole etching again, then second layer insulating medium layer is carried out reflow treatment.

(9), second layer insulating medium layer etching: with plasma etching machine anisotropic etching second layer insulating medium layer, form second layer dielectric side wall layer, the second dielectric side wall layer is isolated follow-up polysilicon sidewall and source metal or emitter metal.

(10), source region silicon etching: lose second impurity layer with the plasma etching machine engraving and form source hole or emitter hole, and the degree of depth of source hole or emitter hole surpasses second kind of impurity layer.

Claims

1. a manufacture method that increases mos gate oxide-semiconductor control transistors primitive unit cell density is characterized in that; Carry out according to the following steps,

(8), the deposit and the backflow of second layer insulating medium layer: at silicon chip surface deposit second layer insulating medium layer, the THICKNESS CONTROL of second layer insulating medium layer exists Carry out reflow treatment then;

2. the manufacture method of increase mos gate oxide-semiconductor control transistors primitive unit cell density according to claim 1, it is characterized in that: described ground floor insulating medium layer is that silicon chip is put into high temperature furnace, forms oxide layer 950 ℃～1150 ℃ following oxidations, oxidated layer thickness exists

3. the manufacture method of increase mos gate oxide-semiconductor control transistors primitive unit cell density according to claim 1, it is characterized in that: described ground floor insulating medium layer is earlier silicon chip to be put into high temperature furnace, form oxide layer 950 ℃～1150 ℃ following oxidations, at this deposition insulating layer above oxide layer, thickness of oxide layer exists

The thickness of insulating barrier exists

4. the manufacture method of increase mos gate oxide-semiconductor control transistors primitive unit cell density according to claim 1, it is characterized in that: the thickness of described gate oxide exists

5. the manufacture method of increase mos gate oxide-semiconductor control transistors primitive unit cell density according to claim 1, it is characterized in that: the thickness of described polysilicon layer exists

6. the manufacture method of increase mos gate oxide-semiconductor control transistors primitive unit cell density according to claim 1, it is characterized in that: the thickness of described second layer insulating medium layer exists