CN100461406C - Inspection substrate for display device - Google Patents
Inspection substrate for display device Download PDFInfo
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- CN100461406C CN100461406C CNB2005100758706A CN200510075870A CN100461406C CN 100461406 C CN100461406 C CN 100461406C CN B2005100758706 A CNB2005100758706 A CN B2005100758706A CN 200510075870 A CN200510075870 A CN 200510075870A CN 100461406 C CN100461406 C CN 100461406C
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Abstract
In order to make it possible to easily detect an electrical defect by using an array tester, the present inspection substrate includes: plural scan lines and plural signal lines; plural storage capacitor lines arranged in parallel to the scan lines; storage capacitor elements, each of which uses a part of the storage capacitor line as one of electrodes thereof; storage capacitor upper electrodes formed of the same layer as that for the signal lines and electrically connected to the storage capacitor elements; switching elements arranged on intersection points of the signal lines and the scan lines and electrically connected to the storage capacitor elements; and dummy wiring lines formed by use of at least one of two types of metals constituting electrodes of the switching elements, and electrically connected to any of the scan lines, the signal lines, the storage capacitor lines and the storage capacitor upper electrodes.
Description
The cross reference of related application
The application based on and require the priority of Japanese patent application 2004-158796 number submitted on May 28th, 2004 and submission on December 16th, 2004 2004-364964 number, its full content is combined in this by reference.
Technical field
The present invention relates to be used for detect the inspection substrate of the cloth line defect, fault point etc. of the array substrate of display device.
Description of Related Art
In recent years, though be that the commercialization of the high functional liquid crystal device that can high definition shows of high density and big capacity makes progress.In this LCD, often use a kind of active-matrix liquid crystal display device.Active-matrix liquid crystal display device comprises the array substrate, and wherein each district of being separated severally by the multi-strip scanning line that crosses one another and many signal line is confirmed as pixel, is each pixel arrangement switch element, pixel electrode etc.In active-matrix liquid crystal display device, the cross (talk) between the neighbor is little, obtains high-contrast to show, enable reflective demonstration, it is also easy that its area amplifies.
In active-matrix liquid crystal display device, along with the raising of its definition, wiring and little processing of contact hole become essential, and have required the technology rank that keeps high.Therefore, in recent years, produced the process level chip (hereinafter referred to as " PL chip ") that wiring wherein only is provided in the array substrate, the state that connects up in the PL chip carries out electrical measurement with tester, or carries out optical evaluation with flaw detection apparatus.In addition, also actual array formula substrate is checked its circuit defect with array tester, analyze its fault, reach other management of process level and improvement.
But according to the problem that said method exists be, the defective that is detected in the PL chip is always not consistent with the defective on the array substrate, and does not but detect in the PL chip during defective in thinking the array substrate.
And the defective that can detect in the PL chip according to said method only limits on the plane routing pattern and observed in appearance unusual defective.Therefore problem is the assessment that must be used for device property is comprised the characteristic of switch element and contact hole to the assessment of array substrate simultaneously.
In addition, under the situation with array tester inspecting array formula substrate, its defects detection ability is not enough, can not determine the position that defective takes place under some depend on the situation of defect type.Therefore problem is the management and the improvement of implementing process level effectively.
Referring to Fig. 1 and Fig. 2 this point is described.Fig. 1 is the plane graph of wiring pattern in the routine PL chip.Fig. 2 is the plane graph with wiring pattern of contact chain structure.
Form the bending wiring 181 that metallic film is made among Fig. 1, its two ends are receiving electrode pad 183a and 183b respectively.For detecting the fracture of crooked wiring 181, between two electrode pad 183a and 183b, add voltage, and monitor have the electric current of denying to flow through.During no current, in the crooked wiring 181 fracture appears.
Be formed with the bending wiring 191 of contact chain structure among Fig. 2, wherein dispose a plurality of wirings, it is with alternately arranging first metal 193 and second metal 195 to form and be electrically connected mutually with contact hole 197 termination of each metal.Electrode pad 199a and 199b are connected on two terminations of contact chain structure.For detecting the fracture of crooked wiring 191, between two electrode pad 199a and 199b, add voltage, and monitor have the electric current of denying to flow through.During no current, fracture appears in crooked wiring 191.
But, in two kinds of situations as at not seeing in appearance unusually of connecting up, just can not determine the position that fracture takes place.
In addition, in production line, use a kind of incidence of managing defect and the method for invalid state in recent years, its way is to make the process level chip that only disposes various lines and space (L/S) for check in production line, and assesses this process level chip with the tester electrical measurement or with the flaw detection apparatus optical mode.
Utilize in the electric mode defect inspection of array tester, as inspection substrate, the pin that respectively detects of array tester is received each holding wire on the array substrate, thereby implements to measure with actual array substrate.The switch element of each pixel is by open-minded on the array substrate in the measurement, and after this, electric charge stores the holding capacitor of each pixel into by each holding wire, measures the stored charge amount by the detection pin of array tester.By the measurement result that obtains is implemented defect analysis, the characteristic of electric leakage defective, switch element that detects stored charge amount in the holding capacitor of each pixel is unusual, the short circuit/fracture defective of wiring or the like.According to testing result, the technological level of management and improvement production line.
But in the testing result that obtains with array tester, the holding capacitor that check is more little, and with regard to this relevant array tester, the noise effect that is caused by parasitic capacitance is just big more.In general, the feed end that leaves each holding wire when holding capacitor moves, and the influence of parasitic capacitance is big more, thereby the result is to be output the state that it applies gradient along the holding wire direction in output.And, handle about 200 signal line usually simultaneously, the problem of existence is because each of array tester detects the change of sensitivity at input signal, the output result is the striped inhomogeneities between holding wire.
In addition, the problem that exists be because, because the parasitic capacitance of every signal line and the detection of array tester are at the influence of input signal change of sensitivity, even exist the characteristic of the switch element of pixel can not detect abnormal pixel unusually sometimes, therefore evaluation process level chip correctly.
Check defective with array tester simultaneously, can only measure the electrical characteristic of each pixel.Therefore,, be short circuit or open circuit, just must be used in combination the pattern check of optical appearance testing fixture as the defective that is detected for determining defect type.
Summary of the invention
One object of the present invention is to provide the inspection substrate that can easily detect the display device of electric defective.
Another object of the present invention is to provide for the testing result of correction array tester the inspection substrate of check data, and described testing result is subjected to the parasitic capacitance and the influence of each detection at the change of sensitivity of input signal of every signal line.
No matter another purpose of the present invention is the parasitic capacitance of every signal line or each and detects the influence at the change of sensitivity of input signal, the inspection substrate of check data can be provided for the unusual pixel in the characteristic aspect of sense switch element.
No matter a further object of the present invention is the parasitic capacitance of every signal line or each and detects the influence at the change of sensitivity of input signal, can provide the inspection substrate of check data to the defective of certain detection such as short circuit and fracture.
Inspection substrate according to first display device of inventing is characterised in that inspection substrate comprises: multi-strip scanning line and many signal line are configured to cross one another; Many storage capacitor line with the scan line array; Storage capacitor elements, each utilizes a part of storage capacitor line as one of its electrode; The holding capacitor top electrode is formed by the layer identical with the layer of holding wire, and is electrically connected on the storage capacitor elements; Switch element is configured on the intersection point of holding wire and scan line and is electrically connected to storage capacitor elements; And the vacation wiring (dummy wiringline) that utilizes at least two kinds of a kind of formation in the metal that constitutes the switch element electrodes, and be electrically connected in scan line, storage capacitor line, holding wire and the holding capacitor top electrode any.
According to the present invention, multi-strip scanning bar, holding wire, storage capacitor line, storage capacitor elements, holding capacitor top electrode, switch element and false wiring are provided on inspection substrate, and false wiring is electrically connected to arbitrary in scan line, holding wire, storage capacitor line and the holding capacitor top electrode.Like this, the probability that occurs short circuit in the inspection substrate between each wiring can be increased, the short circuit of wiring can be easily detected by the voltage of measuring false wiring with array tester.
Therefore, according to the fault of the relevant short circuit that takes place, the measurable fault that easily is short-circuited in which part or which wiring.Can grasp the performance of technical process according to prediction result, make this result feed back to production line in addition, thereby can increase output.Specifically, can simultaneously the function of checking process level be offered inspection substrate, available array tester is assessed device performance and technological level simultaneously.
Second invention is characterised in that, the wiring region that is formed by holding wire, scan line, storage capacitor line, holding capacitor top electrode, switch element and false wiring is greater than the non-wiring region that does not have any wiring.Like this, wiring density can be done highly, can increase the probability that is short-circuited between each wiring, and can easily detect short circuit with array tester.
The 3rd invention is characterised in that, between the scan line that is configured in storage capacitor line with vacation wiring that the identical metal level of layer of scan line and storage capacitor line forms and forms by the bottom electrode that extends one of two kinds of metals that use constitutes switch element.According to the present invention, the voltage by measuring false wiring is the short circuit between checkout scanning line and the storage capacitor line easily.
The 4th invention according to the 3rd invention is characterised in that false wiring is electrically connected to holding wire.Like this, use the layer identical with storage capacitor line that false wiring is provided, and false wiring is connected to holding wire with scan line between scan line and storage capacitor line.Thereby, by measuring the voltage of false wiring, can check the short circuit between scan line and the storage capacitor line, and definite short dot.Specifically, when short circuit occur in scan line and and the holding capacitor of scan line configured in parallel between the time, though can detect short circuit simply, can not determine short circuit occurs in which part of wiring as line defct by array tester.In contrast, according to the present invention, the vacation wiring that the metal level identical with the layer of scan line and storage capacitor line forms is connected on the holding wire.Short circuit between scan line and the storage capacitor line becomes the intersection short circuit by vacation wiring and holding wire, can determine the point that has been short-circuited according to the position of relevant holding wire.
The 5th invention according to the 3rd invention is characterised in that the inspection substrate of display device further comprises: the holding wire that the top electrode of one of two kinds of metals by extend to use constituting switch element forms; Connect up with the vacation that forms by extension holding capacitor top electrode, wherein adjacent to each otherly configuration signal line, false wiring and holding capacitor top electrode.Like this, increased wiring density, in one deck, easily be short-circuited.Thereby, can easily detect short circuit with array tester, according to the measurable relevant fault that easily is short-circuited of the fault of the relevant short circuit of this generation at which part or any bar circuit.
The 6th invention according to the 3rd invention is characterised in that the inspection substrate of display device further comprises: the holding wire that extends the top electrode formation of switch element; By extending the vacation wiring that the holding capacitor top electrode forms; And dummy electrodes, configuration signal line, false wiring, dummy electrodes and holding capacitor top electrode wherein adjacent to each otherly.By measuring the voltage of false wiring and dummy electrodes, can check with the short circuit between the top electrode of holding capacitor top electrode and switch element in one deck.
The 7th invention according to the 6th invention is characterised in that dummy electrodes is electrically connected to scan line.Like this, can determine the point of short circuit in the scan line.
The 8th invention according to the 7th invention is characterised in that, the size of dummy electrodes and holding capacitor top electrode be the size of being scheduled to or more than, in the part of holding wire, provide preset width or above zone as the Contact welding contact.Like this, can be with dummy electrodes, holding capacitor top electrode and scan line Contact welding contact as the probe etc. of accepting array tester, can be accurately and check short circuit effectively with array tester etc.
Inspection substrate according to the 9th display device of inventing is characterised in that inspection substrate comprises: multi-strip scanning line and many signal line are configured to cross one another; Many storage capacitor line with the scan line configured in parallel; Storage capacitor elements, each utilizes a part of storage capacitor line as one of its electrode; The holding capacitor top electrode is formed by the layer identical with the layer of holding wire, and is electrically connected to storage capacitor elements; And switch element, be configured on the intersection point of holding wire and scan line and be electrically connected to storage capacitor elements, at least one be crooked in holding wire and the scan line wherein.
According to the present invention, at least one is crooked in holding wire and the scan line.Therefore, at least one length of arrangement wire is lengthened out in holding wire and the scan line, has increased the probability of its rupture (open circuit).By measure the fault of the relevant open circuit that takes place with array tester, measurable easy generation fracture defect is at which part or which bar circuit.
The tenth invention according to the 9th invention is characterised in that the holding wire bending is on storage capacitor line.Usually, appear at a wiring down when layer with such as the wiring of storage capacitor line, this relevant wiring is tended to than these layers not occurring and thinner when connecting up.Among the present invention, the holding wire bending is routed on the storage capacitor line, therefore can determines which kind of degree holding wire is thinned to.In addition, can determine that holding wire is thinned to the degree that causes fracture.
The 11 invention is characterised in that, inspection substrate further comprises the contact chain structure, the metal that wherein passes through the electrode of two kinds of formations of alternate configurations switch element constitutes at least a of holding wire and scan line, and the termination of holding wire and scan line is electrically connected mutually by contact hole.
According to the present invention, can determine the defective probability of happening of contact hole by the contact chain structure.In addition, for example available array tester detects the contact hole fracture to the contact chain structure.Also can detect the part that fracture has taken place in the contact hole according to the outward appearance of each contact hole.Simultaneously, when contact hole is not observed when unusual in appearance, can determine the part that fracture takes place according to the position of respective signal line.
The 12 the invention be characterised in that, the pre-sizing of dummy electrodes and holding capacitor top electrode with edge lengths represent be 10 μ m or more than, the preset width of a part of holding wire be 10 μ m or more than.
Display device inspection substrate according to the 13 invention is characterised in that, inspection substrate comprises: comprise storage capacitor elements and be electrically connected to the check pixel of the switch element of this holding capacitor that described check pixel arrangement is on each intersection point of the multi-strip scanning line of the wiring that crosses one another and many signal line; Have the calibration pixel of memory capacity greater than the storage capacitor elements of the storage capacitor elements of described check pixel with comprising, described calibration pixel is configured at least one end of the feed end of at least one holding wire in the described holding wire and non-feed end.
According to the present invention, described calibration pixel is configured on the feed end or non-feed end of holding wire, and the memory capacity of calibration pixel makes the memory capacity greater than described check pixel, may improve detection sensitivity like this when the electric charge of array tester detection of stored in holding capacitor.Like this, the check data of array tester comparison calibration pixel between holding wire may obtain like this to proofreading and correct because of being subjected to the data of each check of array tester at the array tester output result of input signal change of sensitivity influence.
The 14 invention is characterised in that the distolateral and non-feed of the feed of at least one holding wire is distolateral in described holding wire provides the calibration pixel with same structure on both.
According to the present invention, the calibration pixel with same structure be configured in the distolateral and non-feed of feed of holding wire distolateral on.Therefore, have two calibration pixel of same structure in the more same mutually signal line of array tester, may obtain like this to proofreading and correct by the output result's of the check pixel of effect of parasitic capacitance on the holding wire direction data.
Inspection substrate according to the 15 display device of inventing is characterised in that, comprise storage capacitor elements and the check pixel that is connected to the switch element of this holding capacitor, described check pixel arrangement is on each intersection point of many signal line of the multi-strip scanning line of the wiring that crosses one another; With comprise that characteristic is different from the calibration pixel of the switch element of the switch element of checking pixel.
According to the present invention, provide electrical characteristic to be different from the calibration pixel of the electrical characteristic of checking pixel with switch element.Therefore, as the check data of mutual comparison calibration pixel be positioned near the result of the testing result of the check pixel the calibration pixel, if this check data presents similar electrical characteristic with testing result, array tester can determine that this check pixel is unusual on characteristic so, with and switch element be unusual.
The characteristic of the 16 invention is that calibration pixel comprises a switch element that is different from the switch element of checking pixel in channel width and channel length at least.
According to the present invention, calibration pixel comprises channel width or the different switch element of channel length, so calibration pixel has the electrical characteristic of the switch element that is different from the electrical characteristic of checking pixel.
The inspection substrate of the display device of the 17 invention is characterised in that, comprise: comprise check pixel with the storage capacitor elements that is routed in the storage capacitor line between top electrode and the bottom electrode, with the switch element that is electrically connected to storage capacitor elements, described check pixel arrangement and has prepare defective calibration pixel in advance in its part on each intersection point of many signal line of the multi-strip scanning line of the wiring that crosses one another.
According to the present invention, provide the calibration pixel that comprises defective.Therefore, calibration pixel has the electrical characteristic that is different from the electrical characteristic of checking pixel.Pretend the result for the testing result of the check data of the calibration pixel that relatively comprises mutually circuit defect and check pixel, roughly be equal to mutually as both characteristic, array tester can determine that relevant check pixel has circuit defect so.
The 18 invention is characterised in that two in scan line, holding wire, storage capacitor line and top electrode have prepared defective by short circuit at least.
The 19 invention is characterised in that in scan line and storage capacitor line has prepared defective by opening circuit at least.
Description of drawings
Fig. 1 illustrates wiring pattern in the PL chip.
Fig. 2 illustrates contact chain structure in the PL chip.
Fig. 3 illustrates the inspection substrate plane graph of the display device of first and second embodiment.
Fig. 4 illustrates the wiring of extending in the horizontal direction of a taking-up from a large amount of wirings of Fig. 3 such as the plane graph of scan line and storage capacitor line.
Fig. 5 illustrates from a large amount of wirings of Fig. 3 the wiring of extending in vertical direction of only taking out such as the plane graph of scan line and holding capacitor top electrode.
Fig. 6 illustrates the inspection substrate plane graph of the display device of the 3rd embodiment.
Fig. 7 illustrates the enlarged drawing of contact chain structure among Fig. 6.
Fig. 8 A illustrates the weld locations of detection of broken in the PL chip, and Fig. 8 B is the enlarged drawing of pad.
Fig. 9 A illustrates the weld locations that detects short circuit in the PL chip, and Fig. 9 B is the enlarged drawing of pad.
Figure 10 is the plane graph of the active array type inspection substrate chips profile of the 4th embodiment.
Figure 11 be in the active array type inspection substrate of the 4th embodiment along the holding wire direction be configured in feed on distolateral the check pixel and the enlarged drawing of calibration pixel.
Figure 12 be in the chip of active array type inspection substrate of the 4th embodiment along the holding wire direction be configured in non-feed on distolateral the check pixel and the enlarged drawing of calibration pixel.
Figure 13 is the plane graph of the active array type inspection substrate chips profile of the 5th embodiment.
Figure 14 is along the calibration pixel of holding wire configuration and near the enlarged drawing of the check pixel it in the chip of active array type inspection substrate of the 5th embodiment.
Figure 15 is the enlarged drawing of the switch element of the check pixel in the active array type inspection substrate of the 5th embodiment.
Figure 16 is the enlarged drawing of the switch element of the calibration pixel in the active array type inspection substrate of the 5th embodiment.
Figure 17 is along the check pixel of scan-line direction configuration and the enlarged drawing of calibration pixel in the chip of active array type inspection substrate of the 6th embodiment.
Embodiment
First embodiment
Shown in the plane graph of Fig. 3, on glass substrate, make the inspection substrate of the display device among first embodiment, this glass substrate has the array substrate identical materials component of practical application in the liquid crystal display device of the manufacturing process identical with actual array formula substrate, therefore has the electrical characteristic of equivalence with it.When various wiring is provided on inspection substrate, except exist on the actual array formula substrate as scan line and holding wire, also have: the wiring of band special pattern wherein for being used for checking the place that easily breaks down during making, increases the fault probability of happening as short circuit and fracture; Be electrically connected the wiring of contact hole thereon, be used for the localization of faults.For example, use false wiring or crooked wiring as the wiring that special pattern is arranged.In inspection substrate, its size and shape needn't be identical with actual array formula substrate, but but appropriate change size and shape check being suitable for.
Fig. 4 only schematically illustrates wiring such as the scan line and the storage capacitor line of horizontal expansion among Fig. 3, and it is to take out in a large amount of wirings from the inspection substrate of Fig. 3.Fig. 5 only schematically illustrates wiring such as the holding wire and the holding capacitor top electrode of longitudinal extension among Fig. 3, and it is to take out in a large amount of wirings from the inspection substrate of Fig. 3.The cross symbol or the oblique line symbol that draw in the square of attention Fig. 3 represent that its size is the contact hole 27a to 27g of several millimeters long in every limit.
Referring to Fig. 3, Fig. 4 and Fig. 5 various wirings in the inspection substrate of present embodiment are described below.In this inspection substrate, multi-strip scanning line 11 cloth become array crooked separately simultaneously.Many signal line 13 cloth become array crooked separately simultaneously, intersect with multi-strip scanning line 11.In addition, 15 pairs of multi-strip scanning lines 11 of many storage capacitor line separately cloth become array.
To each holding wire 13, with each holding wire 13 a plurality of holding capacitor top electrodes 17 of structuring the formation in one deck.In addition, provide storage capacitor elements 21, its each form a part by holding capacitor top electrode 17 and holding capacitor bottom electrode 19 as storage capacitor line 15.On each intersection point of scan line 11 and holding wire 13, provide switch element 23.Switch element 23 is the thin-film transistors (TFT) that utilize the polysilicon layer of P-channel-type, is electrically connected to storage capacitor elements 21 by contact hole 27c and 27d.
Specifically, false wiring 25a is electrically connected to holding wire 13 by contact hole 27b, and false wiring 25b is electrically connected to holding wire 13 by contact hole 27g and 27a.
In addition, in inspection substrate, the zone that is formed by scan line 11, holding wire 13, storage capacitor line 15, holding capacitor top electrode 17 and false wiring 25a and 25b is greater than the non-wiring zone that does not have any wiring.
As mentioned above, the same among first embodiment with actual array formula substrate, in inspection substrate, possess scan line 11, holding wire 13, storage capacitor line 15, holding capacitor top electrode 17, holding capacitor bottom electrode 19, storage capacitor elements 21 and switch element 23. False wiring 25a and 25b are provided in the zone beyond the zone that has above-mentioned wiring, and are electrically connected in storage capacitor line 15, the holding capacitor top electrode 17 one.Like this, increased the probability that is short-circuited between each wiring in the inspection substrate, and available array tester is measured the short circuit that the false voltage that connects up easily detects wiring.
In addition, adjacent wire is connected in the different mutually wiring of current potential.In addition, connect up 25 zones that form than not existing the zone of any wiring to be greater by scan line 11, holding wire 13, storage capacitor line 15, holding capacitor top electrode 17, switch element 23 and vacation.Therefore, can further increase the probability that is short-circuited.
Like this, connect up in place part or place according to the measurable relevant fault that easily is short-circuited of the fault of the relevant short circuit that is taken place.Performance according to prediction result grasp technology makes the result feed back to production line in addition, thereby might reduce the generation of defective item.
As mentioned above, can provide the function of checking technological level simultaneously, assess device performance and technological level simultaneously with array tester to inspection substrate.For example, under the condition identical, open switch element 23 in the inspection substrate with actual displayed image on the liquid crystal display device, thereby by the holding wire part of charge charging corresponding to pixel.Then, stopcock element 23, pixel is opened a way once.Switch element 23 is open-minded again then, and using in the past, how the current potential of the variation supervisory signal line 13 of the quantity of electric charge of charging changes.Then, all pixels are checked current potential, thereby the pixel that definite wherein current potential is higher or lower than the normal current potential of pixel there is leak current fault.
Second embodiment
The inspection substrate of second embodiment is extremely shown in Figure 5 as Fig. 3 of first example.Here illustrate and in first embodiment, do not illustrate and be intrinsic structure, function and the effect of second example.
First of this inspection substrate is characterised in that, in storage capacitor line 15 with by extending between the scan line 11 that uses a kind of bottom electrode formation in two kinds of metals that constitute switch element 23, provide false wiring 25a by the metal level identical, and false wiring 25a is connected to holding wire 13 by contact hole 27b with scan line 11 and storage capacitor line 15.Here, the bottom electrode of switch element 23 is grids.
Adopt this structure, can check scan line 11 and the short circuit between the storage capacitor line 15 that scan line 11 is structured the formation that presents with the layer identical, and can determine the point of short circuit with vacation wiring 25a by vacation wiring 25a.Which specifically, when short circuit occurs between scan line 11 and the storage capacitor line 15, in actual array formula substrate,, can not determine of connecting up partly to be short-circuited although can detect short circuit simply as line fault.In contrast, in this inspection substrate, form false wiring 25a by the metal level identical and be connected to holding wire 13, thereby the short circuit between scan line 11 and the storage capacitor line 15 becomes the intersection short circuit by vacation wiring 25a and signal silk 13 with scan line 11 and storage capacitor line 15.Therefore, the available array tester voltage of measuring false wiring 25a is determined the point that has been short-circuited.
Second of this inspection substrate is characterised in that, provide by extending the holding wire 13 of a kind of top electrode 17 formation of using in two kinds of metals that constitute switch element 23, with the vacation wiring 34 that forms by extension holding capacitor top electrode 17, and holding wire 13, false wiring 34 and holding capacitor top electrode 17 dispose adjacent to each other.Here, top electrode is source electrode or drain electrode.
The 3rd of this inspection substrate is characterised in that, provide by extending the holding wire 13 of a kind of top electrode 17 formation of using in two kinds of metals that constitute switch element 23, by extending the vacation wiring 34 that holding capacitor top electrode 17 forms, and dummy electrodes 31, and holding wire 13, false wiring 34, dummy electrodes 31 and holding capacitor top electrode 17 dispose adjacent to each other.
In the second and the 3rd feature, dummy electrodes 31 and false wiring 34 are provided, and are disposed at holding capacitor top electrode 17 contiguous places.Therefore formed high-density wiring, helped with being short-circuited in one deck.Like this, available array tester easily detects short circuit, according to the place part or the place wiring of the relevant fault that easily is short-circuited of failure predication of the relevant short circuit that takes place.
The 4th of this inspection substrate is characterised in that dummy electrodes 31 is electrically connected to scan line 11 by contact hole 27e.Dummy electrodes 31 is connected to scan line 11, therefore, by measure the voltage of dummy electrodes 31 with array tester, can check with the short circuit between scan line in one deck 11 and the storage capacitor line 15, can determine the point of short circuit.
The 5th of this inspection substrate is characterised in that holding capacitor top electrode 17 is set at predetermined size or bigger with the size that is electrically connected to the dummy electrodes 31 of scan line 11, provides preset width or above zone in a part of holding wire 13.The size of dummy electrodes 31 and holding capacitor top electrode 17 set its length of side be about 10 μ m or more than.Above-mentioned zone is defined as has about 10 μ m of width or above dummy electrodes 33.Here dummy electrodes 31 is connected to scan line 11 by contact hole 27e.
Adopt this structure, can be with dummy electrodes 33, holding capacitor top electrode 17, dummy electrodes 31 as the Contact welding contact, be used for admitting the probe of array tester etc.Specifically, manually or automatically with the contact of the probe of array tester dummy electrodes 33, holding capacitor top electrode 17 and dummy electrodes 31, therefore can implement between them, they and the electric-examination between other test.Like this, can measure the characteristic of the monomer of the TFT element that constitutes switch element 23.
The 3rd embodiment
Fig. 6 illustrates the plane graph of inspection substrate among the 3rd embodiment.The basic structure of the inspection substrate of Fig. 6 is similar to the structure that illustrates referring to Fig. 3 to Fig. 5 substantially in first embodiment.First and second features of the 3rd embodiment are as Fig. 3 to Fig. 5 and shown in Figure 6.The 3rd feature of the 3rd embodiment is shown in Fig. 6.
Shown in thick line among Fig. 3 and Fig. 6, first characteristic of this inspection substrate be to scan 11 and holding wire 13 full of twists and turns.More particularly, scan line 11 bends to the zone that makes in one deck wiring and switch element 23 and makes a circulation.The zone that holding wire 13 also bends in one deck wiring and holding capacitor top electrode 17 makes a circulation.
Adopt this structure, the length of arrangement wire of extended scan line 11 and holding wire 13 has increased the rupture probability of (open circuit) of scanning 11 and holding wire 13.Like this, in which part or any bar wiring fracture defect takes place easily according to the fault of the relevant open circuit that takes place is measurable.Point out that though scan line 11 and holding wire 13 both's bendings among Fig. 3 to Fig. 6, this inspection substrate is not limited thereto, just scan 11 and signal 13 at least a must be crooked.
Second feature of this inspection substrate also is holding wire 13 bendings on storage capacitor line 15 except above-mentioned points, and is extremely shown in Figure 6 as Fig. 3.
Generally, there is down layer in a wiring and during such as the such wiring of storage capacitor line 15, and this relevant wiring is tended to than these layers and connected up when not existing thinly.Therefore, when as above-mentioned when placing holding wire 13 above the storage capacitor line 15, holding wire 13 attenuation.Like this, can determine which kind of degree holding wire 13 is thinned to, and holding wire 13 is easy to be cut to which kind of degree etc.In addition, can determine that holding wire is thinned to the degree that causes fracture.
As shown in Figure 6, the 3rd feature of this inspection substrate also is to provide contact chain structure 41 except above-mentioned points.In this contact chain structure, in holding wire 13 and the scan line 11 at least one (holding wire 13 among Fig. 6) constitutes by two kinds of metals that alternate configurations constitutes the electrode of switch element 23, and each termination of holding wire 13 and scan line 11 is electrically connected mutually by contact hole.
Specifically, shown in the enlarged drawing of Fig. 7, holding wire 13 constitutes by top electrode 23a and its bottom electrode 23b that alternately arranges switch element 23.A top electrode 23a and a bottom electrode 23b end points are connected to each other by contact hole 27a and 27g.Here each top electrode 23a is source electrode or drain electrode, and bottom electrode 23b is a grid.When only showing alternately arranging and during coupling part by contact hole, just presenting figure shown in Figure 2, of two kinds of metals although not too accurate.
Adopt above-mentioned contact chain structure 41, increased the probability that contact hole breaks down, available array tester easily detects the fracture of contact hole 27.In addition, when not observing in appearance when unusual, can determine which part fracture occur in according to the position of respective signal line 13 at contact hole 27.
Though note only illustrating typically among Fig. 7 two top electrode 23a and a bottom electrode 23b of contact chain structure, in fact all provide top electrode 23a and bottom electrode 23b to every signal line 13.Certainly, can provide top electrode 23a and bottom electrode 23b to every scan line.
Fig. 8 A illustrates the structure of a plurality of pads 51 of the detection of broken that is used for general PL chip, and Fig. 8 B represents the enlarged drawing of pad 51.A plurality of pads are connected to each other.Resistance between the two ends of a plurality of pads 51 of inspections such as available tester detects the fracture between the pad.
Fig. 9 A illustrates the structure of a plurality of pads 53 that are used for the short circuit of general PL chip detection, and Fig. 9 B illustrates the enlarged drawing of pad 53.Pad 53 is disconnected from each other.Conducting between the inspection pads 53 such as available tester detects the short circuit between each pad.
Point out, in the various embodiments described above, illustrated and adopted the inspection substrate of P channel-type polysilicon layer, but the invention is not restricted to this, the polysilicon layer of also available N channel-type as the active-matrix liquid crystal display device of semiconductor layer.In addition, promptly use other semiconductor layers such as amorphous silicon layer as also obtaining similar effects under the situation of semiconductor layer.
The 4th embodiment
To be similar to the mode of the array substrate that is used in the active-matrix liquid crystal display device substantially, the inspection substrate of present embodiment comprises scan line, holding wire, storage capacitor line, storage capacitor elements and switch element etc., and the employing manufacturing process identical with actual manufacturing process forms.The special use wiring of inspection substrate by forming check thereon, make verifying attachment thereon and wait and simulate actual array formula substrate.Check inspection substrate with array tester, thus allow to assess various wirings in the production line defective, fault point, or the like.
Figure 10 is the plane graph of this inspection substrate chips profile.In this chip, the check pixel A is configured on each intersection point of many signal line of the multi-strip scanning line that crosses one another, and it is distolateral that calibration pixel B is configured in the distolateral and non-feed of feed of every signal line.
Figure 11 is the enlarged drawing of check pixel A and calibration pixel B, and the feed that they are configured in along the holding wire direction in the inspection substrate of Figure 10 is distolateral.Figure 11 illustrates the switch element 204A that comprises storage capacitor elements 203A and be electrically connected to storage capacitor elements 203A, and the check pixel A is configured on the scan line 201A and the intersection point of holding wire 202 of the wiring that crosses one another.In addition, Figure 11 illustrates calibration pixel B, and it comprises the storage capacitor elements 203B of its memory capacity greater than the memory capacity of the storage capacitor elements 203A of check pixel A.
In the check pixel A, storage capacitor elements 203A comprises storage capacitor line 205A, be configured in the top electrode 206A on the storage capacitor line 205A and be positioned at bottom electrode 207A below it.Storage capacitor line 205A is positioned on the scan-line direction and connects up and send to the holding wire 202 of a pel spacing.Near deploy switch element 204A and be electrically connected to top electrode 206A and the bottom electrode 207A intersection point of scan line 201A and holding wire 202.Switch element 204A for example adopts the thin-film transistor (hereinafter referred to as the TFT element) of P channel-type.
Here help to detect the structure of the shape defect, fault point etc. of defective, the contact hole of each wiring in the active array type inspection substrate with the explanation of the check pixel A of Figure 11.In the check pixel A of Figure 11, in the zone beyond scan line 201A, holding wire 202, storage capacitor line 205A, top electrode 206A, bottom electrode 207A and the switch element 204A, the false wiring 208a of the superiors, the intermediate layer false wiring 208b that are electrically connected among scan line 201A, holding wire 202, storage capacitor line 205A, top electrode 206A, bottom electrode 207A and the switch element 204A arbitrary and the false wiring of lowermost layer 208c (below be referred to as false wiring 208) have been disposed.By highdensity like this wiring, increased the probability of the fault that is short-circuited between wiring.
In addition, wiring scan line 201A and holding wire 202 and make its bending.The length of arrangement wire of scan line 201A and holding wire 202 that extended by this way, thus the probability that the fracture defective takes place in every wiring may be increased.In addition, adopting this spline structure to make provides contact hole 210 in holding wire 202, and respectively wiring interconnects by contact hole 210, thereby can increase because the shape defect of contact hole 210 causes the probability that fracture defect takes place.Like this, can easily detect the defective of each wiring in the active array type inspection substrate, the defective and the fault point of each contact hole.
Below be illustrated as the correction influence that each check of array tester brings at the change of sensitivity of input signal on the array tester side and the calibration pixel B that disposes with Figure 11.In the calibration pixel B of Figure 11, storage capacitor elements 203B comprises storage capacitor line 205B, be configured in the top electrode 206B on the storage capacitor line and be positioned at bottom electrode 207B under it.Holding capacitor 205B is arranged on the scan-line direction, be routed to a pel spacing in holding wire 202 intersect.Near the intersection point of scan line 201B and holding wire 202, deploy switch element 204B, and be electrically connected to top electrode 206B and bottom electrode 207B.With the thin-film transistor of P channel-type as switch element 204B.Calibration pixel B is as follows with the difference of check pixel A.Specifically, omit the vacation wiring 208 of check defective, storage capacitor line 205B, the top electrode 206B of formation storage capacitor elements 203B and the area of bottom electrode 207B are set to the twice of the area of check pixel A correspondence, thereby the memory capacity of storage capacitor elements 203B is set the twice of the memory capacity that is about the storage capacitor elements 203A that checks pixel A for.
Therefore as implied above, calibration pixel B is configured in the feed end and the non-feed end of holding wire, and the memory capacity of calibration pixel B is greater than the memory capacity of check pixel A, when the electric charge of array tester detection of stored in holding capacitor, can improve detection sensitivity.Like this, the check data of calibration pixel B between array tester comparison signal line can obtain being used to proofreading and correct because of each check of array tester data at the output result of the affected array tester of change of sensitivity of input signal.
The calibration pixel B that is illustrated as the influence of parasitic capacitance on the correction array tester side holding wire direction with Figure 11 and 12 below and disposes.Figure 12 is the enlarged drawing of check pixel A and calibration pixel B, and it disposes along the distolateral holding wire direction that goes up of non-feed in the chip of the inspection substrate of Figure 10.Be configured in the distolateral calibration pixel B of the feed of holding wire shown in Figure 11 202 and have identical structure with calibration pixel B on the non-feed that is configured in Figure 12 is distolateral, B is on the feed end and non-feed end of same holding wire 2 for the configuration calibration pixel, makes them relative to each other.
Shown in Figure 11 and 12, the calibration pixel B with same structure is configured on the feed end and non-feed end of holding wire 202.Therefore array tester two check data in the more same holding wire mutually with calibration pixel B of same structure, thereby may obtain to be used to proofread and correct data because of the output result of the check pixel A that is subjected to effect of parasitic capacitance on the holding wire direction.
The calibration pixel B is configured on the feed end and non-feed end of each holding wire in the present embodiment, and the memory capacity of each calibration pixel B is greater than the memory capacity of check pixel A.Thereby when the electric charge of array tester detection of stored in holding capacitor, can improve detection sensitivity.Like this, the check data of the calibration pixel B between array tester comparison signal line can obtain being used to proofreading and correct because of each check of array tester data at the output result of the affected array tester of change of sensitivity of input signal.In addition, have the check data of two check pixel B of same structure in the more same mutually holding wire, thereby may obtain to be used to proofread and correct because of being subjected to the data of effect of parasitic capacitance on the holding wire direction.
Specifically, this inspection substrate can be provided as array tester and proofread and correct because of being subjected to parasitic capacitance on the holding wire and checking check data at the testing result of the array tester of the influence of the change of sensitivity of input signal because of each of array tester.
The 5th embodiment
Figure 13 is the chip profile plane graph of inspection substrate in the present embodiment.In this chip, the check pixel A is configured on each intersection point of multi-strip scanning line intersecting each other and many signal line, comprises its calibration pixel B at the characteristic switch element different with check pixel A switch element, is configured on 2 in the chip.Note as in the 4th embodiment with as described in Figure 11, for the shape defect of the defective that helps to detect each bar laying-out and wiring, contact hole, fault point etc., here not only to the check pixel A, and provide false wiring to calibration pixel B, make scan line and holding wire be crooked wiring, and contact hole is provided in the holding wire, be interconnected to each wiring by contact hole.
Figure 14 is the enlarged drawing along the check pixel A of the calibration pixel B of the holding wire direction configuration of Figure 13 and its adjacency.Figure 14 illustrates the check pixel A, and it comprises storage capacitor elements 203A and be electrically connected to the switch element 204A of holding capacitor 203A, and the check pixel A is configured on the intersection point of the scan line 201A that crosses one another and holding wire 202.In addition, Figure 14 illustrates the calibration pixel B that comprises the switch element 204B that is different from switch element 204A on the characteristic.
In the check pixel A, storage capacitor elements 203A comprises storage capacitor line 205A, be configured in the top electrode 206A on the storage capacitor line and be positioned at bottom electrode 207A under it.Storage capacitor line 205A is configured on the scan-line direction, and wiring is crossing with the holding wire in pel spacing.Near the switch element 204A of intersection point that is configured in scan line 201A and holding wire 202 is electrically connected to top electrode 206A and bottom electrode 207A.
Figure 15 is the enlarged drawing of the switch element 204A of check pixel A shown in Figure 14.Among Figure 15, configuration P channel-type TFT is as switch element 204A.The channel width W of this TFT (A) is 4 μ m, and channel length L (A) is 5 μ m.Here be the leakage current when reducing the TFT shutoff, the TFT of two the identical sizes that are connected in series.
Below, be illustrated as channel length L (A) unusual of the switch element 204A that determines that the check pixel A is all with Figure 14 and 16 and the calibration pixel B of configuration.In the calibration pixel B of Figure 14, storage capacitor elements 203B comprises holding capacitor 205B, be configured in the top electrode 206B on the storage capacitor line and be positioned at bottom electrode 207B under it.On scan-line direction, provide storage capacitor line 205B, and wiring is crossing with the holding wire 202 in pel spacing.Near the switch element 204B of intersection point that is configured in scan line 201B and holding wire 202 is electrically connected to top electrode 206B and bottom electrode 207B.
Figure 16 is the enlarged drawing of the switch element 204B of calibration pixel B shown in Figure 14.Configuration P channel-type TFT is as switch element 204B among Figure 16.The channel width W of this TFT (B) is 4 μ m, and channel length L (B) is 3 μ m.Here the also leakage current in order to reduce TFT and to turn-off, the TFT of two the identical sizes that are connected in series.As mentioned above, be similar to check pixel A configuration calibration pixel B, just the channel length L (B) of switch element 204B is shorter than the channel length L (A) of switch element 204A.
Like this, calibration pixel B has the electrical characteristic of switch element 204B, and it is different from the electrical characteristic of the switch element 204A that checks pixel A.Therefore, as the check data of the calibration pixel B that in array tester, shortens mutually channel length L (B) more in advance result with the testing result that is positioned near the check pixel A the calibration pixel B, if check data and testing result present similar electrical characteristic, it is unusual to determine to check the pixel A characteristic so, and switch element 204A channel length is unusual.
Here use the calibration pixel B that comprises switch element 204B with different channel length L (B).Even comprise among wherein the channel width W (B) and channel length L (B) that at least one is the calibration pixel B of different switch element 204B but use, the also available similar fashion of array tester detect near be positioned at the calibration pixel B check pixel A unusually.Here set and be positioned near the reason of the check pixel A of calibration pixel B as the pixel that will compare with it, be because in this check pixel A, in the inspection period, less relatively from the influence of respectively checking pin of the parasitic capacitance of holding wire or array tester to the change of sensitivity of input signal.
Simultaneously for example according to the structure described in the 4th embodiment, be subjected in correction under the situation of each check at the testing result of the array tester of the influence of the change of sensitivity of input signal of the parasitic capacitance of holding wire and array tester, will not check pixel A be positioned at calibration pixel B near.At this moment, according to the check data of a calibration pixel B, array tester can determine respectively to check the unusual of pixel A according to the testing result of all the check pixel A in same chip.
Like this, according to present embodiment, provide to comprise the calibration pixel B that has with the switch element of checking pixel A switch element different qualities.Therefore, as the check data of mutual comparison calibration pixel B and the result of the testing result of check pixel A, if check data presents similar electrical characteristic with testing result, array tester can determine that the check pixel A comprises the switch element 204A that characteristic is unusual so.
Specifically, the inspection substrate of present embodiment can be provided for detecting the unusual check data of check pixel A characteristic that comprises switch element 204A to array tester, and does not consider the influence of each check of the parasitic capacitance of holding wire and array tester at the change of sensitivity of input signal.
Point out,, be not limited thereto structure though the wherein structure of the configuration of 2 in the chip of inspection substrate calibration pixel B has been described in the present embodiment.For example, even the configuration calibration pixel B more than 2 in the chip of inspection substrate, even at the optional position of each holding wire configuration calibration pixel B, check data by mutual comparison calibration pixel B and be positioned near the testing result of the check pixel A the calibration pixel B, array tester can be determined the unusual of check pixel A.
In addition, configuration includes only the check pixel chip of checking pixel A in the inspection substrate.And in inspection substrate, disposing onesize calibration pixel chip as check pixel chip, one of them chip all is set at the calibration pixel B in the arbitrary region of inspection substrate.Therefore, by testing result that relatively obtains from check pixel chip and the check data that obtains from calibration pixel chip between pixel in correspondence with each other, array tester can determine in the check pixel chip all check pixel A unusually.
The 6th embodiment
Figure 17 is the enlarged drawing of check pixel A and calibration pixel B, and they dispose along scan-line direction in a chip of inspection substrate in the present embodiment.Here to point out as among the 4th embodiment with as described in Figure 11, for the shape defect of the defective that helps to detect every wiring, contact hole, fault point etc., provide false wiring to check pixel A and calibration pixel B, scan line and holding wire are made crooked wiring, and contact hole is provided in holding wire, by contact hole and each wire interconnects.
Figure 17 illustrates the check pixel A, comprise the wherein storage capacitor elements 203A of storage capacitor line 205 cloth between top electrode 206A and bottom electrode 207A, and comprising the switch element 204A that is electrically connected to storage capacitor elements 203A, the check pixel A is configured on the intersection point of the scan line 201 that crosses one another and holding wire 202A.In addition, Figure 14 illustrates its part of calibration pixel B and has prepared circuit defect 209 in advance.
In the check pixel A, storage capacitor elements 203A comprises storage capacitor line 205, be arranged on the top electrode 206A on the storage capacitor line and be positioned at bottom electrode 207A under it.Provide storage capacitor line 205 along scan-line direction, and wiring is crossing with holding wire 202A in the distance of a pixel.
Below, be illustrated as and detect the calibration pixel B that the check pixel A of circuit defect is arranged and dispose.Among the calibration pixel B of Figure 17, storage capacitor elements 203B comprises storage capacitor line 205, be arranged on the top electrode 206B on the storage capacitor line and be positioned at bottom electrode 207B under it.Provide storage capacitor line 205 along scan-line direction, and wiring is crossing with holding wire 202B in the distance of a pixel.In addition, storage capacitor line 205 is included in holding wire 202B in one deck and top electrode 206B by the short trouble 209 of short circuit.
As mentioned above, calibration pixel B comprises short trouble 209, thereby has electrical characteristic and be different from the electrical characteristic of checking pixel A.Therefore, as the check data of the calibration pixel B that relatively comprises mutually short trouble 209 be positioned near the result of the testing result of the check pixel A the calibration pixel B, if both characteristics roughly are equal to mutually, array tester can be determined and should relevant check pixel A have short trouble so.
Here set near be arranged in the calibration pixel B check pixel A and be as the reason of the pixel that will compare with it because in this relevant check pixel A during check mutually, less relatively from each check of the parasitic capacitance of holding wire or array tester at the influence of input signal change of sensitivity.
Simultaneously, for example according to the structure described in the 4th embodiment, be subjected in correction under the situation of each check at the testing result of the array tester of the influence of the change of sensitivity of input signal of the parasitic capacitance of holding wire and array tester, will not check pixel A be positioned at calibration pixel B near.At this moment, according to the check data of a calibration pixel B, array tester can determine respectively to check pixel A whether short trouble is arranged according to the testing result of all the check pixel A in same chip.
Therefore, according to present embodiment, provide the calibration pixel B that comprises short trouble 209, thereby calibration pixel B has the electrical characteristic that is different from the electrical characteristic of checking pixel A.Therefore, as the check data of the calibration pixel B that relatively comprises short trouble 209 mutually and the result of the testing result of check pixel A, if both characteristics roughly are equal to mutually, array tester can determine that relevant this check pixel A has short trouble so.
Specifically, the active array type inspection substrate can provide array tester and make the check data that short trouble can reliable Detection, and does not consider the influence of each check of the parasitic capacitance of holding wire and array tester at the change of sensitivity of input signal.
Point out, though illustrated as an example in the present embodiment that by short circuit by all short circuits of calibration pixel, short circuit is not limited to this situation with holding wire and top electrode.If the part that will compare is mutually, the each several part of potential difference takes place in the practical operation of the switch element of pixel between them, then this each several part is connected to each other in advance, short circuit, form calibration pixel, relatively comprise the detection data and the testing result of checking pixel of the calibration pixel of short trouble mutually, thereby may determine to comprise the check pixel of short trouble.For example, wish that in scan line, holding wire, storage capacitor line and the top electrode at least at least two are by short circuit.
In addition, though be that circuit defect has illustrated as an example in the present embodiment that by all defectives of calibration pixel, defective is not limited to this situation with defective.The wiring that constitutes pixel is broken to form in calibration pixel in advance, and relatively comprises the check data and the testing result of checking pixel of the calibration pixel of fracture defect mutually, thereby may determine to comprise the check pixel of fracture defect.For example, wish that for fracture defect one in the scan line and storage capacitor line at least is fracture.
In addition, though to adopt P channel-type polysilicon layer as the active-matrix liquid crystal display device of semiconductor layer each the foregoing description to be described as an example, semiconductor layer and liquid crystal display device are not limited thereto.For example, under the situation of the polysilicon layer that adopts the N channel-type and in the active-matrix liquid crystal display device of another kind of semiconductor layer of employing such as polysilicon layer, also can obtain similar effects.
Claims (19)
1. the inspection substrate of a display device is characterized in that, comprising:
Multi-strip scanning line and many signal line are configured to cross one another;
Separately with many storage capacitor line of scan line configured in parallel;
Storage capacitor elements, each is by the holding capacitor top electrode that forms in identical with described holding wire layer and be that the holding capacitor bottom electrode of the part of each in described a plurality of storage capacitor elements constitutes;
Switch element, each is made of two kinds of metals, and these two kinds of metals comprise the metal of the grid that is electrically connected to described scan line and are electrically connected to the source electrode of described holding wire and described storage capacitor elements separately and the metal of drain electrode; And
Utilize the vacation wiring of at least a formation in the described two kinds of metals that constitute the switch element electrode, and be electrically connected in scan line, storage capacitor line, holding wire and the holding capacitor top electrode any.
2. the inspection substrate of display device as claimed in claim 1 is characterized in that, the wiring region that is formed by holding wire, scan line, storage capacitor line, holding capacitor top electrode, switch element and false wiring is greater than the non-wiring region that does not have any wiring.
3. the inspection substrate of display device as claimed in claim 1, it is characterized in that, by being configured between the scan line that the bottom electrode of one of storage capacitor line and two kinds of metals by extending the electrode that use constitutes switch element forms with vacation wiring that the identical metal level of layer of scan line and storage capacitor line forms.
4. the inspection substrate of display device as claimed in claim 3 is characterized in that, false wiring is electrically connected to holding wire.
5. the inspection substrate of display device as claimed in claim 3 is characterized in that, further comprises: the holding wire that the top electrode of one of two kinds of metals of the electrode by extend to use constituting switch element forms; With
Connect up by the vacation of extending the formation of holding capacitor top electrode,
Configuration signal line, vacation are connected up and the holding capacitor top electrode wherein adjacent to each otherly.
6. the inspection substrate of display device as claimed in claim 3 is characterized in that, further comprises:
The holding wire that forms by the top electrode that extends switch element;
By extending the vacation wiring that the holding capacitor top electrode forms; With
Dummy electrodes,
Configuration signal line, false wiring, dummy electrodes and holding capacitor top electrode wherein adjacent to each otherly.
7. the inspection substrate of display device as claimed in claim 6 is characterized in that, dummy electrodes is electrically connected to scan line.
8. the inspection substrate of display device as claimed in claim 7 is characterized in that,
The size of dummy electrodes and holding capacitor top electrode is the size of being scheduled to or also bigger than predetermined size, provides to have preset width or the zone bigger than preset width can be used as the Contact welding contact in the part of holding wire.
9. the inspection substrate of a display device is characterized in that, comprising:
Multi-strip scanning line and many signal line are configured to cross one another;
Many storage capacitor line with the scan line configured in parallel;
Storage capacitor elements, each is by the holding capacitor top electrode that forms in identical with described holding wire layer and be that the holding capacitor bottom electrode of the part of each in described a plurality of storage capacitor elements constitutes; And
Switch element, each is made of two kinds of metals, and these two kinds of metals comprise the metal of the grid that is electrically connected to described scan line and are electrically connected to the source electrode of described holding wire and described storage capacitor elements separately and the metal of drain electrode,
Wherein, at least one be crooked in holding wire and the scan line.
10. the inspection substrate of display device as claimed in claim 9 is characterized in that, the holding wire bending is on storage capacitor line.
11. the inspection substrate of display device as claimed in claim 9, it is characterized in that, further comprise the contact chain structure, wherein constitute at least a of holding wire and scan line by the described two kinds of metals that constitute the electrode of switch element of alternate configurations, the termination of holding wire and scan line is electrically connected mutually by contact hole.
12. the inspection substrate of display device as claimed in claim 8 is characterized in that, the pre-sizing of dummy electrodes and holding capacitor top electrode represents it is 10 μ m or more than the 10 μ m with edge lengths, and the preset width of a part of holding wire is 10 μ m or more than the 10 μ m.
13. the inspection substrate of a display device is characterized in that, comprising:
Comprise storage capacitor elements and be electrically connected to the check pixel of the switch element of this storage capacitor elements, scan line and holding wire that described check pixel arrangement is on each intersection point of the multi-strip scanning line of the wiring that crosses one another and many signal line; With
Comprise having the calibration pixel of memory capacity greater than the storage capacitor elements of the storage capacitor elements of described check pixel, at least one holding wire, the described calibration pixel of configuration at least one end of the feed end of holding wire and non-feed end.
14. the inspection substrate of display device as claimed in claim 13 is characterized in that, at least one holding wire, provides the calibration pixel with identical configuration on both in that the distolateral and non-feed of the feed of holding wire is distolateral.
15. the inspection substrate of a display device is characterized in that, comprising:
Comprise storage capacitor elements and be electrically connected to the check pixel of the switch element of this storage capacitor elements, scan line and holding wire that described check pixel arrangement is on each intersection point of the multi-strip scanning line of the wiring that crosses one another and many signal line; With
Comprise that characteristic is different from the calibration pixel of the switch element of the switch element of checking pixel.
16. the inspection substrate of display device as claimed in claim 15 is characterized in that, calibration pixel comprises a switch element that is different from the switch element of checking pixel in channel width and channel length at least.
17. the inspection substrate of a display device is characterized in that, comprising:
Comprise check pixel with the storage capacitor elements that is routed in the storage capacitor line between top electrode and the bottom electrode, with the switch element that is electrically connected to storage capacitor elements, scan line and holding wire, described check pixel arrangement on the multi-strip scanning line and each intersection points of many signal line of wiring that cross one another, and
Has the calibration pixel that in its part, has defective in advance.
18. the inspection substrate of display device as claimed in claim 17 is characterized in that, has prepared defective by at least two in short circuit scan line, holding wire, storage capacitor line and the top electrode.
19. the inspection substrate of display device as claimed in claim 17 is characterized in that, has prepared defective by in fracture scan line and the storage capacitor line at least one.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004158796A JP4660122B2 (en) | 2004-05-28 | 2004-05-28 | Inspection matrix for active matrix liquid crystal display devices |
| JP2004158796 | 2004-05-28 | ||
| JP2004364964 | 2004-12-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1702864A CN1702864A (en) | 2005-11-30 |
| CN100461406C true CN100461406C (en) | 2009-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100758706A Expired - Fee Related CN100461406C (en) | 2004-05-28 | 2005-05-27 | Inspection substrate for display device |
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| JP (1) | JP4660122B2 (en) |
| CN (1) | CN100461406C (en) |
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| JP5470726B2 (en) * | 2008-03-19 | 2014-04-16 | 富士電機株式会社 | Manufacturing method of MOS type semiconductor device having trench gate structure |
| JP5395640B2 (en) * | 2009-11-27 | 2014-01-22 | パナソニック株式会社 | Substrate and portable terminal device |
| CN103487961B (en) | 2013-10-22 | 2016-01-06 | 合肥京东方光电科技有限公司 | Display panel testing method |
Citations (4)
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| JPH11145237A (en) * | 1997-11-13 | 1999-05-28 | Toshiba Ave Co Ltd | Process variation determination circuit and process variation determination system |
| JP2002350802A (en) * | 2001-05-25 | 2002-12-04 | Matsushita Electric Ind Co Ltd | Liquid crystal display device and its manufacturing method |
| CN1438521A (en) * | 2002-02-12 | 2003-08-27 | 精工爱普生株式会社 | Photoelectric device, electronic apparatus and method for making photoelectric apparatus |
| CN1527046A (en) * | 2003-03-07 | 2004-09-08 | 友达光电股份有限公司 | Method and device for testing liquid crystal display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10339887A (en) * | 1997-06-09 | 1998-12-22 | Hitachi Ltd | Active matrix type liquid crystal display device |
| JPH11167123A (en) * | 1997-09-30 | 1999-06-22 | Sanyo Electric Co Ltd | Display device |
| JP2001053282A (en) * | 1999-08-11 | 2001-02-23 | Matsushita Electric Ind Co Ltd | Thin-film transistor array substrate and method of testing the same |
| JP2001264719A (en) * | 2000-03-15 | 2001-09-26 | Toshiba Corp | Insulated substrate device for liquid crystal display |
-
2004
- 2004-05-28 JP JP2004158796A patent/JP4660122B2/en not_active Expired - Fee Related
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2005
- 2005-05-27 CN CNB2005100758706A patent/CN100461406C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11145237A (en) * | 1997-11-13 | 1999-05-28 | Toshiba Ave Co Ltd | Process variation determination circuit and process variation determination system |
| JP2002350802A (en) * | 2001-05-25 | 2002-12-04 | Matsushita Electric Ind Co Ltd | Liquid crystal display device and its manufacturing method |
| CN1438521A (en) * | 2002-02-12 | 2003-08-27 | 精工爱普生株式会社 | Photoelectric device, electronic apparatus and method for making photoelectric apparatus |
| CN1527046A (en) * | 2003-03-07 | 2004-09-08 | 友达光电股份有限公司 | Method and device for testing liquid crystal display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4660122B2 (en) | 2011-03-30 |
| JP2005338540A (en) | 2005-12-08 |
| CN1702864A (en) | 2005-11-30 |
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