CN100459124C - Multi-chip packaging structure - Google Patents

Abstract

A multi-chip packaging structure comprises a loader, a first chip, a plurality of bumps, a second chip, a plurality of first bonding wires, a packaging unit, a spacer, a plurality of second bonding wires and a packaging colloid. The first chip has an active surface and a back surface, and the bump is disposed between the active surface of the first chip and the carrier, wherein the first chip is electrically connected to the carrier through the bump. The second chip is configured on the back surface of the first chip, and the first bonding wire is connected with the second chip and the loader. The packaging unit is arranged above the spacer and the second chip, the spacer is arranged on the first chip, and the second bonding wire is connected with the packaging unit and the loader. The packaging colloid is configured on the loader to cover the first chip, the second chip, partial area of the packaging unit, the convex block, the spacer, the first welding wire and the second welding wire.

Description

Multi-chip package structure

technical field

The invention relates to a chip package structure, in particular to a multi-chip package structure (multi-chip package structure).

Background technique

In the semiconductor industry, the production of a chip packaging unit is mainly divided into two stages, namely, a chip manufacturing stage and a chip packaging stage. In the chip manufacturing stage, chips with specific functions are mainly formed through steps such as wafer manufacturing, circuit design, patterned circuit manufacturing, and chip dicing. In the chip packaging stage, firstly, the chip is electrically connected to the packaging substrate, and then the chip is covered with packaging glue to obtain a chip packaging unit. The purpose of chip packaging is to prevent the chip from being affected by moisture and heat, and to provide a medium for electrical connection between the chip and an external circuit, where the external circuit is, for example, a printed circuit board (PCB) or other packaging substrates.

General electronic components, such as memory, sensors and other components, are mostly composed of multiple chips with different or the same functions, and these packages containing multiple chips are mostly stacked chip packaging structures or other types Multi-chip package structure.

FIG. 1 is a schematic cross-sectional view of a known multi-chip package structure of US Pat. No. 6,838,761. Please refer to FIG. 1, the known multi-chip packaging structure 10 includes a first packaging unit 100, a second packaging unit 200, a plurality of bonding wires 218 and a packaging compound 207, wherein the second packaging unit 200 is configured in the first package unit 100 , and the bonding wire 218 is connected between the second packaging unit 200 and the first packaging unit 100 . The encapsulant 207 is disposed on the first encapsulation unit 100 to cover the second encapsulation unit 200 and the bonding wire 218 .

In more detail, the first packaging unit 100 is a known Ball Grid Array package (BGA package). In addition, the first packaging unit 100 includes a packaging substrate 112 , a chip 114 , a plurality of bonding wires 116 , a packaging compound 117 and a plurality of solder balls 118 . Wherein, the packaging substrate 112 has metal layers 121 , 123 and a conductive hole 122 , and the metal layers 121 and 123 are electrically connected to each other through the conductive hole 122 . In addition, the chip 114 is adhered on the packaging substrate 112 by an adhesive layer 113 , and the bonding wire 116 is connected between the chip 114 and the packaging substrate 112 . The packaging compound 117 is disposed on the packaging substrate 112 to cover the chip 114 and the bonding wire 116 . In addition, the solder balls 118 are disposed on the metal layer 123 of the packaging substrate 112 , and the solder balls 118 are electrically connected to the chip 114 through the packaging substrate 112 and the bonding wires 116 .

The second package unit 200 is a known pad grid array package (land grid array package, LGA package), and the second package unit 200 includes a package substrate 212, a chip 214, a plurality of bonding wires 216 and an encapsulant 217 . Wherein, the packaging substrate 212 has metal layers 221 , 223 and a conductive hole 222 , and the metal layers 221 and 223 are electrically connected to each other through the conductive hole 222 . In addition, the chip 214 is adhered on the packaging substrate 212 by an adhesive layer 213 , and the bonding wire 216 is connected between the chip 214 and the packaging substrate 212 . The encapsulant 217 is disposed on the encapsulation substrate 212 to cover the chip 214 and the bonding wire 216 .

Both the first packaging unit 100 and the second packaging unit 200 use a certain number of bonding wires to form electrical connections, but it takes a certain amount of time to form these bonding wires.

Contents of the invention

The purpose of the present invention is to provide a multi-chip packaging structure to reduce the number of bonding wires used.

Based on the above purpose or other purposes, the present invention proposes a multi-chip packaging structure, which includes a first carrier, a first chip, a plurality of first bumps, a second chip, a plurality of first bonding wires, a The packaging unit, a spacer, a plurality of second bonding wires and a first packaging compound. Wherein, the first chip has an active surface and a back surface, and the first bump is disposed between the active surface of the first chip and the first carrier, wherein the first chip is electrically connected to the first carrier through the first bump. connect. The second chip is configured on the back side of the first chip, and the first bonding wire connects the second chip and the first carrier. The packaging unit is arranged on the spacer and the second chip, and the spacer is arranged on the first chip, and the second bonding wire connects the packaging unit and the first carrier. The first encapsulant is disposed on the first carrier to cover the first chip, the second chip, a partial area of the packaging unit, the first bump, the spacer, the first bonding wire and the second bonding wire.

According to an embodiment of the present invention, the packaging unit may include a second carrier, a third chip, a plurality of third bonding wires, and a second encapsulant, wherein the third chip is disposed on the second carrier, and the third The bonding wire is connected between the second carrier and the third chip. The second encapsulant is disposed on the second carrier to cover the third chip and the third bonding wire.

According to an embodiment of the present invention, the packaging unit may include a second carrier, a third chip, a plurality of second bumps, and a second encapsulant, wherein the third chip is disposed on the second carrier, and the second The bump is disposed between the third chip and the second carrier. In addition, the third chip is electrically connected to the second carrier through the second bump. The second encapsulant is disposed on the second carrier to cover the third chip and the second bump.

According to an embodiment of the present invention, the first encapsulant exposes a partial area of the encapsulation unit.

According to an embodiment of the present invention, the spacer may be an insulating thick film or a dummy chip.

According to an embodiment of the present invention, the multi-chip packaging structure further includes a third encapsulant covering the second chip, the first bonding wire, a partial area of the first chip, and a partial area of the first carrier.

According to an embodiment of the present invention, the first carrier has a first surface and a second surface, and the first chip, the second chip and the packaging unit are disposed on the first surface of the first carrier. In addition, the multi-chip packaging structure further includes a plurality of solder balls disposed on the second surface of the first carrier, wherein the solder balls are electrically connected to the first chip, the second chip and the packaging unit through the first carrier.

Based on the above, the present invention adopts flip-chip packaging technology and wire bonding technology simultaneously to form a multi-chip packaging structure, so the present invention can reduce the usage of bonding wires.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

1 is a schematic cross-sectional view of a multi-chip packaging structure of US Patent No. 6,838,761;

2 is a schematic cross-sectional view of a multi-chip packaging structure according to a first embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of a multi-chip packaging structure according to a second embodiment of the present invention.

Among them, reference signs

10: Known multi-chip packaging structure 100: The first packaging unit

112, 212: Package substrate 113, 213: Adhesive layer

114, 214: chip 116, 216: welding wire

117, 214: Encapsulation colloid 118, 2190: Solder balls

121, 123, 221, 223: metal layer 122, 222: conductive hole

200: Second package unit 218: Bonding wire

207: Packaging colloid 20, 30: Multi-chip packaging structure

2110: First carrier 2110a: First surface

2110b: second surface 2120: first chip

2120a: Active Surface 2120b: Backside

2130: The first bump 2140: The second chip

2150: The first welding line 2160: The second welding line

2170: First Encapsulation Colloid 2180: Spacer

2200, 3200: packaging unit 2210, 3210: second carrier

2220, 3220: The third chip 2230: The third bonding wire

2240, 3240: the second encapsulation colloid 3110: the third encapsulation colloid

3230: second bump

Detailed ways

first embodiment

FIG. 2 is a schematic cross-sectional view of a multi-chip packaging structure according to a first embodiment of the present invention. Please refer to FIG. 2, the multi-chip packaging structure 20 of this embodiment includes a first carrier 2110, a first chip 2120, a plurality of first bumps 2130, a second chip 2140, a plurality of first bonding wires 2150, A packaging unit 2200 , a plurality of second bonding wires 2160 and a first packaging compound 2170 . Wherein, the first carrier 2110 has a first surface 2110 a and a second surface 2110 b, and the first chip 2120 , the second chip 2140 and the packaging unit 2200 are disposed on the first surface 2110 a of the first carrier 2110 . In addition, in this embodiment, the first carrier 2110 is a packaging substrate, however, the first carrier 2110 may also be a lead frame or other types of carriers.

The first chip 2120 has an active surface 2120a and a back surface 2120b, and the first bump 2130 is disposed between the active surface 2120a of the first chip 2120 and the first carrier 2110, wherein the first chip 2120 passes through the first bump 2130 It is electrically connected with the first carrier 2110 . That is, the first chip 2120 is electrically connected to the first carrier 2110 in a flip chip package (flip chip) manner. In addition, the second chip 2140 is disposed on the back surface 2120 b of the first chip 2120 , and the first bonding wire 2150 connects the second chip 2140 and the first carrier 2110 .

The package unit 2200 is disposed above the first chip 2120 , and the second bonding wire 2160 is connected between the package unit 2200 and the first carrier 2110 . In addition, the first encapsulant 2170 is disposed on the first carrier 2110 to cover the first chip 2120 , the second chip 2140 , part of the package unit 2200 , the first bump 2130 , the first bonding wire 2150 and the second Weld wire 2160. In this embodiment, the first encapsulant 2170 completely covers the encapsulation unit 2200 , however, the first encapsulant 2170 may also expose part of the encapsulation unit 2200 . In addition, an underfill can also be disposed between the first chip 2120 and the first carrier 2110 , and the first encapsulant 2170 also covers the underfill.

Based on the above, the package unit 2200 may be a wire-bonded package, a flip-chip package or other types of packages. In this embodiment, the packaging unit 2200 is a wire bonding package, and the packaging unit 2200 includes a second carrier 2210, a third chip 2220, a plurality of third bonding wires 2230 and a second packaging compound 2240, wherein the first The second carrier 2210 may be a package substrate, a lead frame or other types of carriers. In addition, the third chip 2220 is disposed on the second carrier 2210 , and the third bonding wire 2230 is connected between the second carrier 2210 and the third chip 2220 . In addition, the second encapsulant 2240 is disposed on the second carrier 2210 to cover the third chip 2220 and the third bonding wire 2230 .

It is worth noting that, in order to prevent the packaging unit 2200 from pressing on the first bonding wires 2150, the multi-chip packaging structure 20 further includes a spacer 2180, which is disposed between the packaging unit 2200 and the first chip 2120, and the spacer 2180 can be It is an insulating thick film or a quasi-chip, wherein the material of the insulating thick film can be epoxy resin or other insulating materials. In addition, an adhesive layer may also be disposed between the spacer 2180 and the first chip 2120 and between the spacer 2180 and the packaging unit 2200 to fix the packaging unit 2200 .

In order to enable the first carrier 2110 to be electrically connected to the outside world (such as a circuit board), the multi-chip package structure 20 further includes a plurality of solder balls 2190 disposed on the second surface 2110b of the first carrier 2110, wherein the solder balls The ball 2190 is electrically connected to the first chip 2120 , the second chip 2140 and the packaging unit 2200 through the first carrier 2110 . However, the solder balls 2190 can also be changed into pins or other types of electrical contacts. Compared with the prior art, the invention can accommodate more chips and reduce the number of required bonding wires. That is, the present invention can shorten the time required to form the bonding wire and increase the number of electrical contacts.

second embodiment

FIG. 3 is a schematic cross-sectional view of a multi-chip packaging structure according to a second embodiment of the present invention. Please refer to FIG. 2 , this embodiment is similar to the above-mentioned embodiment, the difference is that: the multi-chip packaging structure 30 of this embodiment also includes a third packaging compound 3110, which covers the second chip 2140, the first bonding wire 2150 , a partial area of the first chip 2120 and a partial area of the first carrier 2110 . That is, the third encapsulant 3110 is used to protect the first bonding wires 2150 . In addition, the packaging unit 2200 of the above-mentioned embodiment is a wire-bonded package, while the packaging unit 3200 of this embodiment is a flip-chip package.

In more detail, the package unit 3200 includes a second carrier 3210, a third chip 3220, a plurality of second bumps 3230 and a second encapsulant 3240, wherein the second carrier 3210 can be a package substrate or a wire rack, and the third chip 3220 is disposed on the second carrier 3210 . In addition, the second bump 3230 is disposed between the third chip 3220 and the second carrier 3210 , and the third chip 3220 is electrically connected to the second carrier 3210 through the second bump 3230 . In addition, the second encapsulant 3240 is disposed on the second carrier 3210 to cover the third chip 3220 and the second bump 3230 .

However, a primer can also be disposed between the second carrier 3210 and the third chip 3220 to cover the second bump 3230 , and the primer and the second encapsulant 3240 can be disposed simultaneously or separately. In addition, an adhesive layer may also be disposed between the second encapsulant 3240 and the third encapsulant 3110 to fix the encapsulation unit 3200 . In addition, in order to enable the packaging unit 3200 to be stably disposed on the first carrier 2110 , a plurality of second chips 2140 and third encapsulants 3110 may also be disposed on the first chip 2120 . Furthermore, in this embodiment, the first encapsulant 2170 completely covers the encapsulation unit 3200 , however, the first encapsulant 2170 may also expose a part of the encapsulation unit 3200 .

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (8)

1, a kind of multichip packaging structure is characterized in that, comprising:

One first carrier;

One first chip has an active surface and a back side;

A plurality of first projections are disposed between the described active surface and described first carrier of described first chip, and wherein said first chip electrically connects by described a plurality of first projections and described first carrier;

One second chip is disposed on the described back side of described first chip;

Many first bonding wires connect described second chip and described first carrier;

One sept is disposed on described first chip;

One encapsulation unit is disposed at described sept and described second chip top;

Many second bonding wires connect described encapsulation unit and described first carrier; And

One first packing colloid, be disposed on described first carrier, with the subregion that coats described first chip, described second chip, described encapsulation unit, described a plurality of first projections, described sept, described many first bonding wires and described many second bonding wires.

2, multichip packaging structure according to claim 1 is characterized in that, described encapsulation unit further comprises:

One second carrier;

One the 3rd chip is disposed on described second carrier;

Many articles the 3rd bonding wires are connected between described second carrier and described the 3rd chip; And

One second packing colloid is disposed on described second carrier, to coat described the 3rd chip and described many articles the 3rd bonding wires.

3, multichip packaging structure according to claim 1 is characterized in that, described encapsulation unit further comprises:

One second carrier;

One the 3rd chip is disposed on described second carrier;

A plurality of second projections are disposed between described the 3rd chip and described second carrier, and wherein said the 3rd chip electrically connects by described a plurality of second projections and described second carrier; And

One second packing colloid is disposed on described second carrier, to coat described the 3rd chip and described a plurality of second projection.

4, multichip packaging structure according to claim 1 is characterized in that, described first packing colloid exposes the subregion of described encapsulation unit.

5, multichip packaging structure according to claim 1 is characterized in that, described sept comprises insulative thick film or intends chip.

6, multichip packaging structure according to claim 1, it is characterized in that, also comprise one the 3rd packing colloid, in order to coat described second chip, described many first bonding wires, the subregion of described first chip and the subregion of described first carrier.

7, multichip packaging structure according to claim 1, it is characterized in that, described first carrier has a first surface and a second surface, and described first chip, described second chip and described encapsulation unit are disposed on the described first surface of described first carrier.

8, multichip packaging structure according to claim 7, it is characterized in that, also comprise a plurality of soldered balls, be disposed on the described second surface of described first carrier, wherein said a plurality of soldered balls electrically connect by described first carrier and described first chip, described second chip and described encapsulation unit.

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