CN100458616C - Multi-channel serial analog serial-to-parallel processing equipment and method thereof - Google Patents
Multi-channel serial analog serial-to-parallel processing equipment and method thereof Download PDFInfo
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- CN100458616C CN100458616C CNB2007101325829A CN200710132582A CN100458616C CN 100458616 C CN100458616 C CN 100458616C CN B2007101325829 A CNB2007101325829 A CN B2007101325829A CN 200710132582 A CN200710132582 A CN 200710132582A CN 100458616 C CN100458616 C CN 100458616C
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Abstract
The invention relates to a multi-channel serial analog series-parallel processing device and a method thereof, which processes the multi-channel serial analog processing data into a synchronization and parallel digital signal through field programmable gate array components for a main CPU use, and is capable of greatly decreasing the load of the main CPU and improving the efficiency and reliability of the system when being used in various power automation equipment. The device comprises an analog input/ low pass filter (1), a multi-channel switch (2), an operational amplifier (3), an analog conditioning circuit (4), a series A/D converter (5) and a field programmable gate array (6). The field programmable gate array (6) is applied to control the multi-channel switch (2) and the series A/D converter (5) to obtain all the conversion data of the channels to be collected and converses into the parallel data read by the main CPU. The whole circuit of the invention is of compact, lower cost, lower power consumption, etc.
Description
Technical field
The present invention be a kind of analog quantity deal with data with multi-channel serial by FPGA be processed into synchronously, parallel digital signal, use for host CPU, be used for various power automatic devices, can greatly reduce the load of host CPU, improve system effectiveness and reliability.Belong to the technical field that power automatic device is made.
Background technology
In electric system, various protection measure and control device and aut.eq. based on electric parameters all need the analog quantitys such as electric current and voltage at scene are gathered, handled, and are used as measuring the criterion that shows, protects outlet.In all Processing tasks of protection measure and control device and aut.eq., it all is the highest that workload that analog quantity is handled and real-time require, and is the condition precedent that realizes other functions.On the other hand; because the treatment of simulated amount need consume a large amount of resource of host CPU, take most break period; host CPU also must be handled other tasks such as protection, communication, demonstration in addition; make the load of host CPU reach almost saturated degree, be unfavorable for the quick, sensitive of device reliability of operation and protection outlet.
Though use multi-channel synchronous sample conversion AD chip can solve above-mentioned technological difficulties,, use the tupe of present technique invention to solve owing to be subjected to the restriction of cost, device volume etc.
Summary of the invention
Technical matters: string and the treating apparatus and the method for minimum, the satisfactory multi-channel serial analog quantity of performance index that the purpose of this invention is to provide a kind of low cost, occupies minimum space, the host CPU load is fallen.
Technical scheme: in order to realize above purpose, the present invention adopts cost cheap relatively, the pattern of single channel serial AD device+multi-channel analog switch that precision, speed, degree of stability, processing power (as figure place) are superior fully realizes, is aided with that FPGA (FPGA) is controlled, Data Format Transform, prestores, notifies and read etc.Host CPU is read the multi-analog data that all have converted with the disposable concentrated receipts of parallel mode after only need receiving and reading signal, alleviates the burden of host CPU greatly, improves device performance, reduces the plant failure rate.
The serial/parallel treating apparatus of multi-channel serial analog quantity of the present invention comprises: analog quantity input/low-pass filter, multicircuit switch, operational amplifier, analog quantity modulate circuit, serial A/D converter, field programmable gate array; Wherein, analog quantity input/low-pass filter, multicircuit switch, operational amplifier, analog quantity modulate circuit, serial A/D converter, field programmable gate array are connected in series in proper order, the input end of the channel selecting signal of the output termination multicircuit switch of the channel selecting signal of field programmable gate array, the input end of the conversion/reading order of the output terminated serial A/D converter of the conversion/reading order of field programmable gate array; The input end of analog quantity input/low-pass filter is the input end of this device, connects six input signals " AIN1 " to " AIN6 "; The output terminal of field programmable gate array " INTO " is the output terminal of this device, and the passing through of field programmable gate array is connected with outside host CPU with the data line of host CPU swap data.
Its disposal route is: by field programmable gate array control multicircuit switch and serial A/D converter, obtain the translation data of all passages to be collected and convert the parallel data that host CPU reads to, concrete grammar is:
1.) field programmable gate array reception host CPU is that cue starts mould/number conversion with " conversion starting signal ", when field programmable gate array detects " conversion starting signal " rising edge, control the coding input end and the Enable Pin of the multi-way switch circuit " ADG506A " of multicircuit switch with " A0; A1; A2; A3; EN " five ends, control gating corresponding analog quantity applies serial mould/number conversion circuit " AD7687 " of sending into after biasing and the range conditioning in the serial A/D converter by second operational amplifier " OPA132 " in the operational amplifier and the 3rd operational amplifier " OPA353 ";
2.) field programmable gate array is by " CNV " end of control serial mould/number conversion circuit " AD7687 ", when controlling it when uprising, " CNV " carry out analog to digital conversion, when " CNV " step-down, control its data output, field programmable gate array provides " SCK " end that clock signal inserts serial mould/number conversion circuit " AD7687 " behind serial mould/number conversion circuit " AD7687 " EOC, and receives the serial data of its output from " SDO " termination of serial mould/number conversion circuit " AD7687 ";
3. after) complete 16bit Data Receiving was finished, field programmable gate array (6) is inner to be organized into parallel 16 bit data with it, prestores to buffer zone; Field programmable gate array (6) forbids that enable " EN " of multi-way switch circuit " ADG506A " holds, and provide the corresponding encoded of next road analog quantity channel by " A0-A3 " end, enable " EN " end of multi-way switch circuit " ADG506A " then, make selected analog quantity enter the serial A/D converter and change by multicircuit switch;
4.) field programmable gate array repeats these processes and converts until all analog quantitys, then output terminal " int0 " end is dragged down with the notice host CPU and read ready data, read end back field programmable gate array and be in idle condition, the wait host CPU is initiated the arrival of next apotype/number conversion order.
Beneficial effect: entire circuit of the present invention has following characteristics:
A) compactness.Because use single channel serial AD device, volume own is little, only wants a slice in addition, institute takes up space and reduces greatly, can reduce the PCB layout difficulty, improve interference free performance.
B) low cost.Because use serial technology, technical indicator meets product demand fully, but cost can reduce the market competition advantage of raising product greatly.
C) low-power consumption.The power consumption of serial AD has only about 3% of parallel AD under condition on year-on-year basis, and low-power consumption brings low temperature rise, thereby the temperature that reduces AD is floated influence.
Description of drawings
Fig. 1 is a schematic block circuit diagram of the present invention.Wherein have: analog quantity input/low-pass filter 1, multicircuit switch 2, operational amplifier 3, analog quantity modulate circuit 4, serial A/D converter 5, field programmable gate array 6.
Fig. 2 is circuit theory diagrams of the present invention.
Fig. 3 is a control flow chart of the present invention.
Embodiment
The serial/parallel treating apparatus of multi-channel serial analog quantity of the present invention comprises analog quantity input/low-pass filter 1, multicircuit switch 2, operational amplifier 3, analog quantity modulate circuit 4, serial A/D converter 5, field programmable gate array 6; Wherein, analog quantity input/low-pass filter 1, multicircuit switch 2, operational amplifier 3, analog quantity modulate circuit 4, serial A/D converter 5, field programmable gate array 6 orders are connected in series, the input end of the channel selecting signal of the output termination multicircuit switch 2 of the channel selecting signal of field programmable gate array 6, the input end of the conversion/reading order of the output terminated serial A/D converter 5 of the conversion/reading order of field programmable gate array 6; The input end of analog quantity input/low-pass filter 1 is the input end of this device, connects six input signals " AIN1 " to " AIN6 "; The output terminal of field programmable gate array 6 " INTO " is the output terminal of this device, and the passing through of field programmable gate array 6 is connected with outside host CPU with the data line of host CPU swap data.
At first the analog quantitys such as electric current and voltage that the outside is imported are through 2 rank RC low-pass filtering loop filtering high order clutters, be connected to 16 then and select 1 multicircuit switch 2, multicircuit switch 2 at the scene under the control of programmable gate array FPGA successively gating each road wherein export the amplifier device of back level to, the amplifier device is connected into the mode of emitter following, its output signal is nursed one's health into the light current voltage signal of 0-2.5V through two amplifier chips and a slice high-precision voltage reference source, this signal is sent into the digital signal that A/D converter spare converts 16 to, and the wait FPGA reads and starts next time and changes after converting.The field programmable gate array collection is notified the host CPU reading of data with a cue after finishing 16 tunnel all analog quantitys.
The disposal route of the serial/parallel treating apparatus of multi-channel serial analog quantity is: by field programmable gate array 6 control multicircuit switch 2 and serial A/D converters 5, obtain the translation data of all passages to be collected and convert the parallel data that host CPU reads to, concrete grammar is:
1.) field programmable gate array 6 reception host CPUs are that cue starts mould/number conversion with " conversion starting signal ", when field programmable gate array 6 detects " conversion starting signal " rising edge, control the coding input end and the Enable Pin of the multi-way switch circuit " ADG506A " of multicircuit switch 2 with " A0-A3; EN " end, control gating corresponding analog quantity applies serial mould/number conversion circuit " AD7687 " of sending into after biasing and the range conditioning in the serial A/D converter 5 by second operational amplifier " OPA132 " in the operational amplifier 3 and the 3rd operational amplifier " OPA353 ";
2.) field programmable gate array (6) is by " CNV " end of control serial mould/number conversion circuit " AD7687 ", when controlling it when uprising, " CNV " carry out analog to digital conversion, when " CNV " step-down, control its data output, field programmable gate array 6 provides " SCK " end that clock signal inserts serial mould/number conversion circuit " AD7687 " behind serial mould/number conversion circuit " AD7687 " EOC, and receives the serial data of its output from " SDO " termination of serial mould/number conversion circuit " AD7687 ";
3. after) complete 16bit Data Receiving was finished, field programmable gate array 6 inside were organized into parallel 16 bit data with it, prestore to buffer zone; Field programmable gate array 6 forbids that enable " EN " of multi-way switch circuit " ADG506A " holds, and provide the corresponding encoded of next road analog quantity channel by " A0, A1, A2, A3 " four ends, enable " EN " end of multi-way switch circuit " ADG506A " then, make selected analog quantity enter serial A/D converter 5 and change by multicircuit switch 2;
4.) field programmable gate array 6 these processes of repetition convert until all analog quantitys, then output terminal " int0 " end is dragged down with the notice host CPU and read ready data, read end back field programmable gate array 6 and be in idle condition, the wait host CPU is initiated the arrival of next apotype/number conversion order.
Fig. 1, Fig. 2 are respectively schematic block circuit diagram of the present invention and schematic diagram.Analog signalses such as current/voltage with the outside need collection carry out 2 rank low-pass filtering earlier, insert at a high speed, Low ESR, CMOS multi-channel analog switch, be connected into the operational amplifier input end of emitter following mode behind the gating, with two amplifiers this signal is added direct current biasing afterwards, sending into the AD chip after its input that meets the AD device is required changes, digital stream after the conversion is read among the BUF of FPGA under the control of FPGA, and the parallel data that converts 16bit to is temporary, read finish after FPGA control the conversion of next road, so repeatedly, convert until all passages, the notice host CPU reads ready data.
Fig. 2 is a control flow chart of the present invention.At first send the enabling signal of gathering each road next point data of analog quantity by the device host CPU, promptly, ad_start (conversion starting signal) signal is dragged down (CPU draws high it again after a period of time), after FPGA detects this signal negative edge, driving A0-A3 earlier is passage respective value to be selected, then the EN signal is changed to high level, subsequently the pipe leg 6 " CNV " of serial mould/number conversion circuit " AD7687 " is drawn high, make serial mould/number conversion circuit " AD7687 " begin conversion, time-delay serial mould/number conversion circuit " AD7687 " is after required switching time, FPGA drags down the CNV signal, export the square-wave signal of certain frequency simultaneously at the pipe leg 8 " SCK " of serial mould/number conversion circuit " AD7687 ", at this moment serial mould/number conversion circuit " AD7687 " will be managed the effective information of leg 7 " SDO " after the rising edge output conversion of SCK by it, and FPGA converts 16 bit parallel data storing to after receiving complete 16bit data.Next paths of gating repeats said process successively then.After finishing, read in all passages the parallel data of all passages with int0 signalisation host CPU, and ready next time conversion and control.
Below be the model of each used device of present technique:
| The device label | The function title | The device model |
| U7 | Voltage-reference | ADR02BR |
| U6 | A/D converter | AD7687 |
| U5 | The 3rd operational amplifier | OPA353 |
| U4 | Second operational amplifier | OPA132 |
| U3 | First operational amplifier | OP07C |
| U2B | Field programmable gate array (FPGA) | LFXP6-3C-144T |
| U1 | Multi-way switch | ADG506A |
| R1、R2、R5、R6 | Resistance | CR0603-1/8W-4.7K |
| R3、R4 | Resistance | CR0603-1/8W-510 |
| R7-R10 | Resistance | CR0603-1/8W-1K |
| C1-C4 | Electric capacity | X7R-63V-0603-10pF |
Claims (2)
1. the string of a multi-channel serial analog quantity and treating apparatus is characterized in that this device comprises analog quantity input/low-pass filter (1), multicircuit switch (2), operational amplifier (3), analog quantity modulate circuit (4), serial A/D converter (5), field programmable gate array (6); Wherein, analog quantity input/low-pass filter (1), multicircuit switch (2), operational amplifier (3), analog quantity modulate circuit (4), serial A/D converter (5), field programmable gate array (6) order are connected in series, the input end of the channel selecting signal of the output termination multicircuit switch (2) of the channel selecting signal of field programmable gate array (6), the input end of the conversion/reading order of the output terminated serial A/D converter (5) of the conversion/reading order of field programmable gate array (6); The input end of analog quantity input/low-pass filter (1) is the input end of this device, connects six input signals " AIN1 " to " AIN6 "; The output terminal " INTO " of field programmable gate array (6) is the output terminal of this device, and the passing through of field programmable gate array (6) is connected with outside host CPU with the data line of host CPU swap data.
2. use the string of multi-channel serial analog quantity according to claim 1 and the string and the disposal route for the treatment of apparatus for one kind, it is characterized in that: by field programmable gate array (6) control multicircuit switch (2) and serial A/D converter (5), obtain the translation data of all passages to be collected and convert the parallel data that host CPU reads to, concrete grammar is:
1.) field programmable gate array (6) reception host CPU is that cue starts mould/number conversion with " conversion starting signal ", when field programmable gate array (6) detects " conversion starting signal " rising edge, control the coding input end and the Enable Pin of the multi-way switch circuit " ADG506A " of multicircuit switches (2) with " A0; A1; A2; A3; EN " five ends, control gating corresponding analog quantity applies serial mould/number conversion circuit " AD7687 " of sending into after biasing and the range conditioning in the serial A/D converter (5) by second operational amplifier " OPA132 " in the operational amplifier (3) and the 3rd operational amplifier " OPA353 ";
2.) field programmable gate array (6) is by " CNV " end of control serial mould/number conversion circuit " AD7687 ", when controlling it when uprising, " CNV " carry out analog to digital conversion, when " CNV " step-down, control its data output, field programmable gate array (6) provides " SCK " end that clock signal inserts serial mould/number conversion circuit " AD7687 " behind serial mould/number conversion circuit " AD7687 " EOC, and receives the serial data of its output from " SDO " termination of serial mould/number conversion circuit " AD7687 ";
3. after) complete 16bit Data Receiving was finished, field programmable gate array (6) is inner to be organized into parallel 16 bit data with it, prestores to buffer zone; Field programmable gate array (6) forbids that enable " EN " of multi-way switch circuit " ADG506A " holds, and provide the corresponding encoded of next road analog quantity channel by " A0, A1, A2, A3 " four ends, enable " EN " end of multi-way switch circuit " ADG506A " then, make selected analog quantity enter serial A/D converter (5) and change by multicircuit switch (2);
4.) field programmable gate array (6) repeats these processes and converts until all analog quantitys, then output terminal " int0 " end is dragged down with the notice host CPU and read ready data, read end back field programmable gate array (6) and be in idle condition, the wait host CPU is initiated the arrival of next apotype/number conversion order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB2007101325829A CN100458616C (en) | 2007-12-17 | 2007-12-17 | Multi-channel serial analog serial-to-parallel processing equipment and method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007101325829A CN100458616C (en) | 2007-12-17 | 2007-12-17 | Multi-channel serial analog serial-to-parallel processing equipment and method thereof |
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| CN101158856A CN101158856A (en) | 2008-04-09 |
| CN100458616C true CN100458616C (en) | 2009-02-04 |
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| CN102192765B (en) * | 2010-03-10 | 2013-03-27 | 连云港杰瑞电子有限公司 | Multi-channel parallel isolation analog/digital (A/D) acquisition and processing method |
| CN101968639B (en) * | 2010-11-02 | 2012-08-22 | 上海电器科学研究院 | Analog quantity acquisition module for programmable logic controller (PLC) extension |
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| CN108233928B (en) * | 2016-12-14 | 2021-07-16 | 中国航空工业集团公司西安航空计算技术研究所 | BIT method of aviation multi-channel high-precision analog quantity acquisition system |
| CN108036872A (en) * | 2017-11-23 | 2018-05-15 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of multi-channel high-accuracy temperature acquisition method |
| CN108683415A (en) * | 2018-05-23 | 2018-10-19 | 中国电子科技集团公司第四十研究所 | A kind of frequency overlapped-resistable filter for high performance network instrument |
| CN109446578A (en) * | 2018-09-28 | 2019-03-08 | 成都大公博创信息技术有限公司 | A kind of circuit design method of analog/digital and D/A converter |
| CN111796726A (en) * | 2020-07-07 | 2020-10-20 | 中航华东光电有限公司 | Signal receiving circuit of capacitive touch screen |
| CN113311222B (en) * | 2021-05-21 | 2025-02-11 | 中国科学院微小卫星创新研究院 | A satellite analog signal acquisition system |
| CN113607288A (en) * | 2021-06-25 | 2021-11-05 | 上海航天控制技术研究所 | High-speed large-area-array infrared imaging circuit |
| CN113568347A (en) * | 2021-07-27 | 2021-10-29 | 中电科思仪科技股份有限公司 | High-speed digital logic acquisition circuit and acquisition method based on ADC |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1191420A (en) * | 1997-01-31 | 1998-08-26 | 冲电气工业株式会社 | Serial-to-parallel converter |
| CN1702992A (en) * | 2005-06-10 | 2005-11-30 | 天津大学 | Serial-parallel conversion technology and device of high-speed optical signal |
| US20070115122A1 (en) * | 2005-11-22 | 2007-05-24 | Stmicroelectronics, Inc. | Test mode circuitry for a programmable tamper detection circuit |
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2007
- 2007-12-17 CN CNB2007101325829A patent/CN100458616C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1191420A (en) * | 1997-01-31 | 1998-08-26 | 冲电气工业株式会社 | Serial-to-parallel converter |
| CN1702992A (en) * | 2005-06-10 | 2005-11-30 | 天津大学 | Serial-parallel conversion technology and device of high-speed optical signal |
| US20070115122A1 (en) * | 2005-11-22 | 2007-05-24 | Stmicroelectronics, Inc. | Test mode circuitry for a programmable tamper detection circuit |
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