CN100454899C - A network processing device and method - Google Patents

Abstract

The present invention is a network processing device and method, comprising: an interface unit and a micro-engine unit, the interface unit includes multiple channels for receiving and forwarding messages; the micro-engine unit includes multiple micro-engines; the address A mapping unit, which consists of a plurality of register segments and is used for segmented address mapping; wherein, the messages in the channel are filled into the cache of the microengine according to the address mapping of the address mapping unit segment . The message is sent to different message processing micro-engines, which solves the problem of the convenience of the message processing micro-engine forwarding software development.

Description

A network processing device and method

technical field

The present invention relates to a network processing unit (NPU: Network Process Unit), specifically a network processing device and method.

Background technique

Network Processing Unit (NPU: Network Process Unit) is a programmable or configurable semiconductor device designed and optimized for processing network data (packets). NPU optimizations include hardware and instruction sets to support high-speed packet classification and packet modification. The main function of the network processing unit is to offload the data transmission and processing tasks specific to network applications from the general-purpose processor, thereby greatly speeding up the processing and transmission of information packets. A network processing unit generally consists of a core processor (such as the Strong ARM core series) and multiple micro engines (Micro engines), which concurrently and synchronously complete the processing of a data packet. In the network processing unit, generally there are multiple micro-engines for receiving messages from multiple interfaces, and such a solution is very complicated.

As shown in FIG. 1 , the network processing unit described in the prior art generally includes the following units: a micro-engine unit, a storage unit, an interface unit and a register unit. The micro-engine unit is the core of the network processing unit, which completes packet analysis and forwarding. The micro-engine unit of the network processing unit may have multiple micro-engines for parallel processing. The storage unit is an internal storage device of the network processing unit, such as an SRAM, where messages or entries are stored. The interface unit is the external data interface of the network processing unit, and the message enters through the incoming interface and is forwarded by the outgoing interface. The register unit completes the configuration of the network processing unit.

The network processing unit in the prior art processes the message as follows: the message entered from the channel in the interface unit is first cached in the storage unit, and when it needs to be processed, the micro-engine uses specific instructions to read from the storage unit and perform deal with. Since the packets of multiple interfaces are all stored in a dedicated memory outside the microengine, complex storage management is required. Moreover, when the microengine processes the message, it needs to schedule specific instructions and need additional resources to read the content of the message for processing. This will increase the management complexity of the storage unit (because there are multiple channels), and will also increase the delay for the interface data to reach the micro-engine, thereby reducing the performance of the network processing unit.

It can be seen that in the previous network processing unit, it is difficult and complicated for multiple micro-engines to obtain the messages to be processed. Get the message in the storage space.

Contents of the invention

The purpose of the present invention is to provide a network processing device and method, so that the message can be flexibly and conveniently sent to any storage space of the network processing unit, improve the performance of the network processing unit, and also reduce the complexity of the network processing unit design Spend.

The technical solution of the present invention is: a network processing device, including: an interface unit and a micro-engine unit, the interface unit includes a plurality of channels for receiving and forwarding messages; the micro-engine unit includes a plurality of micro-engines , the device also includes:

The address mapping unit, which is composed of multiple register segments, adopts a three-segment address mapping mechanism to realize the mapping relationship between the channel and the buffer corresponding to the micro-engine or the buffer inside the micro-engine;

Wherein, the message in the channel is filled into the buffer corresponding to the microengine or the buffer inside the microengine according to the address mapping segmented by the address mapping unit.

The address mapping unit includes: a first section of mapping unit, including a plurality of registers, the number of registers is the same as the number of channels of the interface unit; a second section of mapping unit, including at least one register; a third section of mapping unit, including Two groups of registers, the number of each group of registers is the same as the number of the microengine.

The third segment mapping unit includes: an address register group, including a plurality of first registers, the number of the first registers is the same as the number of microengines of the microengine unit, and each of the first registers stores a The address of a microengine buffer in the microengine unit; the position register group, which corresponds to the address register group one-to-one, includes a plurality of second registers, each of which is stored in a microengine unit in the second register The address of another microengine buffer.

Each register of the first-segment mapping unit stores an address of a register of the second-segment mapping unit respectively.

The multiple registers of the first segment mapping unit store the address of one register of the second segment mapping unit.

The value range of the number of registers in the second segment mapping unit is: any integer value greater than or equal to 1 and less than or equal to the number of channels; each register of the second segment mapping unit stores the third segment The address of a register in the mapping unit.

The present invention also provides a network message processing method, which includes: using the channel in the interface to accept the message; making the channel map with the buffer corresponding to the micro-engine or the internal memory of the micro-engine through segment address mapping; The buffer establishes a communication connection, and fills the messages in the channel into the buffer corresponding to the micro-engine or the buffer inside the micro-engine. The corresponding buffer or the mapping relationship between the buffers inside the microengine.

The network message processing method of the present invention, its concrete steps are:

The interface unit accesses a register in the first mapping unit corresponding to one channel, and obtains the first address stored in the register;

The interface unit accesses a register of the second mapping unit corresponding to the first address, and obtains a second address stored in the register;

The interface unit accesses a register of the third mapping unit corresponding to the second address, and obtains a third address stored in the register;

The interface unit stores the packets entering the channel into the buffer corresponding to the third address.

When a buffer is filled, the second address stored in the register of the second segment mapping unit will change according to the address of the next buffer defined in the third segment mapping unit, so as to point to store the next buffer address The registers of the third-segment mapping unit.

The present invention also provides a network message processing method, which includes: a channel of the interface unit receives external messages; the interface unit searches the address mapping unit to find the address of the buffer corresponding to the channel, and the address mapping unit The three-segment address mapping mechanism is used to realize the mapping relationship between the channel and the buffer corresponding to the micro-engine or the buffer inside the micro-engine; the interface unit stores the message into the buffer corresponding to the micro-engine or the micro-engine through the bus internal buffer.

The specific steps of the network packet processing method are as follows: the interface unit searches the address mapping unit to find the address of the buffer corresponding to the channel, and the interface unit retrieves a register stored in the first mapping unit corresponding to one channel. the first address; retrieve the second address stored in a register of the second mapping unit corresponding to the first address; retrieve the third address stored in a register of the third mapping unit corresponding to the second address; interface unit Store the message entering one of the channels into the buffer corresponding to the third address.

After a buffer is filled, the second address stored in the register of the second mapping unit will be changed according to the address of the next buffer defined in the third mapping unit, so as to point to the first address storing the address of the next buffer. Three mapping unit registers.

The beneficial effect of the present invention is that: due to the adoption of the three-segment address mapping mechanism, the message entering the network processing device can flexibly reach any storage space of the network processing unit, which solves the problem of interface data management and micro-engine difficulty in the network processing unit. Obtaining pending messages and acquiring messages is a common problem with high overhead, thereby improving the performance of message forwarding and processing, and making the message processing micro-engine software easier to implement.

Description of drawings

FIG. 1 is a schematic structural diagram of a network processing unit in the prior art;

Fig. 2 is the register diagram of three-section address mapping of the present invention;

Fig. 3 is the register diagram of Embodiment 1 of three-segment address mapping of the present invention;

Fig. 4 is the register diagram of Embodiment 2 of three-segment address mapping of the present invention;

Fig. 5 is the register diagram of Embodiment 3 of three-segment address mapping of the present invention;

FIG. 6 is a schematic structural diagram of a network processing device of the present invention;

Fig. 7 is a flowchart of the network processing method of the present invention;

FIG. 8 is a flow chart of a specific embodiment of the network processing method of the present invention.

Detailed ways

The specific implementation manner of the present invention will be described below in conjunction with the accompanying drawings. The present invention is mainly applied in the hardware design of the network processing unit, and the present invention defines that the network processing unit includes the following units: micro-engine unit (or storage unit), interface unit and register unit.

The micro-engine unit is the core of the network processing unit, which completes packet analysis and forwarding. The micro-engine unit of the network processing unit may have multiple micro-engines for parallel processing.

The storage unit is an internal storage device of the network processing unit, such as an SRAM, where messages or entries are stored.

The interface unit is the external data interface of the network processing unit. Messages enter through the incoming interface and are forwarded by the outgoing interface.

The register unit completes segment address mapping of the network processing unit.

Three groups of register units are defined in the register unit, namely: the first mapping unit (MAPStage1), the second mapping unit (MAP Stage2) and the third mapping unit (MAP Stage3), as shown in Figure 2. The first mapping unit is composed of multiple registers, and the number of registers is equal to the number of channels; the second mapping unit is composed of at least one register; the third mapping unit is composed of multiple registers Composed, and the number of the registers is associated with the number of the channels; the buffer unit is composed of a plurality of buffers, and the number of the buffers is related to the number of registers in the third segment mapping unit Correspondingly, the buffer corresponds to a microengine or refers to the buffer inside the microengine.

The number of registers in the first segment of the mapping unit register group is the same as the number of channels in the interface unit, which respectively define whether the channels in the interface unit are valid. If the register value corresponding to the channel points to the valid register in the second segment of the mapping unit register group, it indicates The channel in the interface unit is valid, otherwise it indicates that the channel is invalid.

The register value in the register group of the second mapping unit points to a specific register in the register group of the third mapping unit. It is the only variable in the three-segment address mapping. Through its continuous change, the address of the third-segment mapping unit it points to is also constantly changing, that is to say, the effective channel defined in the first-segment mapping unit register group Messages can flexibly arrive at different buffers (MAP Stage3 address definition).

The third segment of the mapping unit register group is actually composed of two sets of registers corresponding to each other. A set of registers defines the memory address (buffer address), and a set of registers defines the size of the buffer and the location of the next buffer. When a buffer is filled (full), the register value corresponding to the second mapping unit register group will change the register value according to the next buffer position defined in the third mapping unit, and the second mapping unit register points to A new third-segment mapping unit register. Subsequent messages are deduced in turn.

Example 1:

Address mapping settings at each stage are shown in schematic diagram 3, and its structural schematic diagram is shown in Figure 6, wherein the network processing device 100 includes: an interface unit 101, a micro-engine unit 103, and the interface unit includes a plurality of channels for message receiving and forwarding; the microengine unit includes a plurality of microengines, characterized in that the device also includes: an address mapping unit 102, which is composed of a plurality of register segments, and is used for segmented address mapping; wherein, The messages in the channel are filled into the cache of the microengine according to the segmented address mapping of the address mapping unit. Its specific mapping relationship is:

The n channel addresses of MAP Stage1 are all set to point to MAP Stage2 address 0, which means that the n channels of the interface unit are valid, and there may be packets arriving. The 0 address of MAP Stage2 is set to point to the 0 address of MAP Stage3. Since the n channel addresses of MAP Stage1 are all set to 0, it means that all the n channels have incoming messages, and the n channels are polled in Round-Robin mode, MAP Stage1 address 0 (that is, channel 1) points to MAP Stage2 address 0, and MAP Stage2 address 0 also points to address 0 of MAP Stage3, so the message of channel 1 fills the Buffer1 address pointed to by MAP Stage3 address 0 (the MAP Stage3 address pointed to by the MAP Stage2 address). Set the step size to modify the MAP Stage2 address. If you need to fill the Buffer2 pointed by the next MAP Stage3 address, you can set the step size to 1, and the MAP Stage2 address 0 will be modified to 1 (0+1), so channel 2 (MAP Stage1 channel polling) when the message arrives (MAP Stage1 address setting channel 2 also points to MAP Stage2 address 0), then according to the value of MAP Stage2 address 0 (=1), get MAP Stage3 address 1 (MAP Stage2 The address points to Buffer2 in the MAP Stage3 address) to fill Buffer2, and then the MAP Stage2 address becomes 2 (1+1), and so on until the last buffer, and the MAP Stage2 address changes back to 0, thus completing A loop, such an infinite loop, the messages of each channel are flexibly distributed to any Buffer (SRAM or message processing micro-engine, etc.).

As shown in Figure 7, it is the workflow of the network message processing method of the present invention, wherein: adopt the passage in the interface to accept the entry of the message; make the passage establish a communication connection with the cache memory of the micro-engine through segment address mapping, And fill the messages in the channel into the cache of the microengine.

The specific workflow of the network message processing method of the present invention is (as shown in Figure 8): the mapping relationship shown in Figure 3, the interface unit of the network processing device accesses one of the first mapping units corresponding to its channel 1 Register, that is: and obtain the first address 0 stored in the register; the interface unit accesses a register of the second mapping unit corresponding to the first address, and obtain the second address 0 stored in the register; The interface unit accesses a register of the third segment mapping unit corresponding to the second address, and obtains the third address (i.e. the address of Buffer1) stored in the register; thus the interface unit will enter its described The message of the channel is stored in the buffer Buffer1 corresponding to the third address.

After Buffer1 is full, the MAP Stage2 address can be modified according to the step size set by the second set of registers of MAP Stage3. If the Buffer2 pointed to by the next MAP Stage3 address needs to be filled, the step size can be set to 1, and the MAP Stage2 address 0 will be It is modified to 1 (0+1), so when the message of channel 2 (the polling of MAP Stage1 channel) arrives (MAP Stage1 address setting channel 2 also points to MAP Stage2 address 0), then according to the value of MAP Stage2 address 0 ( =1), get Buffer2 in MAP Stage3 address 1 (MAP Stage2 address points to MAP Stage3 address), so as to fill Buffer2, then MAP Stage2 address becomes 2(1+1), and so on until the end One buffer, the address of MAP Stage 2 is changed back to 0, thus completing a cycle, and so on indefinitely, the messages of each channel are flexibly distributed to any Buffer (SRAM or message processing micro-engine, etc.).

Example 2:

The address mapping settings at each stage are shown in schematic diagram 4, and its structural schematic diagram is shown in Figure 6, wherein the network processing device 100 includes: an interface unit 101, a micro-engine unit 103, and the interface unit includes a plurality of channels for message receiving and forwarding; the microengine unit includes a plurality of microengines, characterized in that the device also includes: an address mapping unit 102, which is composed of a plurality of register segments, and is used for segmented address mapping; wherein, The messages in the channel are filled into the cache of the microengine according to the segmented address mapping of the address mapping unit. Its specific mapping relationship is:

The n channels of the MAP Stage1 address are all set to point to the value of the MAP Stage2 address, and the n channels of the MAP Stage1 address are all valid. The value set by channel 1 points to MAP Stage2 address 0, and the value set by MAP Stage2 address 0 points to MAP Stage3 address is also 0, and the message arriving on channel 1 will fill buffer1 in MAPStage3 address 0. Similarly, channel 2 messages will also fill buffer 2 in MAP Stage 3 address 1, and channel n messages will fill buffer n in MAP Stage 3 address n, so each channel is set to arrive at different buffers independently, In this case, the address of MAP Stage2 can be unchanged (the change step size is set to 0), the message of channel 0 always fills buffer1, and the message of channel n always fills buffer n.

As shown in Figure 7, it is the workflow of the network message processing method of the present invention, wherein: adopt the passage in the interface to accept the entry of the message; make the passage establish a communication connection with the cache memory of the micro-engine through segment address mapping, And fill the messages in the channel into the cache of the microengine. The specific workflow of the network message processing method of the present invention is: the mapping relationship shown in Figure 4, the interface unit of the network processing device accesses a register in the first section of the mapping unit corresponding to its channel 1, and obtains the register stored in the register. The first address 0 in the first address; the interface unit accesses a register of the second mapping unit corresponding to the first address, and obtains the second address 0 stored in the register; the interface unit accesses the second address corresponding to A register of the third segment mapping unit, and obtain the third address (i.e. the address of Buffer1) stored in the register; thus the interface unit will store the message entering its channel 1 into the third address The corresponding buffer Buffer1.

The interface unit accesses a register in the first segment of the mapping unit corresponding to channel 2, and obtains the first address 1 stored in the register; the interface unit accesses a register of the second segment of the mapping unit corresponding to the first address , and obtain the second address 1 stored in the register; the interface unit accesses a register of the third segment mapping unit corresponding to the second address, and obtains the third address stored in the register (that is, the address of Buffer2 ); so that the interface unit stores the message entering the channel 2 into the buffer Buffer2 corresponding to the third address.

Repeat the above steps until the interface unit accesses a register in the first segment mapping unit corresponding to its channel n, and obtains the first address n stored in the register; the interface unit accesses the second segment corresponding to the first address A register of the mapping unit, and obtain the second address n stored in the register; the interface unit accesses a register of the third segment mapping unit corresponding to the second address, and obtain the third address stored in the register (that is, the address of Buffern); so that the interface unit stores the message entering the channel n into the buffer Buffern corresponding to the third address.

Example 3:

The address mapping settings at each stage are shown in schematic diagram 5, and its structural schematic diagram is shown in Figure 6, wherein the network processing device 100 includes: an interface unit 101, a micro-engine unit 103, and the interface unit includes a plurality of channels for message receiving and forwarding; the microengine unit includes a plurality of microengines, characterized in that the device also includes: an address mapping unit 102, which is composed of a plurality of register segments, and is used for segmented address mapping; wherein, The messages in the channel are filled into the cache of the microengine according to the segmented address mapping of the address mapping unit. Its specific mapping relationship is:

The two channel addresses of MAP Stage1 are set to point to MAP Stage2 address 0, the other two channel addresses of MAP Stage1 are set to point to MAP Stage2 address 3 and address 4 respectively, and the remaining n channel addresses of MAP Stage1 are all set to point to MAP Stage2 address m. Each channel of the interface unit is valid, and there may be packets arriving. The 0 address of MAP Stage2 is set to point to the 0 address of MAP Stage3. Since the two channel addresses of MAP Stage1 are all set to 0, it means that the two channels have incoming messages, and the two channels are polled in Round-Robin mode, and the address 0 of MAP Stage1 (that is, channel 1) points to the address 0 of MAP Stage2 , MAP Stage2 address 0 also points to MAP Stage3 address 0, so the message of channel 1 fills the Buffer1 address pointed to by MAP Stage3 address 0 (the MAP Stage3 address pointed to by the MAP Stage2 address). The step size set by the second set of registers is used to modify the MAP Stage2 address. If the Buffer2 pointed to by the next MAP Stage3 address needs to be filled, the step size can be set to 1, and the MAP Stage2 address 0 will be modified to 1 (0+1). Then when the message of channel 2 (the polling of MAPStage1 channel) arrives (MAP Stage1 address setting channel 2 also points to MAPStage2 address 0), then according to the value of MAP Stage2 address 0 (=1), get MAP Stage3 address 1 (MAP Stage2 address points to Buffer2 in MAP Stage3 address), so as to fill Buffer2.

The channel of MAP Stage1 address 1 is set to point to MAP Stage2 address 3, and the channel of MAP Stage1 address is valid. MAP Stage2 address 3 sets the value pointing to MAP Stage3 address as 3, and the message arriving on this channel will fill buffer3 in MAP Stage3 address 3.

The channel of MAP Stage1 address 3 is set to point to MAP Stage2 address 4, and the channel of MAP Stage1 address is valid. MAP Stage2 address 3 sets the value pointing to MAP Stage3 address to 4, and the message arriving on this channel will fill buffer4 in MAP Stage3 address 4.

The remaining n channel addresses of MAP Stage1 are all set to point to the address m of MAP Stage2, and the m address of MAP Stage2 is set to point to the n address of MAP Stage3. Since the n channel addresses of MAP Stage1 are all set to m, it means that the n channels have packets to enter, and the n channels are polled in Round-Robin mode, MAP Stage1 address n points to MAP Stage2 address m, and MAP Stage2 address m It also points to the address n of MAP Stage3, so the message of channel n1 fills the Buffern1 address pointed to by MAP Stage3 address n (the MAP Stage3 address pointed to by the MAP Stage2 address). After filling, it can be set according to the second set of registers of MAP Stage3 Step size is used to modify the MAP Stage2 address. If the Buffern2 pointed to by the next MAP Stage3 address needs to be filled, the step size can be set to 1, and the MAP Stage2 address m will be changed to m+1, so channel n2 (of MAP Stage1 channel Polling) message arrives (MAP Stage1 address setting channel n2 also points to MAP Stage2 address m, then according to the value of MAP Stage2 address m, get Buffer2 in MAP Stage3 address n (MAP Stage2 address points to MAP Stage3 address) , so as to fill Buffer2. Then the address of MAP Stage2 becomes m+2, and so on, until the last buffer, the address of MAP Stage2 changes back to m, thus completing a cycle, and so on indefinitely, the messages of each channel It is flexibly distributed to any Buffer (SRAM or message processing microengine, etc.).

As shown in Figure 7, it is the workflow of the network message processing method of the present invention, wherein: adopt the passage in the interface to accept the entry of the message; make the passage establish a communication connection with the cache memory of the micro-engine through segment address mapping, And fill the messages in the channel into the cache of the microengine. The specific workflow of the network packet processing method of the present invention is shown in the mapping relationship shown in FIG. 5 , wherein the network packet processing method is a combination of the network packet processing methods in the above-mentioned Embodiment 1 and Embodiment 2.

The above are the three embodiments. According to the previous description, more flexible configuration methods can be formed, so that the messages of different channels can reach different addresses (micro-engine unit or storage unit), which is convenient for message processing. Microengine processing.

The beneficial effects brought by the technical solution of the present invention are as follows: the present invention solves the common problems that in the network processing unit, the interface data management is difficult and the micro-engine is difficult to obtain the message to be processed and the cost of obtaining the message is large, so that the message processing micro-engine Software is easier to implement and improves packet forwarding performance.

The above specific embodiments are only used to illustrate the present invention, but not to limit the present invention.

Claims (13)

1. A network processing device, comprising: an interface unit and a microengine unit, the interface unit comprising a plurality of channels for receiving and forwarding messages; the microengine unit comprising a plurality of microengines, characterized in that, The device also includes: The address mapping unit, which is composed of multiple register segments, adopts a three-segment address mapping mechanism to realize the mapping relationship between the channel and the buffer corresponding to the micro-engine or the buffer inside the micro-engine; Wherein, the message in the channel is filled into the buffer corresponding to the microengine or the buffer inside the microengine according to the address mapping segmented by the address mapping unit. 2. The network processing device according to claim 1, wherein the address mapping unit comprises: The first mapping unit includes a plurality of registers, and the number of registers is the same as the number of channels of the interface unit; The second mapping unit includes at least one register; The third mapping unit includes two groups of registers, and the number of registers in each group is the same as the number of the microengines. 3. The network processing device according to claim 2, wherein the third mapping unit comprises: The address register group includes a plurality of first registers, the number of the first registers is the same as the number of microengines of the microengine unit, each of the first registers stores a microengine buffer in the microengine unit address of the device; The position register group corresponds one-to-one to the address register group, and includes a plurality of second registers, and each of the second registers stores an address of another microengine buffer in the microengine unit. 4. The network processing device according to claim 2, wherein each register of the first-segment mapping unit stores an address of a register of the second-segment mapping unit. 5. The network processing device according to claim 2, wherein the address of one register of the second segment mapping unit is stored in a plurality of registers of the first segment mapping unit. 6. The network processing device according to claim 2, wherein the value range of the number of registers in the second mapping unit is: any integer value greater than or equal to 1 and less than or equal to the number of channels; Each register of the second-stage mapping unit stores an address of a register in the third-stage mapping unit. 7. The network processing device according to claim 1, wherein the address mapping unit comprises: The first segment mapping unit includes a plurality of registers, the number of registers is the same as the number of channels of the interface unit; each register of the first segment mapping unit stores the address of a register of the second segment mapping unit respectively ; The second mapping unit includes at least one register; the value range of the number of registers in the second mapping unit is: any integer value greater than or equal to 1 and less than or equal to the number of channels; the second mapping unit Each register of stores the address of a register in the third segment mapping unit; The third section mapping unit includes two groups of registers, and the number of each group of registers is the same as the number of the microengine; the third section mapping unit includes: an address register group, including a plurality of first registers, and the number of the first registers is the same as that of the microengine. The number of microengines of the microengine unit is the same, and the address of a microengine buffer in the microengine unit is stored in each of the first registers; the position register group, which corresponds to the address register group one by one, includes A plurality of second registers, each of which stores an address of another microengine buffer in the microengine unit. 8. A network message processing method, characterized in that, Use the channel in the interface to accept the incoming message; Make the channel establish a communication connection with the buffer corresponding to the microengine or the buffer inside the microengine through segment address mapping, and fill the messages in the channel into the buffer corresponding to the microengine or inside the microengine In the buffer, the segment address mapping is to use a three-segment address mapping mechanism to realize the mapping relationship between the channel and the buffer corresponding to the micro-engine or the buffer inside the micro-engine. 9. The network message processing method according to claim 8, characterized in that: The interface unit accesses a register in the first mapping unit corresponding to one channel, and obtains the first address stored in the register; The interface unit accesses a register of the second mapping unit corresponding to the first address, and obtains a second address stored in the register; The interface unit accesses a register of the third mapping unit corresponding to the second address, and obtains a third address stored in the register; The interface unit stores the packets entering the channel into the buffer corresponding to the third address. 10. The network packet processing method according to claim 9, further comprising: When a buffer is filled, the second address stored in the register of the second segment mapping unit will change according to the address of the next buffer defined in the third segment mapping unit, so as to point to store the next buffer address The registers of the third-segment mapping unit. 11. A method for processing network packets, comprising: A channel of the interface unit receives external messages; The interface unit searches the address mapping unit to find the address of the buffer corresponding to the channel, and the address mapping unit uses a three-segment address mapping mechanism to realize the mapping between the channel and the buffer corresponding to the microengine or the buffer inside the microengine relation; The interface unit stores the message into the buffer corresponding to the microengine or the buffer inside the microengine through the bus. 12. The network packet processing method according to claim 11, wherein the interface unit searches the address mapping unit to find the address of the buffer corresponding to the channel, specifically comprising: The interface unit retrieves the first address stored in a register in the first mapping unit corresponding to one channel; Retrieving a second address stored in a register of the second mapping unit corresponding to the first address; Retrieving a third address stored in a register of the third mapping unit corresponding to the second address; The interface unit stores the message entering one of its channels into the buffer corresponding to the third address. 13. The network packet processing method according to claim 12, further comprising: After a buffer is filled, the second address stored in the register of the second mapping unit will be changed according to the address of the next buffer defined in the third mapping unit, so as to point to the first address storing the address of the next buffer. Three mapping unit registers.

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