CN100452324C - A method to etch barrier layer of self-alignment refractory metal silicide - Google Patents
A method to etch barrier layer of self-alignment refractory metal silicide Download PDFInfo
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- CN100452324C CN100452324C CNB2005101101227A CN200510110122A CN100452324C CN 100452324 C CN100452324 C CN 100452324C CN B2005101101227 A CNB2005101101227 A CN B2005101101227A CN 200510110122 A CN200510110122 A CN 200510110122A CN 100452324 C CN100452324 C CN 100452324C
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- self
- barrier layer
- etching
- silicon compound
- salicide
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 230000004888 barrier function Effects 0.000 title claims abstract description 19
- 229910021332 silicide Inorganic materials 0.000 title abstract description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title abstract description 4
- 239000003870 refractory metal Substances 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 22
- 150000003377 silicon compounds Chemical class 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000004026 adhesive bonding Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000003292 glue Substances 0.000 abstract 3
- 238000009736 wetting Methods 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 238000000280 densification Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 1
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- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The disclosed etching method for self-alignment undissolved metal silicide comprises: injecting from NMOS and PMOS; growing the barrier layer; coating glue; preparing the barrier layer mask; wetting etching; dried removing glue; wetting removing the glue; diffusing the drain to anneal. This invention releases the etching effect to salicide block before HF etching, and cuts the production period greatly.
Description
Technical field
The present invention relates to the lithographic method on a kind of Salicide block (Self-Aligned Refractory silicon compound barrier layer), relate in particular to a kind of lithographic method that can effectively protect Self-Aligned Refractory silicon compound barrier layer.
Background technology
Growing along with integrated circuit technology, the polysilicon live width and between the live width spacing just becoming more and more narrow, in order to satisfy the needs of design, this just requires this tunic of Salicide block to want to accomplish as far as possible thin.But after the Salicide block attenuation, produced two kinds of negative interactions, the one, because Salicide block can produce more pin hole, thereby directly have influence on Salicide block performance; The 2nd, HF (hydrofluoric acid) the corrasion meeting before Salicide (Self-Aligned Refractory silicon compound) forms produces fatal influence to relatively thinner Salicide block, even with the whole flush awaies of Salicide block.
Fig. 1 is that etching technics and the Salicide of the present Salicide block that uses always forms preceding HF etching flow process.In this flow process,, be easy to be corrupted to very thin Self-Aligned Refractory silicide barrier layer through follow-up HF etching owing to be subjected to the influence of the Self-Aligned Refractory silicide barrier layer self character of chemical vapor deposition (CVD) method growth.
Summary of the invention
Technical problem to be solved by this invention provides the lithographic method on a kind of Self-Aligned Refractory silicon compound barrier layer, and it can effectively protect Salicide block.
In order to solve above technical problem, the invention provides the lithographic method on a kind of autoregistration silicon compound barrier layer, which comprises at least following steps: the first step, NMOS, PMOS source are leaked and are injected; Second step, the lithographic method growth on Self-Aligned Refractory silicon compound barrier layer; The 3rd step, gluing; The 4th step, the lithographic method mask light shield on Self-Aligned Refractory silicon compound barrier layer; The 5th step, etching; In the 6th step, dry method is removed photoresist; In the 7th step, wet method is removed photoresist; The 8th step, source, leakage diffusion annealing.
The 5th step, described etching was a wet etching.
Because the present invention is placed into source, this process of leakage diffusion annealing before the preceding HF processing of Salicide growth, utilize the densification of the diffusion annealing of source, leakage to the lithographic method on Self-Aligned Refractory silicon compound barrier layer, alleviated Salicide greatly and formed of the corrasion of preceding HF etching, thereby played the effect of protecting Salicide block Salicide block; In addition, be updated to more simple wet etching, shortened the production cycle of silicon chip greatly by the dry etching of former technology.
Description of drawings
Below in conjunction with the drawings and specific embodiments, the present invention is further elaborated.
Fig. 1 is that etching technics and the Salicide of existing Salicide block forms preceding HF etching schematic flow sheet;
Fig. 2 is the HF etching schematic flow sheet before Salicide block etching technics of the present invention and Salicide form;
Fig. 3 is the square resistance test result contrast schematic diagram of Salicide block on n type single crystal silicon that adopts under process of the present invention and the existing process.
Embodiment
As shown in Figure 2, it is the HF etching schematic flow sheet before SaliCide block etching technics of the present invention and silicon compound (Salicide) form, and it may further comprise the steps: the first step, and NMOS, the PMOS source is leaked and is injected; Second step, the lithographic method growth of Salicide block; The 3rd step, gluing; The 4th step, the lithographic method mask light shield of Salicide block; The 5th step, wet etching; In the 6th step, dry method is removed photoresist; In the 7th step, wet method is removed photoresist; The 8th step, source, leakage diffusion annealing.In conjunction with Fig. 1; technological process of the present invention is with the source; leak the HF processing step before before this step of diffusion annealing is placed directly into the Salicide growth; it utilizes the source; leak the densification of diffusion annealing to Salicide block; alleviated Salicide greatly and formed of the corrasion of preceding HF etching Salicide block; digital proof is through the source; the silicon dioxide of the plasma activated chemical vapour deposition of the diffusion annealing of leaking is to l: the etch rate of 100 hydrofluoric acid be without the source leak diffusion annealing plasma activated chemical vapour deposition silicon dioxide about 1/2nd; so; through the source; the Salicide block of the diffusion annealing of leaking more can stand the heart etching before the Salicide growth, thereby has played the effect of protection Salicide block.
In addition, because leak the Salicide block of diffusion annealing through the source more fine and close, pin hole still less, so for the continuous development need of the technology that satisfies integrated circuit, technology of the present invention is existing 1/2nd to 2/3rds with the reduced thickness of Salicide block.Such as a certain silica product with plasma activated chemical vapour deposition as Salicideblock, under existing state of arts, at least need the silicon dioxide of 400～500 dusts could realize the performance of Salicide block, but under the same conditions, when adopting process of the present invention, only need 200～300 dusts just can realize the performance of Salicide block.Along with the attenuate of the thickness of Salicideblock, new technology has been simplified the etching technics of Salicide block, is updated to more simple wet etching by the dry etching of former technology, has shortened the production cycle of silicon chip greatly.Its underlying cause is the attenuate with Salicideblock thickness, and the wet etching that possesses isotropic characteristics is quite little to the etch amount of Salicideblock side, can ignore substantially.
As shown in Figure 3, it is same batch a silicon chip, under the identical situation of other process conditions, adopts the square resistance test result contrast schematic diagram of Salicide block on n type single crystal silicon under process of the present invention and the existing process.Wherein, the square resistance under the existing process of curve 1 expression, curve 2 expressions are the square resistances under the process of the present invention.By curve 1,2 as seen, big or small identical with the square resistance of the Salicide block of the Salicide block of process of the present invention and existing process, but the thickness of the Salicide block of process of the present invention only is 1/2nd to 2/3rds of the Salicide block of existing process.Obviously, the HF processing that source, this process of leakage diffusion annealing are placed into before the Salicide growth can be protected Salicide block before effectively, and the etching technics of simplification Salicideblock.
Claims (3)
1, the lithographic method on a kind of Self-Aligned Refractory silicon compound barrier layer is characterized in that, which comprises at least following steps: the first step, and NMOS, PMOS source are leaked and are injected; Second step, Self-Aligned Refractory silicon compound barrier growth; The 3rd step, gluing; The 4th step, Self-Aligned Refractory silicon compound barrier layer mask version light shield; The 5th step, etching; In the 6th step, dry method is removed photoresist; In the 7th step, wet method is removed photoresist; The 8th step, source, leakage diffusion annealing.
2, the lithographic method on Self-Aligned Refractory silicon compound as claimed in claim 1 barrier layer is characterized in that, the 5th step, described etching was a wet etching.
3, the lithographic method on Self-Aligned Refractory silicon compound as claimed in claim 1 barrier layer is characterized in that, second step thickness of described Self-Aligned Refractory silicon compound barrier growth is 200～300 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101101227A CN100452324C (en) | 2005-11-08 | 2005-11-08 | A method to etch barrier layer of self-alignment refractory metal silicide |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101101227A CN100452324C (en) | 2005-11-08 | 2005-11-08 | A method to etch barrier layer of self-alignment refractory metal silicide |
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| Publication Number | Publication Date |
|---|---|
| CN1964003A CN1964003A (en) | 2007-05-16 |
| CN100452324C true CN100452324C (en) | 2009-01-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005101101227A Active CN100452324C (en) | 2005-11-08 | 2005-11-08 | A method to etch barrier layer of self-alignment refractory metal silicide |
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| CN102403190B (en) * | 2010-09-08 | 2014-04-23 | 无锡华润上华半导体有限公司 | Circular piece cleaning method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1341957A (en) * | 2000-09-04 | 2002-03-27 | 中国科学院半导体研究所 | Method for growing silicon oxide thick film by adopting TEOS source PECVD |
| US6530380B1 (en) * | 1999-11-19 | 2003-03-11 | Chartered Semiconductor Manufacturing Ltd. | Method for selective oxide etching in pre-metal deposition |
| CN1435875A (en) * | 2002-02-01 | 2003-08-13 | 旺宏电子股份有限公司 | Method for making selective local self-aligned silicide |
| CN1484285A (en) * | 2002-09-18 | 2004-03-24 | 上海宏力半导体制造有限公司 | Method for forming self-alignment metal silicide |
| CN1591860A (en) * | 2003-09-01 | 2005-03-09 | 上海宏力半导体制造有限公司 | Method for mfg. electrostatic discharge protector by deep amicron process |
| CN1591829A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Self-aligned metal silicide manufacturing method |
-
2005
- 2005-11-08 CN CNB2005101101227A patent/CN100452324C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6530380B1 (en) * | 1999-11-19 | 2003-03-11 | Chartered Semiconductor Manufacturing Ltd. | Method for selective oxide etching in pre-metal deposition |
| CN1341957A (en) * | 2000-09-04 | 2002-03-27 | 中国科学院半导体研究所 | Method for growing silicon oxide thick film by adopting TEOS source PECVD |
| CN1435875A (en) * | 2002-02-01 | 2003-08-13 | 旺宏电子股份有限公司 | Method for making selective local self-aligned silicide |
| CN1484285A (en) * | 2002-09-18 | 2004-03-24 | 上海宏力半导体制造有限公司 | Method for forming self-alignment metal silicide |
| CN1591829A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Self-aligned metal silicide manufacturing method |
| CN1591860A (en) * | 2003-09-01 | 2005-03-09 | 上海宏力半导体制造有限公司 | Method for mfg. electrostatic discharge protector by deep amicron process |
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| CN1964003A (en) | 2007-05-16 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |