CN100448265C - Method and device for adjusting horizontal synchronous signal and vertical synchronous signal - Google Patents

Abstract

A method for regulating horizontal synchronous signal and vertical synchronous signal used in display includes defining a period of time from before to after rising/falling edge of each pulse in vertical synchronous signal as a dangerous range, delaying vertical synchronous signal if rising/falling edge of pulse in horizontal synchronous signal is in dangerous range to let dangerous range be behind rising/falling edge of pulse in horizontal synchronous signal for avoiding image instability and jitter caused by frequency float.

Description

Method and device for adjusting horizontal synchronization signal and vertical synchronization signal

【Technical field】

The invention relates to a method and a device for adjusting a horizontal synchronous signal and a vertical synchronous signal, in particular to a method and a device for adjusting a horizontal and vertical synchronous signal for eliminating jumping and instability of a display screen.

【Background technique】

The display must display, for example, 30 images within one second to form a continuous image in accordance with the persistence of vision of the human eye. Each image includes a plurality of scanning lines, and each scanning line includes a plurality of pixels. Therefore, the image signal received by the display from the image processing system is a series of data corresponding to each pixel. In order for the display to confirm the corresponding pixel position of each data, the image processing system will synchronize with the image signal to send a horizontal synchronization signal representing the start of a scanning line (also known as line feed), and a horizontal synchronization signal representing the start of a picture (also known as page feed). the vertical sync signal. For the sake of illustration, the horizontal and vertical synchronous signals described below take the rising edge of the digital pulse (that is, the address changed from low level to high level) to represent line feed and page change respectively, so when the monitor receives the horizontal synchronous signal pulse At the rising edge, it is known that it will receive the data of the next scanning line, and when it receives the rising edge of the vertical synchronization signal pulse, it is known that it will receive the data of the next frame, so that the image signals are displayed correctly and sequentially.

However, in actual display, the frequency of the horizontal synchronization signal and the vertical synchronization signal may fluctuate slightly due to external factors such as interference and crosstalk, and the frequency may increase or decrease. If it happens that the rising edges of the two rise at the same time and almost overlap, once the frequency fluctuates, it will cause the two to jump in sequence. As shown in Figure 1, the horizontal axis represents time. The rising edges 111 and 121 of the horizontal synchronization signal 11 and the vertical synchronization signal 12 overlap almost at the same time position, and the frequency fluctuation will cause the rising edge 121 of the vertical synchronization signal to be ahead of the rising edge of the horizontal synchronization signal 111. One cycle T, or a delay of one cycle T. If in the Nth picture, the rising edge 111 of the horizontal synchronizing signal 11 is after the rising edge 121 of the vertical synchronizing signal 12, so it is determined as the first line of the picture, and when the N+1 picture is reached, the horizontal synchronizing signal 11 The rising edge 111 is before the rising edge 121 of the vertical synchronizing signal 12 , so that the data of the first line continuing from the Nth frame is misjudged and not displayed, and the data of the second line is presented as the first line instead. If at the N+2th sheet, the rising edge 111 of the horizontal synchronizing signal 11 floats to after the rising edge 121 of the vertical synchronizing signal 12, the first line of data will sometimes disappear in the continuous picture, and the image picture will go up and down. , showing unstable jitter and degrading the displayed image quality.

On the contrary, as shown in Figure 2, if the rising edge 121' of the vertical synchronizing signal 12' lags behind the rising edge 111' of the horizontal synchronizing signal 11' by more than the dangerous range where jumping may occur, even if the frequency fluctuates, the image will still not be unstable. Condition.

However, it would be too irresponsible to leave such factors that seriously endanger the image quality to chance and luck. If it can be ensured that the rising edges 111 ′, 121 ′ of the horizontal synchronizing signal 11 ′ and the vertical synchronizing signal 12 ′ maintain a certain time interval (that is, greater than the dangerous range), it can effectively prevent the frequency fluctuation phenomenon from causing the two rising edges 111 , 121 to follow one another. Change the relationship, avoid this phenomenon of sudden and sudden in order to completely solve the aforementioned problems. Therefore, the main feature of this case is that when the time distance between the two rising edges is less than the dangerous range, the distance between the two rising edges is automatically increased to ensure a certain safe time distance between the two, and to fully avoid image instability and jitter caused by frequency fluctuations.

【Content of invention】

An object of the present invention is to provide a method for adjusting the horizontal synchronization signal and the vertical synchronization signal, so as to automatically avoid image instability caused by frequency fluctuation.

Another object of the present invention is to provide a device for adjusting the horizontal synchronous signal and the vertical synchronous signal to achieve the effect of ensuring a constant and safe time interval between the rising/falling edges of the horizontal and vertical synchronizing signals.

Therefore, the method for adjusting the horizontal synchronous signal and the vertical synchronous signal of the present invention is used in a display, and the horizontal synchronous signal and the vertical synchronous signal have a plurality of pulses respectively, and the method includes the following steps:

A) Delay the received original vertical synchronous signal with a delay time equal to or greater than one display clock signal period T to form a first vertical synchronous signal, and then delay the first vertical synchronous signal to form a second vertical synchronous signal , a dangerous range is formed by the time distance between the rising/falling edges of the original vertical synchronization signal and the second vertical synchronization signal; and

B) If the rising/falling edge of the horizontal sync signal pulse is within the dangerous range, delaying the first vertical sync signal so that the dangerous range is after the rising/falling edge of the horizontal sync signal pulse.

Therefore, a device for adjusting the horizontal synchronous signal and the vertical synchronous signal is arranged in a display, the period of the clock signal of the display is T, and the horizontal synchronous signal and the vertical synchronous signal have multiple pulses respectively, and the device is characterized in that Include:

A hazardous pulse forming circuit having:

A first delay circuit for receiving an original vertical synchronous signal from the outside and delaying it for a first delay time equal to or greater than one cycle T to output as a first vertical synchronous signal;

A second delay circuit, used to receive the first vertical synchronization signal and delay it for a second delay time to form a second vertical synchronization signal output; and

a pulse generator for receiving the second vertical synchronization signal and the original vertical synchronization signal and forming a dangerous pulse corresponding to the time interval between the rising/falling edges of the two signals;

A judging circuit for receiving the output signal of the dangerous pulse forming circuit and the horizontal synchronizing signal and judging whether the rising/falling edge of the horizontal synchronizing signal pulse is within the dangerous pulse, and outputting a trigger signal; and

A delay loop for receiving the first vertical synchronization signal and being activated when receiving the trigger signal, so that the first vertical synchronization signal is delayed and output, so that the dangerous pulse is located at the rising/falling edge of the horizontal synchronization signal pulse after.

【Description of drawings】

Below in conjunction with accompanying drawing and embodiment the present invention is described in detail:

FIG. 1 is a waveform diagram of a conventional horizontal synchronization signal and vertical synchronization signal, wherein a rising edge of the horizontal synchronization signal and a rising edge of the vertical synchronization signal occur simultaneously.

FIG. 2 is a waveform diagram of a conventional horizontal synchronization signal and vertical synchronization signal, wherein a rising edge of the horizontal synchronization signal lags behind a rising edge of the vertical synchronization signal.

Figure 3 is a block schematic diagram of a preferred embodiment of the present invention incorporated into a display.

FIG. 4 is a detailed circuit diagram of the preferred embodiment shown in FIG. 3 .

FIG. 5 is a waveform diagram illustrating an example of input and output signals of the first delay circuit in FIG. 4 .

FIG. 6 is a waveform diagram illustrating an example of input and output signals of the second delay circuit in FIG. 4 .

FIG. 7 is a waveform diagram illustrating an example of input and output signals of the pulse generator in FIG. 4 .

FIG. 8 is a waveform diagram illustrating an example of input and output signals of the decision circuit in FIG. 4. Referring to FIG.

FIG. 9 is a waveform diagram illustrating another example of input and output signals of the decision circuit in FIG. 4. Referring to FIG.

FIG. 10 is a waveform diagram illustrating an example of input and output signals of the delay loop in FIG. 4 .

FIG. 11 is a signal processing flowchart of the embodiment in FIG. 4 .

【Detailed ways】

Sv, the original horizontal synchronous signal Ho, and the original vertical synchronous signal Vo are sent to a display 3, and an image processing circuit 5 in the display 3 drives the display 3 to display image frames according to the instructions of the signals Sv, Vo, and Ho. As mentioned above, before the original vertical and horizontal synchronous signals Vo, Ho are input to the image processing circuit 5 of the display 3, a certain safe time interval should be ensured between the rising/falling edges of the two synchronous signals Vo, Ho, so as to avoid image instability with the beating situation. The device 4 for adjusting the horizontal synchronous signal and the vertical synchronous signal according to an embodiment of the present invention is disposed in the display 3 and located between the image processing system 2 and the image processing circuit 5 . The adjustment device 4 includes a dangerous pulse forming circuit 41 , a determination circuit 42 and a delay circuit 43 . Generally, the original horizontal and vertical synchronization signals Ho and Vo are composed of multiple pulses, and trigger the image processing circuit 5 to change lines or pages with rising edges (or falling edges). For the convenience of explanation, the original horizontal and vertical synchronization signals are assumed hereinafter Both Ho and Vo trigger actions with their rising edges.

The danger pulse forming circuit 41 forms a danger pulse a period of time after the rising edge of each pulse in the original vertical synchronous signal Vo to define a danger range, and a series of danger pulses form a danger pulse signal VP. The dangerous pulse forming circuit 41 has a first delay circuit 411 , a second delay circuit 412 and a pulse generator 413 .

The first delay circuit 411 receives the original vertical synchronous signal Vo and delays it for a period of time to form a first vertical synchronous signal V _S1 for output. The second delay circuit 412 receives the first vertical synchronous signal V _S1 and delays it again to form a second vertical synchronous signal V _S2 which is input to the pulse generator 413 . The pulse generator 413 simultaneously receives the original vertical synchronous signal V ₀ and the second vertical synchronous signal V _S2 , compares the two signals, and generates a dangerous pulse signal _VP corresponding to the delay period between the two rising edges, and outputs it to the determination circuit 42 .

Referring to FIG. 4 , the first delay circuit 411 of this embodiment is composed of an OR gate (OR gate) 60 , a resistor 61 and a capacitor 62 . One end of the resistor 61 is electrically connected to the line 22 for transmitting the original vertical synchronization signal V ₀ , and the other end is electrically connected to two interconnected input ends 601 , 602 of the OR gate 60 . One end of the capacitor 62 is electrically connected to the two input ends 601 and 602 of the OR gate 60 , and the other end is grounded. As shown in FIG. 5, when the original vertical synchronous signal _V0 is fed into the first delay circuit 411, the delay effect of the capacitor 62 (i.e., the capacitor charging and discharging effect) is used to shift the overall waveform backward by a first delay time. A delay time is not less than one period T (period of the clock signal of the display 3) and can be set by variable resistors and capacitors. In this way, the output terminal 603 of the OR gate 60 outputs the first vertical synchronous signal V _S1 delayed by a period of time from the original vertical synchronous signal V ₀ .

The second delay circuit 412 is the same as the first delay circuit 411 , and is also composed of a resistor 64 , an OR gate 65 and a capacitor 66 . One end of the resistor 64 is electrically connected to the output end 603 of the OR gate 60 of the first delay circuit 411 , and the other end is electrically connected to two interconnected input ends 651 , 652 of the OR gate 65 . One end of the capacitor 66 is electrically connected to the two input ends 651 and 652 of the OR gate 65, and the other end is grounded. Therefore, when the first vertical synchronous signal V _S1 is fed into the second delay circuit 412, it is delayed by a second delay time through the delay effect of the capacitor 66, and is output by the output terminal 653 of the OR gate 65 (as shown in FIG. 6 ). The first vertical synchronous signal V _S1 is delayed by a second vertical synchronous signal V _S2 for a second delay time.

Through the aforementioned first and second delay circuits 411, 412, each rising edge of the second vertical synchronous signal V _S2 lags behind the rising edge of the original vertical synchronous signal V ₀ for a certain period of time (the first delay time plus the second delay time), and by This period is a dangerous range. That is to say, when the horizontal synchronous signal H ₀ appears within this period of time, once the frequency fluctuates, the picture will be unstable, so the pulse generator 413 forms a dangerous period between the rising edges of the two vertical synchronous signals V ₀ and V _S2 respectively. The pulse is used for detection by the subsequent determination circuit.

The pulse generator 413 in this example includes an exclusive-OR gate (exclusive-OR) 67 and an AND gate (AND gate) 68 . One input terminal 671 of the exclusive OR gate 67 is electrically connected to the output terminal 653 of the OR gate 65 of the second delay circuit 412 , and the other input terminal is electrically connected to the line 22 for transmitting the original vertical synchronization signal V ₀ . One input terminal 681 of the AND gate 68 is electrically connected to the output terminal 673 of the XOR gate 67 , and the other input terminal 682 is electrically connected to the line 22 for transmitting the original vertical synchronization signal V ₀ . 7, when the XOR gate 67 receives the second vertical synchronous signal V _S2 and the original vertical synchronous signal V ₀ , only one of the two signals outputs a high level when it is high, and when both are the same (i.e. both When the level is high or both are low), then the output is low, so the second vertical synchronous signal V S2 can be output only when the level between V _S2 and the original vertical synchronous signal V ₀ is different, that is, it corresponds to the second vertical synchronous signal The delay between V _S2 and the rising edge (falling edge) of the original vertical synchronization signal V ₀ can only be output when the level between the second vertical synchronization signal V _S2 and the original vertical synchronization signal V ₀ is different, that is, it corresponds to the second vertical synchronization signal The delay period between V _S2 and the rising edge (falling edge) of the original vertical synchronous signal V ₀ can form a series of pulse signals, and output to the AND gate 68 to compare with the original vertical synchronous signal V ₀ to output only corresponding to two synchronous The dangerous pulses in the delay period between the rising edges of the signals V ₀ and V _S2 are deleted, and the pulses corresponding to the falling edges are deleted, and finally the dangerous pulse signal _VP is formed and output to the determination circuit 42 . Of course, as those skilled in the art can understand, the delay period between falling edges can also be selected here instead.

Because each dangerous pulse in the dangerous pulse signal _VP represents the dangerous range around each rising edge of the original vertical synchronous signal V ₀ , if the rising edge of the horizontal synchronous signal H ₀ falls between them, the picture may be unstable when the frequency fluctuates , otherwise there is no doubt about it, so the determination circuit 42 is used to determine whether the rising edge of the horizontal synchronization signal _H0 falls within this range.

The decision circuit 42 in this example includes a delay flip-flop (also known as a D-type flip-flop) 69 and an OR gate 70 . One input end 701 of the OR gate 70 is electrically connected to the positive output end Q of the delay flip-flop 69, and the other input end 702 is electrically connected to the output end 683 of the AND gate 68 of the pulse generator 413 to receive the dangerous pulse signal V _P , the output terminal 703 is electrically connected to the signal input terminal D of the delay flip-flop 69 . The timing input terminal CLK of the delay flip-flop 69 is electrically connected to the line 23 for transmitting the horizontal synchronization signal Ho to receive the horizontal synchronization signal Ho. When the rising edge of the horizontal synchronization signal Ho is fed in, if the dangerous pulse signal V _P of the signal input terminal D of the delay flip-flop 69 happens to be a dangerous pulse (high level), its forward output terminal Q will output a dangerous pulse (i.e. high level), fed into the delay loop 43 as a trigger signal V _T , and due to the feedback control of the OR gate 70, the trigger signal is always held and output.

When the judging circuit 42 receives the rising edge of the horizontal synchronization signal _Ho , it outputs the dangerous pulse signal V _P fed in at this time, as shown in FIG. The high-level trigger signal V _T is fed back to the input determination circuit 42 so that when the next rising edge of the horizontal synchronization signal Ho is fed in, the determination circuit 42 still maintains a high-level output and locks the trigger signal V _T . In this way, once the horizontal synchronization signal Ho falls within the dangerous range, the determination circuit 42 will continue to output the trigger signal. Conversely, if the delay loop 43 receives the first vertical synchronous signal V _S1 and the trigger signal V _P , when the trigger signal V _T is received, the first vertical synchronous signal V _S1 is delayed for a period of time before being input to the image processing circuit 5 , As a result, the dangerous pulse is located after the rising edge of the horizontal synchronization signal H ₀ (as shown in FIG. 2 ). On the contrary, if the trigger signal V _T is not received, the first vertical synchronous signal V _S1 is output to the image processing circuit 5 almost without delay.

The delay circuit 43 of this embodiment includes a switch element 431 and a third delay circuit 432 . As shown in FIG. 4 , the switch element 431 is a transistor 71 , its base 711 is electrically connected to the positive output terminal Q of the delay flip-flop 65 through a resistor 72 , and its emitter 713 is grounded. The third delay circuit 432 is similar to the aforementioned first and second delay circuits 411 and 412 , including a resistor 73 , an OR gate 74 and a capacitor 75 . One end of the resistor 73 is electrically connected to the output end 603 of the OR gate 60 of the first delay circuit 411 , and the other end is electrically connected to two interconnected input ends 741 , 742 of the OR gate 74 . One terminal of the capacitor 75 is electrically connected to the two input terminals 741 and 742 of the OR gate 74 , and the other terminal is electrically connected to the collector 712 of the transistor 71 .

In this way, when the trigger signal V _T is not fed into the transistor 71, the transistor 71 is not turned on. Since the capacitor 75 of the third delay circuit 432 is not grounded, the delay function of the third delay circuit 432 does not work, and the first vertical synchronization The signal V _S1 is not delayed (the "undelayed" means that there is no obvious time delay caused by the influence of the capacitor 75, but since the first vertical synchronous signal V _S1 is output through the third delay circuit 432, the output signal and the input signal There will be a slight time difference, such as 9 ns, but it is negligible because it is less than the delay time), that is, the output terminal 743 of the OR gate 74 is output to the image processing circuit 5 . In this embodiment, since the vertical synchronous signal fed into the image processing circuit 5 is the first vertical synchronous signal V _S1 outputted through the first delay circuit 411, the dangerous pulse can be regarded as rising relative to the first vertical synchronous signal V _S1 Along the time before and after.

On the contrary, if the pulse signal V _T is fed into the transistor 71, the transistor 71 is turned on, and the capacitor 75 can be grounded through the collector 712 and the emitter 713 of the transistor 71, so that the third delay circuit 432 can play a delay function, as shown in FIG. 10 As shown, the first vertical synchronous signal V _S1 will be delayed for a safe period of time (for example, 90ns), and the third vertical synchronous signal V _S3 will be output to the image processing circuit 5, so that the dangerous pulse is located after the rising edge of the horizontal synchronous signal _H0 , so that A time interval not smaller than the dangerous range is maintained between the rising edge of the vertical synchronous signal V _S3 input to the image processing circuit 5 and the rising edge of the horizontal synchronous signal H ₀ . Therefore, even if the frequency fluctuates, it can still be ensured that the mutual positional relationship between the rising edges of the vertical synchronous signal V _S3 and the horizontal synchronous signal _H0 will not change, that is, the situation of front and back does not occur, thereby avoiding the occurrence of picture instability .

Therefore, in this embodiment, when the display 3 starts to receive signals from the image processing system 2, the original vertical synchronous signal Vo will first be input to the device 4 of this example, and will be output to the device 4 after comparison with the original horizontal synchronous signal _H0 The image processing device 5 can ensure a safe distance between the rising edge of the horizontal synchronizing signal _H0 received by the image processing circuit 5 and the rising edge of the first vertical synchronizing signal _VS1 , effectively avoiding image jitter caused by frequency fluctuation. Therefore, in the following, the signal processing flow in this embodiment will be described in conjunction with FIG. 11 according to the aforementioned components and their mutual relationships.

In step 81, the dangerous pulse signal V P corresponding to the rising edge of the first vertical synchronous signal V _S1 (that is, the original vertical synchronous signal V ₀ delayed by the first delay circuit 411 ) is formed by the dangerous pulse forming circuit 41, that is, the first vertical synchronous signal V _P is defined. Danger range for each rising edge of the vertical sync signal V _S1 . Here, the original vertical synchronous signal V ₀ is firstly passed through the first and second delay circuits 411 to form the second vertical synchronous signal V _S2 , and the second vertical synchronous signal V _S2 lags behind the original synchronous signal V ₀ for a period of time, which may cause frequency fluctuations. The dangerous time (that is, the first delay time plus the second delay time) is formed by using the XOR gate 67 of the pulse generator 413 for the level difference between the second vertical synchronous signal V _S2 and the original vertical synchronous signal V ₀ pulse (this pulse is the dangerous range near the rising/falling edge), and finally use the AND gate 68 to delete the pulse corresponding to the falling edge in this pulse signal to form the dangerous pulse signal V _P corresponding to the rising edge.

Next, in step 82, use the determination circuit 42 to monitor whether the horizontal synchronous signal _H0 is located in each dangerous pulse of the dangerous pulse signal _VP , that is, whether it falls within the dangerous range, if so, output the trigger signal V _T to inform the delay Loop 43. In this example, the delay flip-flop 69 in the determination circuit 42 receives the dangerous pulse signal _VP and uses the horizontal synchronous signal H ₀ as the timing, so that when the horizontal synchronous signal H ₀ and the pulse of the dangerous pulse signal _VP exist simultaneously In the case of (this situation means that the horizontal synchronous signal _H0 is in the dangerous range of the first vertical synchronous signal _VS1 ), the trigger signal V _T is output (because the dangerous pulse of high level is being input by the input terminal D), and enters the step 83, to enable the delay function of the delay loop 43 to start. On the contrary, if it is judged that the rising edge of the horizontal synchronous signal _H0 is not in the dangerous range (that is, in the corresponding dangerous pulse), then end, and since the delay function of the delay loop 43 is not activated, it is fed into the image processing The vertical synchronization signal of the circuit 5 is the first vertical synchronization signal V _S1 .

In step 83, after the delay circuit 43 receives the trigger signal V _T , it will start its delay function, so that the passed first vertical synchronous signal V _S1 will be delayed for a period of time (such as 90ns), and then output as the third vertical synchronous signal V _S3 to the image processing circuit 5. In this example, since the switching element 431 (i.e., the transistor 71) of the delay loop 43 receives the trigger signal V _T , it will be turned on, so that the capacitor 75 of the third delay circuit 432 is grounded, so that the first vertical synchronization signal V _S1 can be Delay for a period of time so that the dangerous range is changed to after the rising edge of the horizontal synchronization signal H ₀ , so that the rising edges of the horizontal and vertical synchronization signals H ₀ and V _IN are kept at a certain safe distance, so as to solve the problem of image instability in the past.

To sum up, the present invention is used to detect in advance whether the time distance between the rising/falling edges of the horizontal and vertical synchronous signals H ₀ and V _S1 is less than the dangerous range, and when it is less than the dangerous range, the first vertical synchronous signal V is delayed. _S1 lengthens the time distance between the two to exceed the dangerous range, which can effectively avoid the picture instability and jitter caused by frequency fluctuation.

It should be noted that, although the aforementioned embodiment delays the vertical synchronous signal _V0 to make its rising/falling edge away from the rising/falling edge of the horizontal synchronizing signal _H0 , it is also possible to delay the horizontal synchronizing signal _H0 so that the two Keep the time distance between them beyond the dangerous range.

Claims (9)

1. a method of adjusting horizontal-drive signal and vertical synchronizing signal be used for display, and this horizontal-drive signal and vertical synchronizing signal has a plurality of pulses respectively, it is characterized in that the method includes the steps of:

A) with the original vertical sync signal delay that is received, be equal to or greater than a display clock signal period T its time of delay, form one first vertical synchronizing signal, and postpone this first vertical synchronizing signal again and form one second vertical synchronizing signal, by between this original vertical synchronizing signal and this second vertical synchronizing signal rising/trailing edge the time apart from forming a risk range; And

B) if when the rising/trailing edge of the pulse of this horizontal-drive signal is positioned at this risk range, then postpone this first vertical synchronizing signal, cause this risk range to be positioned at after the rising/trailing edge of pulse of this horizontal-drive signal.

2. the method for claim 1 is characterized in that:

Step B) comprise a substep B-1), whether be positioned at this risk range in order to the rising/trailing edge that detects this horizontal synchronization signal pulses.

3. the method for claim 1 is characterized in that:

This method also comprises one and is positioned at this step B) after step C), continued to carry out in order to the delay of guaranteeing this first vertical synchronizing signal.

4. a device of adjusting horizontal-drive signal and vertical synchronizing signal is arranged in the display, and the clock signal cycle of this display is T, and this horizontal-drive signal and vertical synchronizing signal have a plurality of pulses respectively, it is characterized in that this device comprises:

One dangerous pulse shaping circuit has:

One first delay circuit is used for receiving from the outside original vertical synchronizing signal and it is postponed one and exports after being equal to or greater than first time of delay of one-period T, with as one first vertical synchronizing signal;

One second delay circuit forms the output of one second vertical synchronizing signal after being used to receive this first vertical synchronizing signal and making it postpone for one second time of delay; And

One pulse generator, be used to receive this second vertical synchronizing signal and this original vertical synchronizing signal and corresponding between the rising/trailing edge of this two signal the time apart from forming a dangerous pulse;

One decision circuit, be used to receive output signal and this horizontal-drive signal of this danger pulse shaping circuit and judge whether the rising/trailing edge of this horizontal synchronization signal pulses is positioned at this danger pulse, and when judgement is positioned at this danger pulse, export a triggering signal; And

One delay loop is used to receive this first vertical synchronizing signal and is activated when receiving this triggering signal, so that this first vertical synchronizing signal postpones back output, causes this danger pulse to be positioned at after the rising/trailing edge of this horizontal synchronization signal pulses.

5. device as claimed in claim 4 is characterized in that:

This first delay circuit comprises a resistance, an electric capacity and one or door, one termination of this resistance is received this original vertical synchronizing signal, the other end connects two interconnective inputs of this or door, one end of this electric capacity is electrically connected two inputs of this or door and other end ground connection, exports this first vertical synchronizing signal with the output from this or door.

6. device as claimed in claim 4 is characterized in that:

This second delay circuit comprises a resistance, an electric capacity and one or door, one termination of this resistance is received this first vertical synchronizing signal and the other end connects two interconnective inputs of this or door, one end of this electric capacity is electrically connected two inputs of this or door and other end ground connection, exports this second vertical synchronizing signal with the output from this or door.

7. device as claimed in claim 4 is characterized in that:

This pulse generator have an XOR gate and one and the door, one input of this XOR gate receives this original vertical synchronizing signal, another input of this XOR gate receives this second vertical synchronizing signal, one output that should be connected this XOR gate with an input of door, should be electrically connected this original vertical synchronizing signal with another input of door, to export dangerous pulse from this output with door.

8. device as claimed in claim 4 is characterized in that this decision circuit comprises one and postpones flip-flop and one or door, wherein,

Should or an input of door receive dangerous pulse, another input is connected to the positive output end of this delays flip-flop, should or an output of door connect the signal input part of this delay flip-flop;

The signal input part of this delay flip-flop connects the output of this or door to receive dangerous pulse, the sequential input of this delay flip-flop receives this horizontal-drive signal, and when the rising of this horizontal-drive signal/trailing edge feed-in, if the dangerous pulse signal of the signal input part of this delay flip-flop is dangerous pulse, the positive output end that then should postpone flip-flop is this danger pulse output, with as triggering signal.

9. device as claimed in claim 8 is characterized in that:

This delay loop comprises one and is subjected to the switch element and of this start trigger signal to be subjected to the 3rd delay circuit of this switch element control, the 3rd delay circuit is driven by this switch element and postpones this first vertical synchronizing signal and export, this switch element is a transistor, its base stage receives this triggering signal and grounded emitter, the 3rd delay circuit comprises a resistance, one electric capacity and one or the door, one termination of this resistance is received this first vertical synchronizing signal and the other end connects two interconnective inputs the 3rd delay circuit or door, and an end of this electric capacity is electrically connected two inputs the 3rd delay circuit or door and the other end connects this transistorized collector electrode.

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