CN100447858C - Display controller capable of reducing use of cache and frame adjusting method thereof - Google Patents

Abstract

A display controller and a frame adjusting method thereof are provided to reduce the use of a cache. The display controller includes a memory controller, a first memory, a second memory, and a frame management circuit. The memory controller reads the image data of the source frame portion to obtain first image data, and reads the image data of the destination frame portion to obtain second image data. The first memory is used for storing first image data. The second memory is used for storing second image data. The frame management circuit is used for processing the first image data to generate processed first image data, and superposing the processed first image data to the second image data in the second memory to obtain processed second image data. And if the processed second image data needs to be processed again, the display controller writes the processed second image data back to the external memory.

Description

Display controller capable of reducing cache usage and frame adjustment method thereof

technical field

The invention relates to a display controller and a frame adjustment method thereof, in particular to a display controller capable of reducing cache usage and an adjustment method thereof.

Background technique

With the advancement of technology, various electronic products have gradually become the focus of human life, and the display effect of electronic products has become a major factor that attracts consumers to buy. The display screen of an electronic product is obtained by processing and superimposing multiple frames to obtain the final display screen. Its operation is such as superimposing the processed sub-frames on the main frame to obtain a display image.

The above applications are used, for example, in function menus displayed by electronic devices. Various functions that can be used by electronic devices have increased significantly. In order to facilitate the selection of various function options in the electronic device, most of the current manufacturers provide graphical menus on the display screen for users to click.

Please refer to FIG. 1 , which shows a schematic diagram of a display controller. The display controller 30 accesses frame image data from the external memory 10 through the bus 20 . The external memory 10 is a synchronous dynamic random access memory (Synchronous Dynamic Random Memory Access, SDRAM). Several frames are stored in the external memory 10 , and the display controller 30 reads the frames from the external memory 10 and processes the frames, superimposes the processed image data of each frame, and outputs them to the display 40 to generate a picture. The frame processing operation of the display controller 30 includes rotating, mirroring, zooming in, zooming out or moving the frame, and then performing frame overlapping. In order to perform the aforementioned processing operations, the display controller 30 must randomly access the image data of each frame in the external memory 10 . In the process of processing each frame, a frame buffer with the same size as the screen of the display 40 is required to store the screens that have not been processed by the display controller 30 .

If the frame buffer is placed in the external memory 10, then when the display controller 30 intends to process the unprocessed picture, the display controller 30 needs to read the unprocessed picture from the frame buffer in the external memory 10 and process. Since the access speed of the SDRAM is relatively slow, the display controller 30 will spend a relatively long access time in the process of accessing the frame buffer.

In order to avoid the above situation, a cache memory (Cache Memory) is configured inside the display controller 30 as a frame buffer, and this cache memory must be able to store the entire display screen. The display controller 30 first stores the image data of the whole frame in the cache memory, and then calculates by matrix operation, and finally generates the required display screen according to the result of the matrix operation and the image data.

However, since the frame buffer needs to store the entire display image, a high-speed cache capable of storing the entire display image requires a relatively large memory capacity. Although the high-speed cache with a considerable size can reduce the access time of the display controller, it also increases the production cost of the traditional display controller, thereby reducing the competitiveness in the market.

Contents of the invention

In view of this, the object of the present invention is to provide an image controller and its frame adjustment method which can reduce the use of cache memory. By changing the hardware design in the display controller, the access time in the process of the display controller accessing image data is reduced. And through the change of the hardware design, the cache memory capacity equipped in the display controller can be reduced at the same time, thereby reducing the production cost.

According to the purpose of the present invention, a display controller that can reduce the use of cache memory is proposed. The display controller is electrically connected with the external memory, and the external memory is used for storing the destination frame and the source frame. The display controller includes memory controller, internal memory and frame management circuit. The memory controller reads the image data of the source frame part to obtain a first image data, and reads the image data of the destination frame part to obtain a second image data. The internal memory includes a first memory and a second memory. The first memory is used for storing two columns of pixels of the first image data. The second memory is used for storing a row of pixels of the second image data. The frame management circuit processes the first image data to generate processed first image data, and overlaps the processed first image data with the second image data in the second memory to obtain processed second image data. If the processed second image data still needs to be processed again, the display controller writes the processed second image data back to the external memory.

According to another object of the present invention, a frame adjustment method that can reduce cache usage is proposed. The frame adjustment method is used to process a source frame and a destination frame in an external memory. The frame adjustment method is used in a display controller. The display controller includes a first memory and a second memory. The frame adjustment method includes the following steps: first, The image data of the source frame part is read to obtain a first image data and stored in the first memory. Next, read the image data of the target frame part to obtain a second image data, and store it in the second memory. Next, the first image data is processed to generate processed first image data. Then, superimpose the processed first image data to the second image data in the second memory to obtain a processed second image data. Finally, it is determined whether the processed second image data still needs to be reprocessed, and if it still needs to be reprocessed, the processed second image data is written back to the external memory.

In order to make the above-mentioned purpose, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and is described in detail with reference to the accompanying drawings.

Description of drawings

Figure 1 shows a schematic diagram of a display controller.

FIG. 2 shows a block diagram of a display controller proposed in accordance with the present invention.

FIG. 3 shows a schematic diagram of image data of each pixel of a source frame and a destination frame.

FIG. 4A shows a schematic diagram of superimposing a source frame to a destination frame.

FIG. 4B is a schematic diagram of shifting the source frame to the destination frame compared to FIG. 4A .

FIG. 5 shows a schematic diagram of superimposing the source frame to the destination frame after left-right mirroring relative to FIG. 4A .

FIG. 6 shows a schematic diagram of the source frame rotated 90 degrees clockwise with respect to FIG. 4A and superimposed to the target frame.

FIG. 7 shows a schematic diagram of superimposing the source frame to the target frame after zooming in relative to FIG. 4A .

Fig. 8 shows a flow chart of the frame adjustment method.

Description of reference symbols

10: External memory

20: bus

30: Display Controller

40: display

50: Display controller that reduces cache usage

110: source frame

120: destination frame

510: memory controller

520: internal memory

522: First memory

524: Second memory

530: frame management circuit

Detailed ways

The function of the display controller is to move, scale, mirror or rotate the source frame to be superimposed to the target frame, and then superimpose it to the target frame. The concept of the present invention is to reduce the internal memory configured in the display controller by changing the way of hardware design without affecting the aforementioned processing functions, which can effectively save the production cost of the display controller.

Please refer to FIG. 2 , which shows a block diagram of a display controller according to the present invention. The display controller 50 accesses the image data from the external memory 10 through the bus 20, and outputs the processed image data to a display 40 having n rows of pixels×m columns of pixels to form a display 40 having n rows of pixels×m columns of pixels Display screen, n and m are non-zero positive integers. The external memory 10 can be, for example, a synchronous dynamic random access memory (Synchronous Dynamic Random Memory Access, SDRAM). The external memory 10 stores the image data of the destination frame 120 and the image data of the source frame 110. The destination frame 120 is, for example, the menu background in the function option screen of the mobile phone, and the source frame 110 is, for example, each option pattern in the menu.

The display controller 50 includes a memory controller 510 , an internal memory 520 and a frame management circuit 530 . The memory controller 510 selects and reads a part of the image data D0 of the target frame 120 from the external memory 10 to generate a second image data D1 . The second image data D1 is, for example, a row of image data of the target frame 120 . The memory controller 510 reads part of the image data S0 in the source frame 110 to generate a first image data S1 , for example, the first image data S1 may be a column of image data in the source frame 110 . The frame management circuit 530 has the ability to adjust the size, rotate, mirror, translate and overlap the source frame 110 .

The internal memory 520 is, for example, a cache, and the internal memory 520 includes a first memory 522 and a second memory 524 . The first memory 522 and the second memory 524 of the internal memory 520 do not need to store the entire display frame, and the capacity of the first memory 522 depends on the maximum width of the supported source frame. If the maximum width of the source frame is M, that is, a column of the source frame has at most M pixels, then the first memory 522 can store 2M pixels. The capacity of the second memory 524 depends on the number of lines of the display screen of the display 40 . That is, one column of the display screen has several pixels. If the display screen has N rows, that is, one column of the display screen has N pixels. Therefore, the capacity of the internal caches 522 and 524 is only enough to store two columns of pixels of the source frame and one column of pixels of the destination frame respectively, which is enough for the display controller 50 to perform various processing on the frames. The first memory 522 is used for storing the first image data S1. The second memory 524 is used for storing the second image data D1.

The frame management circuit 530 processes the first image data S1 to generate a processed first image data S2 (not shown in the figure), so that the processed first image data S2 is superimposed into the second memory 524 The second image data D1 to obtain a processed second image data D2. When the processed second image data D2 in the second memory 524 still needs to be processed again, the display controller 50 writes the processed second image data D2 back to the external memory 10 . If the processed second image data D2 does not need further processing, the memory controller 510 outputs the processed second image data D2 to the display 40 .

Please refer to FIG. 3 , which shows a schematic diagram of image data of each pixel of the source frame and the destination frame. The source frame 110 can be, for example, a frame with 4 rows of pixels×2 columns of pixels, and the image data of each pixel in the first column is P11, P21, P31, P41 in sequence from left to right, and the image data of each pixel in the second column Data from left to right are P12, P22, P32, P42. The target frame 120 is a frame with n rows of pixels×m columns of pixels, the pixel image data of the first column are Q11, Q21, Q31 to Qn1 from left to right, and the pixel image data of the second column are from left to right The sequence is Q12, Q22, Q32 to Qn2, and so on to the mth column. Each pixel data of the target frame 120 corresponds to a pixel position, for example, the pixel position of the pixel data Q22 in the second row and second column in the target frame 120 is (2, 2). The display controller 50 is responsible for superimposing each pixel data of the source frame 110 to the destination frame 120 after processing. frame. They will be described separately later.

Please refer to FIG. 4A and FIG. 4B , FIG. 4A shows a schematic diagram of superimposing a source frame to a destination frame, and FIG. 4B shows a schematic diagram of superimposing a source frame to a destination frame after shifting relative to FIG. 4A . Taking FIG. 4B as an example, if the source frame 110 with 4 rows of pixels×2 columns of pixels is to be superimposed to the destination frame 120 with n rows of pixels×m columns of pixels, and the source frame 110 is superimposed into the destination frame 120 The pixel positions of are (2, 2), (3, 2), (4, 2), (5, 2), (2, 3), (3, 3), (4, 3) and (5, 3). The memory controller 510 of the display controller 50 sequentially reads the image data Q11 , Q21 to Qn1 of the first column in the target frame 120 through the bus 20 to obtain the second image data D1 and stores it in the second memory 524 . The memory controller 510 sequentially reads the image data P11 , P21 , P31 , P41 of the first row in the source frame 110 through the bus 20 to obtain the first image data S1 and stores it in the first memory 522 . At this time, if the first image data S1 does not need other processing, the first image data S1 is used as the processed first image data S2.

Since the image data P11, P21, P31, and P41 in the first row of the source frame 110 are to be superimposed to the second row of the destination frame 120, the second row of the destination frame 120 is the corresponding position of the destination frame at this time, so the frame management The circuit 530 does not superimpose the image data P11, P21, P31, P41 of the first column in the source frame 110 to the image data of the first column in the destination frame, but directly processes the second image data D1 of the destination frame 120 The latter second image data D2 is output to the first row of pixels of the display 40 to display the image. Until the memory controller 510 reads the image data Q12 , Q22 to Qn2 of the second row in the target frame 120 to obtain the second image data D1 and store it in the second memory 524 . The frame management circuit 530 overlaps the processed first image data S2 to the second image data D1 in the second memory 524, and sequentially overlaps from the second pixel Q22 in the second image data D1 to obtain The processed second image data D2 is the image data Q12, P11, P21, P31, P41, Q62 to Qn2. The display controller 50 outputs the processed second image data D2 to the second row of pixels of the display 40 to display the image. The image data of the second column in the source frame 110 is also superimposed to the column image data of the corresponding target frame 120 as described above, and the operation of superimposing the source frame to the target frame is completed. The image is like the image in the first column, and can be directly output to the display monitor 40 because there is no overlapping and no other processing is required.

The operation of superimposing the source frame 110 to the destination frame 120 after being moved is to superimpose the image data of the source frame 110 to the position corresponding to the moved destination frame, so as to complete the superimposition after the source frame is moved by the display controller 50 Processing operations to the destination frame.

Please refer to FIG. 5 , which shows a schematic diagram of superimposing the source frame to the destination frame after left-right mirroring relative to FIG. 4A . For example, if the source frame 110 is to be mirrored left and right first, and then superimposed into a target frame 120 having n rows of pixels×m columns of pixels, and the image data P11, P21, P31, P41, P12, P22, P32, and P42 are respectively superimposed to the pixel positions in the target frame 120 as (4, 1), (3, 1), (2, 1), (1, 1), (4, 2) , (3,2), (2,2), (1,2). The memory controller 510 of the display controller 50 sequentially reads the image data Q11 , Q21 to Qn1 of the first column in the target frame 120 through the bus 20 to obtain the second image data D1 and stores it in the second memory 524 . In order to overlap the source frame 110 to the target frame 120 after left and right mirroring, the memory controller 510 reads the image data P41 and P31 of the first column in the source frame 110 through the bus 20 according to the sequence after the source frame 110 is mirrored. . . If the first image data S1 does not need other processing, the first image data S1 is taken as the processed first image data S2 at this time.

The frame management circuit 530 superimposes the processed first image data S2 to the second image data D1 in the second memory 524, and sequentially superimposes from the first pixel Q11 in the second image data D1 to obtain processed The subsequent second image data D2. The display controller 50 outputs the processed second image data D2 to the first row of pixels of the display 40 to display the image. The image data of the second row in the source frame 110 is also superimposed to the corresponding column image data of the destination frame 120 as described above, so as to complete the processing operation of the display controller 50 mirroring the source frame left and right and superimposing it to the destination frame .

Please refer to FIG. 6 , which shows a schematic diagram of the source frame rotated 90 degrees clockwise relative to FIG. 4A and superimposed to the destination frame. For example, if the source frame 110 with 4 rows of pixels×2 columns of pixels is first rotated 90 degrees clockwise, and then overlapped to a destination frame 120 with n rows of pixels×m columns of pixels. The positions where the source frame 110 is superimposed on the destination frame 120 are (1,1), (1,2), (1,3), (1,4), (2,1), (2,2), (2,3), (2,4). The memory controller 510 of the display controller 50 sequentially reads the image data Q11 , Q21 to Qn1 of the first column in the target frame 120 through the bus 20 to obtain the second image data D1 and stores it in the second memory 524 . The memory controller 510 reads the image data P12 and P11 of the first row in the source frame 110 through the bus 20 according to the order of the source frame 110 rotated clockwise by 90 degrees to obtain the first image data S1 and store it in the first memory 522. At this time, if the first image data S1 does not need to be processed on other images, the first image data S1 is taken as the processed first image data S2.

The frame management circuit 530 superimposes the processed first image data S2 to the second image data D1 in the second memory 524, and sequentially superimposes from the first pixel Q11 in the second image data D1 to obtain processed The latter second image data D2 is the first row of image data P12 , P11 , Q31 , Q41 to Qn1 shown in FIG. 6 . The display controller 50 outputs the overlapped image data to the first row of pixels of the display 40 to display the image. The image data of other columns in the source frame 110 are also superimposed to the column image data of the corresponding destination frame 120 as described above, so that the display controller 50 rotates the source frame clockwise by 90 degrees and then superimposes it to the destination frame processing operations.

Please refer to FIG. 7 , which shows a schematic view of the source frame in FIG. 4A after being enlarged and superimposed to the target frame. In addition to the aforementioned processing functions of mirroring, rotation, and translation, the display controller 50 can also resize the source frame 110 and superimpose it to the destination frame 120 . Because zooming in or out requires two columns of pixels in the source frame to perform linear interpolation to obtain a column of processed image data, the first memory 522 simultaneously stores two columns of image data in the source frame 110 . For example, if a source frame 110 with 4 rows of pixels×2 columns of pixels is to be enlarged twice, and then overlapped to a target frame 120 with n rows of pixels×m columns of pixels, and the source frame 110 is overlapped The pixel positions in the target frame 120 are respectively (1,1), (2,1), (3,1), (4,1), (5,1), (6,1), (7,1 ), (8,1), (1,2), (2,2), (3,2), (4,2), (5,2), (6,2), (7,2), (8, 2), (1, 3), (2, 3), (3, 3), (4, 3), (5, 3), (6, 3), (7, 3), (8 , 3), (1, 4), (2, 4), (3, 4), (4, 4), (5, 4), (6, 4), (7, 4), (8, 4 ).

The memory controller 510 of the display controller 50 sequentially reads the image data Q11 , Q21 to Qn1 of the first column in the target frame 120 through the bus 20 to obtain the second image data D1 and stores it in the second memory 524 . The memory controller 510 reads the first column and the second column image data P11, P21, P31, P41 and P12, P22, P33, P42 in the source frame 110 through the bus 20 to obtain the two column image data S1 and store it in in the first memory 522.

The frame management circuit 530 sequentially determines the first image data S2 of each pixel in the column of the target frame in a linear interpolation manner from left to right. For example, P11 is superposed with Q11, and P11' superimposed with Q21 is the result of interpolation between P11 and P21, and so on. The frame management circuit 530 superimposes the processed first image data S2 to the second image data D1 in the second memory 524, and sequentially superimposes from the first pixel Q11 in the second image data D1 to obtain processed The latter second image data D2. Therefore, the processed second image data D2 does not need further processing, and the display controller 50 outputs the processed second image data D2 to the second row of pixels of the display 40 to display an image.

Next, the memory controller 510 of the display controller 50 sequentially reads the image data Q12, Q22 to Qn2 of the second column in the target frame 120 through the bus 20 to obtain the second image data D1 and store it in the second memory 524 middle. Since the interpolation results of the first column and the second column of the source frame are still to be overlapped with the second column of the target frame, and the first column and the second column already exist in the first memory 522, so there is no need to read source frame. The frame management circuit 530 inserts the image data of dummy pixels between the image data of the first column and the image data of the second row of the source frame 110 in a linear interpolation manner, so that the processed first image data S2 is the image data of dummy pixels P11", P11'", P21", P21'", P31", P31'", P41" and P41'". The frame management circuit 530 superimposes the processed first image data S2 to the second image data D1 in the second memory 524, and sequentially superimposes from the first pixel Q12 in the second image data D1 to be processed The latter second image data D2. The display controller 50 outputs the processed second image data D2 to the second row of pixels of the display 40 to display the image. The image data of other columns in the source frame 110 are also superimposed to the corresponding column image data of the destination frame 120 as described above, so as to complete the processing operation of the display controller 50 to double the source frame and superimpose it to the destination frame .

The aforementioned display controller 50 performs processing operations such as resizing, rotating, mirroring, or moving the source frame 110 and then overlaps it to the target frame. Perform processing operations such as resizing, rotating, mirroring, or moving and overlapping to the target frame. Then, whenever the processed image data D2 obtained after overlapping still needs frame overlapping or other processing, the processed image data D2 is then output to the external memory 10 .

Please refer to FIG. 8 , which shows a flow chart of the frame adjustment method. The frame adjustment method is used to process a source frame and a destination frame in an external memory. The frame adjustment method is used in a display controller. The display controller includes a first memory and a second memory. The frame adjustment method includes the following steps: First, as shown in step 81 , the image data of the source frame 110 is read to obtain the first image data S1 and stored in the first memory 522 . Next, as shown in step 82 , the image data of the target frame 120 is read to obtain the second image data D1 and stored in the second memory 524 . Then, as shown in step 83 , the first image data S1 is processed to generate the processed first image data S2 . Then, as shown in step 84 , the processed first image data S2 is superimposed to the second image data D1 in the second memory 524 to obtain the processed second image data D2 . Finally, as shown in step 85, it is judged whether the processed second image data D2 still needs to be processed again, if so, the processed second image data is written back to the external memory 10; if not, the processed second image data is output to the display 40. Wherein, the second image data D1 is, for example, a row of image data of the target frame. The first image data S1 is, for example, image data of a column or a row of the source frame.

The above embodiments of the present invention disclose a display controller and a frame adjustment method capable of reducing cache memory. With the aforementioned circuit design, the cache memory in the display controller does not need to store the entire display frame. The capacity of the cache memory in the display controller of the present invention only needs to be able to store a row of display images, thereby achieving the effect of cost reduction.

In addition, the present invention also has the advantage of improving reading efficiency. When the memory controller reads the source frame, it also handles the rotation operation at the same time, so that each frame can be read at most only once non-sequentially. Further, the performance of the memory controller to read the external memory is improved.

In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention, and those skilled in the art can make various modifications without departing from the spirit and scope of the present invention. Movement and retouching, so the protection scope of the present invention shall be determined by the claims of the present invention.

Claims (23)

1. A display controller electrically connected to an external memory for storing a destination frame and at least one source frame, the display controller comprising: A memory controller, used to read part of the image data in the source frame to obtain a first image data, and read part of the image data in the destination frame to obtain a second image data; an internal memory including: a first memory for storing the first image data; and a second memory for storing the second image data; and a frame management circuit, used for processing the first image data to generate a processed first image data, so that the processed first image data is superimposed on the second image data in the second memory, so that obtaining a processed second image data; Wherein, if the processed second image data still needs to be processed again, the display controller writes the processed second image data back to the external memory. 2. The display controller as claimed in claim 1, wherein the second image data is a row of image data of the target frame. 3. The display controller as claimed in claim 2, wherein the first image data is a row of image data of the source frame. 4. The display controller as claimed in claim 1, wherein when the display controller intends to resize the source frame and overlap it with the destination frame, the display controller stores the first image data in the second In a memory, the frame management circuit also resizes the first image data in the first memory to generate the processed first image data, and overlaps them into the second memory to obtain the processed second image data. Image data. 5. The display controller as claimed in claim 1, wherein the source frame has a capacity of M rows of pixels, the first memory has a capacity of 2M pixels, and M is a non-zero positive integer. 6. The display controller as claimed in claim 1, wherein the target frame has a capacity of N rows of pixels, the second memory has a capacity of N pixels, and N is a non-zero positive integer. 7. The display controller as claimed in claim 1, wherein if the display controller intends to rotate the source frame and superimpose it on the target frame, the first image data is a line of image data of the source frame, and the first The image data is the processed first image data, and the second image data is a row of image data of the target frame. 8. The display controller as claimed in claim 1, wherein when the display controller intends to overlap the source frame to the target frame after left-right mirroring, the first image data is reflected by a row of image data of the source frame The first image data is the processed first image data, and the second image data is a row of image data of the target frame. 9. The display controller as claimed in claim 1, wherein if the display controller intends to move the source frame and superimpose it to a corresponding position of the destination frame, when the second image data read by the memory controller is When corresponding to the corresponding position, the frame management circuit overlaps the processed first image data with the second image data. 10. The display controller as claimed in claim 1, wherein the external memory is a synchronous dynamic random access memory. 11. The display controller as claimed in claim 1, wherein when the processed second image data does not need to be processed, the memory controller outputs the processed second image data in the second memory to a monitor to display. 12. A frame adjustment method for a display controller to process a source frame and a destination frame in an external memory, the frame adjustment method comprising: reading part of the image data in the source frame to obtain a first image data, and storing it in a first memory of the display controller; reading part of the image data in the target frame to obtain a second image data, and storing it in a second memory of the display controller; After processing the first image data, a processed first image data is generated; superimposing the processed first image data to the second image data in the second memory to obtain a processed second image data; and It is judged whether the processed second image data still needs to be processed again, and if so, the processed second image data is written back to the external memory. 13. The frame adjustment method as claimed in claim 12, wherein the second image data is a row of image data of the target frame. 14. The frame adjustment method as claimed in claim 13, wherein the first image data is a row of image data of the source frame. 15. The frame adjustment method as claimed in claim 12, wherein if the source frame is resized and superimposed to the target frame, further comprising the steps of: The size of the first image data in the first memory is adjusted to generate the processed first image data. 16. The frame adjustment method as claimed in claim 12, wherein the source frame has a capacity of M rows of pixels, the first memory has a capacity of 2M pixels, and M is a non-zero positive integer. 17. The frame adjustment method according to claim 12, wherein the target frame has a capacity of N rows of pixels, the second memory has a capacity of N pixels, and N is a non-zero positive integer. 18. The frame adjustment method according to claim 12, wherein if the source frame is to be rotated and superimposed to the target frame, the first image data is a line of image data of the source frame, and the first image data is The processed first image data and the second image data are a row of image data of the target frame. 19. The frame adjustment method as claimed in claim 12, wherein if the source frame is to be mirrored left and right and superimposed to the target frame, the first image data is a row of image data of the source frame to reverse the pixel sequence Therefore, the first image data is the processed first image data, and the second image data is a row of image data of the target frame. 20. The frame adjustment method as claimed in claim 12, wherein if the display controller intends to move the source frame and superimpose it to a corresponding position of the target frame, when the second image data corresponds to the corresponding position , the display controller reads the source frame to obtain the first image data, and makes the first image data the processed first image data to be superimposed on the second image data. 21. The frame adjustment method according to claim 12, wherein the target frame has a capacity of N rows of pixels, the first memory and the second memory have a capacity of N pixels respectively, and N is a non-zero positive integer. 22. The frame adjustment method as claimed in claim 12, wherein the external memory is a synchronous dynamic random access memory. 23. The frame adjustment method as claimed in claim 12, wherein in the step of judging whether the processed second image data still needs to be processed, if the processed second image data does not need to be processed again, the display controller will The processed second image data is output to a display for display.

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