CN100447837C - Method for improving scan pulse voltage to reduce power consumption - Google Patents
Method for improving scan pulse voltage to reduce power consumption Download PDFInfo
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- CN100447837C CN100447837C CNB2005100961692A CN200510096169A CN100447837C CN 100447837 C CN100447837 C CN 100447837C CN B2005100961692 A CNB2005100961692 A CN B2005100961692A CN 200510096169 A CN200510096169 A CN 200510096169A CN 100447837 C CN100447837 C CN 100447837C
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- 230000000630 rising effect Effects 0.000 claims abstract description 6
- 238000011084 recovery Methods 0.000 claims abstract description 5
- 230000005669 field effect Effects 0.000 claims description 80
- 230000000087 stabilizing effect Effects 0.000 claims description 22
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Abstract
The present invention discloses a method for improving scan pulse voltage to reduce power consumption. The purpose of finally improving voltage redundancy and reducing power consumption can be achieved by improving scan pulse voltage and regulating the plateau voltage of scan driving voltage. Each subfield is divided into an initializing period, an addressing period and a maintaining period, a forming circuit of the initializing period is composed of a forming circuit b of a ramp rising edge and a forming circuit c of a ramp falling edge, a forming circuit of the addressing period is composed of a forming circuit d of plateau voltage Yp, a forming circuit g of negative voltage-Vy and a scan chip e, and a forming circuit of the maintaining period is composed of an energy recovery circuit a. The utility model can improve the voltage redundancy, reduce the power consumption, and improve the image quality.
Description
Technical field
The present invention relates to the method that color plasma display reduces power consumption, particularly improve the method for scan pulse voltage to reduce power consumption.
Background technology
At present, the plasm TV (PDP) as novel development in the large-scale flat-panel screens is subjected to watching attentively of people.PDP utilizes the principle of gas discharge to realize graphic presentation, and its principle is the addressing electrode toward the discharge cell that forms pixel, scan electrode, keep and add voltage in the electrode, and adjust voltage and cause discharge, form ultraviolet ray and impact red, green, blue three kinds of fluorescent powder, and form image.
The effect of address period is to add scan pulse voltage to the discharge cell that will light, and scan pulse voltage is exactly the poor of the 2nd plateau voltage Ypout and negative pressure-Vy.The value of scan pulse voltage and screen inner structure have relevant beyond, the wall CHARGE DISTRIBUTION in the discharge cell has much relations, when the discharge cell inner wall charge was evenly distributed, the scan pulse voltage that needs was relatively little, otherwise the scan pulse voltage that needs is wanted greatly relatively.When carrying out addressing, because the effect during the initialization, when scanning the scan electrode of forward part, the discharge cell inner wall charge distributes very even, the scan pulse voltage that needs is relatively little, when the scan electrode of scanning back, because the long wall CHARGE DISTRIBUTION homogeneity in it of the zero-time of scanning voltage and address period can descend, also relative bigger of the value of the scan pulse voltage that needs.Therefore, select scan pulse voltage often bigger than normal, cause power consumption to increase the shortcoming that the voltage remaining reduces.
Summary of the invention
The objective of the invention is to overcome the shortcoming of above-mentioned prior art, a kind of method of improving scan pulse voltage to reduce power consumption is provided,, adjusts the plateau voltage of turntable driving voltage by improving scan pulse voltage, finally reach and improve the voltage remaining, reduce the purpose of power consumption.
Each son field is divided into during the initialization, address period, and during keeping, the formation circuit during the initialization is made up of the circuit c that forms that forms circuit b and oblique wave negative edge of oblique wave rising edge; The formation circuit of address period be by the 1st plateau voltage Yp form circuit d, negative pressure-Vy form circuit g and scanning chip e forms; Scan pulse voltage is the poor of the 2nd plateau voltage Ypout and virtual earth voltage Yg, and the formation circuit during keeping is made up of energy recovery circuit a;
Follow these steps to carry out:
1) scan pulse voltage in the address period is divided into I, II two parts: the scan pulse voltage II of rear section is than the scan pulse voltage I height of forward part;
2) the 1st voltage stabilizing diode Z1 and the 12nd field effect transistor Q12 parallel circuit have been increased among the formation circuit g of negative pressure-Vy, the anode of its 1st voltage stabilizing diode Z1 connects virtual earth voltage Yg, negative electrode connects the drain electrode of the 12nd field effect transistor Q12, the grid connection control signal of the 12nd field effect transistor Q12, the source electrode of the 12nd field effect transistor Q12 connects negative pressure-Vy; The drain electrode of the 9th field effect transistor Q9 connects virtual earth voltage Yg, the grid connection control signal of the 9th field effect transistor Q9, and the source electrode of the 9th field effect transistor Q9 connects negative pressure-Vy;
The 2nd voltage stabilizing diode Z2 and the 13rd field effect transistor Q13 parallel circuit in the formation circuit d of the 1st plateau voltage Yp, have been increased, the anode of its 2nd voltage stabilizing diode Z2 connects the 1st plateau voltage Yp, negative electrode connects the drain electrode of the 13rd field effect transistor Q13, the grid connection control signal of the 13rd field effect transistor Q13, the source electrode of the 13rd field effect transistor Q13 connect the 2nd plateau voltage Ypout; The drain electrode of the 10th field effect transistor Q10 connects the 1st plateau voltage Yp, the grid connection control signal of the 10th field effect transistor Q10, and the source electrode of the 10th field effect transistor Q10 connects the 2nd plateau voltage Ypout;
3) in address period, the forward part addressing voltage value of address period is less than the addressing voltage value of rear section, the 12nd field effect transistor Q12 conducting when the forward part of address period, and the 9th field effect transistor Q9 disconnects, virtual earth voltage Yg value equals magnitude of voltage and the 1st voltage stabilizing diode Z1 magnitude of voltage addition of negative pressure-Vy, and this moment, virtual earth voltage Yg absolute voltage value was less than negative pressure-Vy absolute value; In the 9th field effect transistor Q9 conducting of the rear section of address period, the 12nd field effect transistor Q12 turn-offs, and this moment, virtual earth voltage Yg magnitude of voltage equaled negative pressure-Vy magnitude of voltage;
4) in address period, the forward part addressing voltage value of address period is less than the addressing voltage value of rear section, the 13rd field effect transistor Q13 conducting when the forward part of address period, and the 10th field effect transistor Q10 disconnects, the 2nd plateau voltage Ypout value equals the 1st plateau voltage Yp value and deducts the 2nd voltage stabilizing diode Z2 magnitude of voltage, and this moment, the 2nd plateau voltage Ypout value was less than the 1st plateau voltage Yp value; The 10th field effect transistor Q10 conducting when the rear section of address period, the 13rd field effect transistor Q13 turn-offs, and this moment, the 2nd plateau voltage Ypout value equaled the 1st plateau voltage Yp value;
5) the scan pulse voltage value is that voltage swing by the input scan chip decides, and the magnitude of voltage of input scan chip equals the poor of the 2nd plateau voltage Ypout and virtual earth voltage Yg, by the 2nd plateau voltage Ypout value of increase address period rear section, or the virtual earth voltage Yg value of reduction address period rear section realizes the scan pulse voltage value function higher than the scan pulse voltage value of address period forward part of address period rear section.
The present invention can improve the voltage remaining by above method, reduces power consumption, improves image quality.
Description of drawings
Fig. 1 is the sub-field pattern of prior art, wherein:
The drive waveforms figure that the drive waveforms figure that the drive waveforms figure that the X-holding circuit produces, Y-sweep circuit produce, A-addressing circuit produce, Yp-the 1st plateau voltage ,-the Vy-negative pressure.
Fig. 2 is that expression Y drive waveforms forms circuit, wherein: Yg-virtual earth voltage, Ypout-the 2nd plateau voltage.
Fig. 3 is a sub-field pattern of the present invention.
Fig. 4 is address period the 2nd plateau voltage Ypout, virtual earth voltage Yg voltage distribution plan.
Fig. 5 is that the Y drive waveforms of adjusting virtual earth voltage Yg magnitude of voltage forms circuit diagram, Z1-the 1st voltage stabilizing diode.
Fig. 6 is that the Y drive waveforms of adjusting the 2nd plateau voltage Ypout magnitude of voltage forms circuit diagram, Z2-the 2nd voltage stabilizing diode.
Embodiment
As shown in Figure 1, PDP is driven by most height field, and represents PDP screen gray level by the luminous number of each son field.Each son field is divided into during the initialization, and address period is during keeping.Be to wipe the discharge that during keeping, produces and make the wall electric charge of discharge cell even during the initialization; Address period is the signal that provides according to external image, adds scan pulse voltage for the discharge cell that will light; Be that the discharge cell that adds scan pulse voltage is kept discharge during keeping.The drive waveforms figure that the drive waveforms figure that the drive waveforms figure that the X-holding circuit produces among Fig. 1, Y-sweep circuit produce, A-addressing circuit produce, Yp-the 1st plateau voltage ,-the Vy-negative pressure.
Fig. 2 is the schematic drawing of Y driving circuit.Among the figure, the formation circuit during the initialization is made up of the circuit c that forms that forms circuit b and oblique wave negative edge of oblique wave rising edge.The formation circuit of address period be by the 1st plateau voltage Yp form circuit d, negative pressure-Vy form circuit g and scanning chip e forms.Formation circuit during keeping is made up of energy recovery circuit a.
Energy recovery circuit a is made up of electric capacity c1, inductance L, the 1st field effect transistor to the 4 field effect transistor Q1, Q2, Q3, Q4 connection in series-parallel, electric capacity c1 one end is connected with ground, the other end is connected with the source electrode of the 2nd an effect pipe Q2 with the drain electrode of the 1st field effect transistor Q1, the drain electrode of the source electrode of the 1st field effect transistor Q1, the 2nd field effect transistor Q2 is connected with inductance L, and the drain electrode of the 4th field effect transistor Q4 is connected the source electrode of the other end of inductance L and the 3rd field effect transistor Q3 and the slope rising edge forms the negative pole of the electric capacity c2 among the circuit b and the source electrode of the 5th field effect transistor Q5 is connected.The formation circuit b of oblique wave rising edge is by electric capacity c2, potentiometer RA1, the 5th field effect transistor to the 7 field effect transistor Q5, Q6, the Q7 connection in series-parallel is formed, the drain electrode of the 5th field effect transistor Q5, the source electrode of the 6th field effect transistor Q6 is connected with the drain electrode of the 7th field effect transistor Q7, the source electrode of the 7th field effect transistor Q7 is connected with virtual earth voltage Yg, the source electrode of electric capacity c3 and the 11st field effect transistor Q11 among the formation circuit d that also has the 1st plateau voltage Yp that links to each other with virtual earth voltage Yg, the drain electrode of the 8th field effect transistor Q8 among the formation circuit c of oblique wave negative edge, the ground end of the drain electrode of the 9th field effect transistor Q9 and scanning chip connects among the formation circuit g of negative pressure-Vy.The oblique wave negative edge forms circuit c and is composed in series by potentiometer RA2 and the 8th field effect transistor Q8.The 1st plateau voltage Yp forms circuit d and is made up of electric capacity c3, the 10th field effect transistor to the 11 field effect transistor Q10, Q11 connection in series-parallel.Scanning chip e is the chip schematic drawing.Virtual earth voltage-Vy forms circuit g and is made up of the 9th field effect transistor Q9.Among the formation circuit d of the 1st plateau voltage Yp, the power end of the drain electrode of the source electrode of the 10th field effect transistor Q10, the 11st field effect transistor Q11 and scanning chip is connected with the 2nd plateau voltage Ypout.
As shown in Figure 3.Y1, Yj are scan pulse voltage among the figure, during a son field is divided into initialization, address period, keep during, its scan pulse voltage value is that the voltage swing by the input scan chip decides.And the magnitude of voltage of input scan chip equals poor between the 2nd plateau voltage Ypout and the virtual earth voltage (Yg).When addressing began, the scan pulse voltage value was identical with Y1, and when scanning to a certain degree, scan pulse voltage is identical with Yi.The drive waveforms figure that the drive waveforms figure that the drive waveforms figure that the X-holding circuit produces, Y-sweep circuit produce, A-addressing circuit produce.Δ V is the voltage difference of scan pulse voltage Y1 and Yj.
Shown in Figure 4 is interior the 2nd plateau voltage Ypout and virtual earth voltage Yg changing condition of address period.Can pass through to increase the magnitude of voltage of the 2nd plateau voltage Ypout rear section, or the magnitude of voltage of reduction virtual earth voltage Yg rear section is realized the scan pulse voltage II method higher than the scan pulse voltage I of forward part of rear section.In address period, the 2nd plateau voltage Ypout voltage is by the 10th field effect transistor Q10 conducting, produces after the 11st field effect transistor Q11 disconnects.And virtual earth voltage Yg is the 9th field effect transistor Q9 conducting generation later on.Among Fig. 4, rear section addressing voltage in forward part addressing voltage, the II-address period in the I-address period, Y-are at the voltage distribution plan of address period sweep circuit.
Fig. 5 realizes that the Y drive waveforms that reduces negative pressure-Vy forms circuit diagram.The 1st voltage stabilizing diode Z1 and the 12nd field effect transistor Q12 parallel circuit in the formation circuit g of negative pressure-Vy, have been increased.In address period, for the addressing voltage value in realizing during the I greater than II during in the addressing voltage value, the 12nd field effect transistor Q12 conducting in during I, and the 9th field effect transistor Q9 disconnects, virtual earth voltage Yg value equals magnitude of voltage and the 1st voltage stabilizing diode Z1 magnitude of voltage addition of negative pressure-Vy, and this moment, virtual earth voltage Yg absolute voltage value was less than negative pressure-Vy absolute voltage value; The 9th field effect transistor Q9 conducting in during II, the 12nd field effect transistor Q12 disconnects, and this moment, virtual earth voltage Yg magnitude of voltage equaled negative pressure-Vy magnitude of voltage.
Because the variation of the virtual earth voltage Yg value of input scan chip e, the scan pulse voltage of exporting in scanning chip e also can change, in Fig. 3.The size of Δ V is exactly the voltage swing that equals the 1st voltage stabilizing diode Z1.By the magnitude of voltage of adjusting the 1st voltage stabilizing diode Z1 is the Δ V voltage swing that can adjust address period.Finally reach the optimum value of the Δ V among Fig. 3.Like this, can reduce the plateau voltage between the Y electrode of the first half, can improve the voltage remaining, and can reduce power consumption.
Fig. 6 realizes that the Y drive waveforms that increases the 2nd plateau voltage Ypout forms circuit diagram.The 2nd voltage stabilizing diode Z2 and the 13rd field effect transistor Q13 parallel circuit in the formation circuit d of the 1st plateau voltage Yp, have been increased.In address period, for the addressing voltage value in realizing during the I less than II during in the addressing voltage value, the 13rd field effect transistor Q13 conducting in during I, and the 9th field effect transistor Q9 disconnects, the 2nd plateau voltage Ypout value equals the 1st plateau voltage Yp value and deducts the 2nd voltage stabilizing diode Z2 magnitude of voltage, and this moment, the 2nd plateau voltage Ypout value was less than the 1st plateau voltage Yp value; The 9th field effect transistor Q9 conducting in during II, the 13rd field effect transistor Q13 turn-offs, and this moment, the 2nd plateau voltage Ypout value equaled the 1st plateau voltage Yp value.
Because the variation of the 2nd plateau voltage Ypout magnitude of voltage of scanning chip e, the scan pulse voltage of exporting in scanning chip e also can change, as Fig. 3.The size of Δ V is exactly the voltage swing that equals voltage stabilizing diode.Magnitude of voltage by the adjustment voltage stabilizing diode is the Δ V voltage swing that can adjust address period.
Claims (1)
1, improves the method for scan pulse voltage to reduce power consumption, comprise: each son field is divided into during the initialization, address period, during keeping, the formation circuit during the initialization is made up of the circuit (c) that forms that forms circuit (b) and oblique wave negative edge of oblique wave rising edge; The formation circuit of address period be by the 1st plateau voltage (Yp) form circuit (d), negative pressure (Vy) form circuit (g) and scanning chip (e) forms; Scan pulse voltage is the poor of the 2nd plateau voltage (Ypout) and virtual earth voltage (Yg), and the formation circuit during keeping is made up of energy recovery circuit (a);
It is characterized in that, follow these steps to carry out:
1) scan pulse voltage in the address period is divided into I, II two parts: the scan pulse voltage II of rear section is than the scan pulse voltage I height of forward part;
2) negative pressure (has increased the 1st voltage stabilizing diode (Z1) and the 12nd field effect transistor (Q12) parallel circuit in the formation circuit (g) Vy), the anode of its 1st voltage stabilizing diode (Z1) connects virtual earth voltage (Yg), negative electrode connects the drain electrode of the 12nd field effect transistor (Q12), the grid connection control signal of the 12nd field effect transistor (Q12), the source electrode of the 12nd field effect transistor (Q12) connects negative pressure (Vy); The drain electrode of the 9th field effect transistor (Q9) connects virtual earth voltage (Yg), the grid connection control signal of the 9th field effect transistor (Q9), and the source electrode of the 9th field effect transistor (Q9) connects negative pressure (Vy);
The 2nd voltage stabilizing diode (Z2) and the 13rd field effect transistor (Q13) parallel circuit in the formation circuit (d) of the 1st plateau voltage (Yp), have been increased, the anode of its 2nd voltage stabilizing diode (Z2) connects the 1st plateau voltage (Yp), negative electrode connects the drain electrode of the 13rd field effect transistor (Q13), the grid connection control signal of the 13rd field effect transistor (Q13), the source electrode of the 13rd field effect transistor (Q13) connects the 2nd plateau voltage (Ypout); The drain electrode of the 10th field effect transistor (Q10) connects the 1st plateau voltage (Yp), the grid connection control signal of the 10th field effect transistor (Q10), and the source electrode of field effect transistor (Q10) connects the 2nd plateau voltage (Ypout);
3) in address period, the forward part addressing voltage value of address period is less than the addressing voltage value of rear section, the 12nd field effect transistor (Q12) conducting when the forward part of address period, and the 9th field effect transistor (Q9) disconnects, virtual earth voltage (Yg) value equal negative pressure (magnitude of voltage Vy) and the addition of the 1st voltage stabilizing diode (Z1) magnitude of voltage, this moment, virtual earth voltage (Yg) absolute voltage value was less than negative pressure (Vy) absolute value; In the rear section of address period the 9th field effect transistor (Q9) conducting, the 12nd field effect transistor (Q12) is turn-offed, and this moment, virtual earth voltage (Yg) value equaled negative pressure (Vy) value;
4) in address period, the forward part addressing voltage value of address period is less than the addressing voltage value of rear section, the 13rd field effect transistor (Q13) conducting when the forward part of address period, and the 10th field effect transistor (Q10) disconnects, the 2nd plateau voltage (Ypout) value equals the 1st plateau voltage (Yp) value and deducts the 2nd voltage stabilizing diode (Z2) magnitude of voltage, and the 2nd plateau voltage this moment (Ypout) value is worth less than the 1st plateau voltage (Yp); The 10th field effect transistor (Q10) conducting when the rear section of address period, the 13rd field effect transistor (Q13) is turn-offed, and this moment, the 2nd plateau voltage (Ypout) value equaled the 1st plateau voltage (Yp) value;
5) the scan pulse voltage value is that voltage swing by the input scan chip decides, and the magnitude of voltage of input scan chip equals the poor of the 2nd plateau voltage (Ypout) and virtual earth voltage (Yg), be worth by the 2nd plateau voltage (Ypout) that increases the address period rear section, or virtual earth voltage (Yg) value of reduction address period rear section realizes the scan pulse voltage value function higher than the scan pulse voltage value of address period forward part of address period rear section.
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| CNB2005100961692A CN100447837C (en) | 2005-10-14 | 2005-10-14 | Method for improving scan pulse voltage to reduce power consumption |
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| CNB2005100961692A CN100447837C (en) | 2005-10-14 | 2005-10-14 | Method for improving scan pulse voltage to reduce power consumption |
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| CN1750086A CN1750086A (en) | 2006-03-22 |
| CN100447837C true CN100447837C (en) | 2008-12-31 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103761940A (en) * | 2014-01-07 | 2014-04-30 | 无锡芯朋微电子股份有限公司 | Low-power-consumption high-voltage driving circuit shared by output pipes |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011000201A1 (en) * | 2009-06-30 | 2011-01-06 | 四川虹欧显示器件有限公司 | Y driving circuit |
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| WO2005010856A1 (en) * | 2003-07-24 | 2005-02-03 | Lg Electronics Inc. | Apparatus and method of driving plasma display panel |
| EP1511000A2 (en) * | 2003-08-27 | 2005-03-02 | Lg Electronics Inc. | Method and apparatus for driving plasma display panel |
| CN1588512A (en) * | 2004-10-14 | 2005-03-02 | 东南大学 | High voltage scan maintaniing driving circuit and its driving method for groove plasma dsiplay plate |
| CN1609920A (en) * | 2003-10-24 | 2005-04-27 | 三星Sdi株式会社 | Plasma display and plasma display panel driving method |
| CN1622151A (en) * | 2004-12-20 | 2005-06-01 | 彩虹集团电子股份有限公司 | Drive method for three-electrode surface discharge type plasma display |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005010856A1 (en) * | 2003-07-24 | 2005-02-03 | Lg Electronics Inc. | Apparatus and method of driving plasma display panel |
| EP1511000A2 (en) * | 2003-08-27 | 2005-03-02 | Lg Electronics Inc. | Method and apparatus for driving plasma display panel |
| CN1609920A (en) * | 2003-10-24 | 2005-04-27 | 三星Sdi株式会社 | Plasma display and plasma display panel driving method |
| CN1588512A (en) * | 2004-10-14 | 2005-03-02 | 东南大学 | High voltage scan maintaniing driving circuit and its driving method for groove plasma dsiplay plate |
| CN1622151A (en) * | 2004-12-20 | 2005-06-01 | 彩虹集团电子股份有限公司 | Drive method for three-electrode surface discharge type plasma display |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103761940A (en) * | 2014-01-07 | 2014-04-30 | 无锡芯朋微电子股份有限公司 | Low-power-consumption high-voltage driving circuit shared by output pipes |
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