CN100446578C - A Multi-Channel Advanced Data Link Controller - Google Patents

Abstract

The multi-channel HDLC controller of the present invention is used to realize the docking of the multi-channel HDLC and the system, organize the data in a multi-channel HDLC mode, and then transmit the data through the time-division multiplexing interface, and at the same time communicate with the system using the HDLC controller through the AHB bus interface The memory is connected. In the present invention, some temporary parameters required by the HDLC controller are placed outside the HDLC controller, and these parameters are called from the outside through the internal logic. The present invention adopts non-RISC design, full circuit realization, does not need to adopt common RISC, and sets special interface for HDLC, and design difficulty is little; Hardware resources of the multi-channel HDLC controller itself. In addition, for data transmission or reception of multiple channels in a multi-channel HDLC controller, all channels of a multi-channel HDLC controller share a set of control logic, which also saves a lot of hardware resources.

Description

A Multi-Channel Advanced Data Link Controller

technical field

The invention relates to the field of T1/E1 communication, in particular to a multi-channel high-level data link (HDLC) controller.

Background technique

In the prior art, controllers using multi-channel HDLC mainly include the following two types.

A kind of is the multi-channel HDLC controller that model is Conexant CN8472/8474, and it adopts non-RISC (reduced instruction set computer structure), full circuit realization, has 128 channels altogether, and this 128-channel HDLC is processed by the serial port interface, bit (bit) Level processing, interrupt processing controller, DMA controller, PCI (peripheral component expansion interface) bus interface.

But there are following two problems in this multi-channel HDLC controller: first, need a large amount of hardware resources to be used for depositing temporary parameter, need a lot of temporary parameter in the working process of controller, comprise: each passway receives temporary cyclic redundancy Remaining check code CRC (32 bits), receiving temporary buffer pointer of each channel (32 bits), available length of receiving temporary buffer of each channel (14 bits), sending temporary cyclic redundancy check of each channel Code CRC (32 bits), the sending temporary buffer pointer (32 bits) of each channel, and the available length (14 bits) of the sending temporary buffer of each channel; then for 128 such channels, the hardware needs to have ( 32+32+14+32+32+14) multiplied by 128 (number of channels) RAM to store these temporary parameters. The above are the temporary parameters necessary for the HDLC controller to work. If you want to improve the performance of the HDLC controller, each channel needs to store more temporary parameters, which will consume a lot of hardware resources. Secondly, ping-pong FIFO is used inside the HDLC controller to realize data transfer, and its receiving FIFO and sending FIFO are shown in Fig. 1 and Fig. 2 . Its FIFO is divided into two RAM structures with equal space. The data is first written to one of the RAMs. After it is full, it is switched to another RAM structure for operation. At the same time, an interrupt is generated to the DMA controller. The DMA controller will to retrieve its data. After one end of such a ping-pong FIFO is occupied by the write data port, the read data port can only access the other half of the FIFO, or wait for the port to be released before accessing, thereby resulting in a waste of resources.

The second is the MPC8260 communication processor produced by Motorola, USA. As shown in Figure 3, there are two 128-channel HDLC communication interfaces inside. The disadvantage of this solution is that its multi-channel HDLC cannot operate independently. There is a RISC to realize the configuration and control of multi-channel HDLC, data organization and data scheduling, and control other peripherals, so as to realize the same function as Conexant CN8472/8474 multi-channel HDLC controller. Therefore, the communication processor requires a RISC module on the hardware, and the module has a corresponding interface connected with multi-channel HDLC and other peripherals to facilitate the control of the RISC module; at the same time, it is also necessary to write code for the RISC module. Such a design is more complicated and requires a longer design cycle.

Contents of the invention

The technical problem to be solved by the present invention is to provide a multi-channel advanced data link controller, which solves the shortcomings of large hardware resource consumption, insufficient use of FIFO resources and high difficulty in implementation in the prior art, and uses external resources to realize internal calculations. .

The multi-channel advanced data link controller of the present invention includes a time division multiplexing data receiving processing module, a receiving channel processor, a receiving monitor, a receiving buffer, a receiving engine, a sending engine, a sending buffer, a sending monitor, a sending Channel processor, time-division multiplexing data transmission processing module and AHB bus interface; wherein

The time-division multiplexing data receiving and processing module is used to receive data from the serial interface, and convert it into 8-bit parallel data, and output it to the receiving channel processor;

The receiving channel processor is used to use the channel number as the serial number to remove the zero inserted in the received data and output it to the receiving monitor;

The receiving monitor is used to store data in the receiving buffer according to the channel number, monitor the capacity of the receiving buffer at the same time, and send a data request to the receiving engine;

The receiving buffer is used to temporarily store the received data;

The receiving engine is used to perform cyclic redundancy check processing on the data, read and write the buffer descriptor, and perform data transmission according to the requirements of the buffer descriptor, and then write the corresponding interrupt into the memory;

The sending engine is used to perform read and write operations on the buffer descriptor, and perform data transmission according to the requirements of the buffer descriptor, and perform cyclic redundancy check processing at the same time, and then write the corresponding interrupt into the memory;

The sending buffer is used to temporarily store sending data;

The transmission monitor is configured to read data from the transmission buffer and transmit it to the transmission channel processor according to the application of the transmission channel processor, and send data to the transmission channel processor according to the capacity of the transmission buffer. Send engine application data as described above;

The sending channel processor is used to perform zero-insertion operation on the data transmitted by the sending monitor with the channel as the number;

The time-division multiplexing data transmission processing module is used to read the channel number from the time slot number, and read the channel data according to the channel number, and convert 8-bit parallel data into serial data output;

The AHB bus interface is connected with the receiving engine and the sending engine, and is used to convert the behavior of the internal bus to the behavior of the AHB bus.

The present invention adopts non-RISC design, full circuit realization, does not need to adopt common RISC, and sets special interface for HDLC, and design difficulty is little; The hardware resources of the multi-channel HDLC controller itself, the saved hardware resources are ((32+32+14) (the number of bits in the sending part)+(32+32+14) (the number of bits in the receiving part))*128 (channel Number); at the same time, the system only needs to allocate a memory space when the multi-channel HDLC controller is used. If the system does not use the multi-channel HDLC controller, or does not need to use the multi-channel HDLC controller for a period of time, then this memory Resources can be released for other uses. In addition, for data transmission or reception of multiple channels in a multi-channel HDLC controller, not each channel adopts a set of control logic, but all channels of a multi-channel HDLC controller share a set of control logic, because in any At this point in time, only one channel is working, so each channel does not need to implement a set of control logic, which also saves a lot of hardware resources. In the present invention, the receiving buffer and the sending buffer adopt a FIFO structure, and the read and write operations can run simultaneously. In addition, the space size of the FIFO is dynamically allocated, that is, allocated according to the number of T1/E1 time slots actually occupied by each channel The size of the FIFO space, such as channels that occupy a large number of time slots, allocate more FIFO space, and channels that occupy a small number of time slots allocate less FIFO space.

Description of drawings

Fig. 1 is the schematic diagram of the receiving FIFO of Conexant CN8472/8474 multi-channel HDLC controller in the prior art;

Fig. 2 is the schematic diagram of sending FIFO of Conexant CN8472/8474 multi-channel HDLC controller in the prior art;

Fig. 3 is the multi-channel HDLC structural representation of Motorola MPC8260 in the prior art;

Fig. 4 is a schematic structural diagram of the multi-channel HDLC controller of the present invention.

Detailed ways

The technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

FIG. 1 to FIG. 3 show solutions of multi-channel HDLC controllers in the prior art, which have been introduced in the background technology section and will not be repeated here.

The multi-channel HDLC controller of the present invention organizes data in a multi-channel HDLC mode, then transmits data through a time-division multiplexing (TDM) interface, and simultaneously connects with the system memory using the HDLC controller through an AHB (AMBA) bus interface, in the present invention In , part of the temporary parameters required for HDLC controller work are placed outside the HDLC controller, and these parameters are called from the outside through internal logic.

As shown in Figure 4, the multi-channel HDLC controller of the present invention includes: time division multiplexing data receiving processing module, receiving channel processor, receiving monitor, receiving buffer, receiving engine, sending engine, sending buffer, sending monitor, A sending channel processor, a time division multiplexing data sending processing module and an AHB bus interface. The following introduces the various components of the multi-channel HDLC controller from two aspects of receiving data and sending data.

Receive data:

After the time-division multiplexing data receiving and processing module receives data from the TDM serial interface, since the subsequent data processing is in units of bytes, it is necessary to convert the data from serial data to 8-bit parallel data and output it to the receiving channel processor . In addition, TDM is numbered by time slots, and subsequent processing is numbered by channel numbers. Therefore, it is also necessary to separate TDM processing from subsequent processing by channel numbers.

After receiving the parallel data transmitted by the time-division multiplexing receiving processing module, the receiving channel processor uses the channel number as the serial number to process the data. Although these parallel data are in units of bytes, zero-insertion operations have actually been performed, so the receiving channel processor needs to remove the zeros inserted in the data, so that subsequent functional modules can actually operate on bytes as the smallest unit . The divided-by-zero data is passed to the receive monitor.

The receiving monitor stores the received data in the receiving buffer according to the channel, and monitors the capacity of the receiving buffer. When it reaches the threshold value, it generates a corresponding data transmission application to the receiving engine. The threshold value is generally 4 bytes or 16 bytes or a frame of data. In order to improve the utilization rate of the bus, the data is generally accumulated to a word (4 bytes) before being sent out.

The receiving buffer temporarily stores the data transmitted by the receiving monitor, and accumulates more than 4 bytes of data for the receiving engine. The capacity of this buffer is dynamically allocable and can be adjusted according to actual conditions. In practice, the buffer can be implemented using FIFO.

In order to save the hardware resources of the HDLC controller, some information required by the HDLC controller can be stored in the memory, such as the temporary receiving cyclic redundancy check code CRC (32 bits), the temporary pointer of the receiving buffer (32 bits), the receiving The temporary available length of the buffer (14 bits) and some control status information of the channel.

After the receiving engine receives the data request from the receiving monitor, it operates in two stages:

If the receiving engine finds that the received data is the beginning of a frame, or there is no valid buffer descriptor (buffer descriptor, referred to as BD) at that time, the receiving engine reads the BD from the specified channel BD table of the memory through the AHB bus interface, Get the parameters on the BD, start to move the data according to the address given by the BD, and confirm whether the length of the BD is enough to hold the data transferred this time: if the BD is not enough or just meets the operation, or the BD length exceeds the data transfer for this time However, during the data transmission, it is found that there is an end-of-frame information in the data, then after the data transmission is completed, the status is written back, and the BD is closed at the same time; if the BD length exceeds the value of this data transmission, and there is no If there is an end-of-frame information in the data, after the data transmission is completed, save the current CRC value in the specified channel (temporary) parameter table as a temporary CRC (32 bits), and save the current address in the specified channel (temporary) The parameter table is used as the receiving buffer temporary pointer (32 bits), and the data length that can be transmitted at that time is stored in the specified channel (temporary) parameter table as the receiving buffer temporary available length (14 bits), and other parameters . Then exit this channel operation.

If the received data is not the beginning of a frame, and the BD at that time has not been used up, the receiving engine reads the receiving temporary CRC (32 bits) from the specified channel (temporary) parameter table of the memory through the AHB bus interface (receiving The engine will be used as the initial value of the CRC for CRC operation), the temporary pointer of the receiving buffer (32 bits) (the receiving engine uses this pointer as the starting point of the address to carry out data transfer), the temporary available length of the receiving buffer (14 bits) (The receiving engine is used for length control) and other control information, and then start to perform CRC processing on the data transmitted from the receiving buffer, and carry out data transfer at the same time, and confirm whether the length of this BD is enough to hold the amount of data transmitted this time: If The length of the BD is not enough or just enough, or the length of the BD exceeds the amount of data transmission this time, but it is found that there is an end of frame information in the data during the data transmission, then after the data transmission is completed, write the status back to the BD, and close the BD at the same time , if the BD length exceeds the value of this data transmission, and there is no information about the end of a frame in the data during data transmission, then after the data transmission is completed, save the current CRC value in the specified channel (temporary) parameter table As a temporary CRC (32 bits), store the address at that time in the specified channel (temporary) parameter table as a temporary pointer (32 bits) of the receiving buffer, and store the current data length that can still be transmitted in the specified channel (temporary) parameter The temporary available length (14 bits) of the receive buffer in the table, and other parameters. Then exit the operation of this channel.

The AHB bus interface is used as the connection port between the multi-channel HDLC controller and the AHB bus to realize the conversion of the HDLC internal bus behavior to the standard AHB bus behavior.

send data:

After the sending engine receives the application from the sending monitor, it will also have two stages of operation, which is similar to receiving, except that the flow of data is opposite to receiving. Also in order to save the hardware resources of the HDLC controller, the HDLC controller works Part of the required information is stored in the memory, such as the cyclic redundancy check code CRC (32 bits), the temporary pointer of the sending buffer (32 bits), the temporary available length of the sending buffer (14 bits), and some channel information. Control status information, after each BD operation ends, the corresponding frame information will be returned to the BD.

Since the sending engine transmits batch data at one time, and the sending channel only requires to read one byte at a time, it is necessary to temporarily store the batch data transmitted by the sending engine. The sending buffer provides this temporary storage space, so the operation can be Make the bus more efficient. The sending buffer is realized by FIFO, and its capacity is dynamically distributable and can be adjusted according to the actual situation.

According to the data application of the sending channel processor, the sending monitor reads the data from the sending buffer and sends it to the sending channel processor; and according to the free amount of the sending buffer at that time, applies for data to the sending engine, and the condition of the application is that the channel It is in the enabled state, and the send buffer corresponds to this channel with 4 bytes or more than 16 bytes free.

The sending channel processor takes the channel as the number and processes the data transmitted from the sending monitor. The data sent by the sending monitor is in units of bytes, but it is not the final data format, and zero insertion is required before sending the data.

The time-division multiplexing data transmission processing module obtains data from the transmission channel processor, and then converts the data into serial data for transmission. Since the previous data processing is in units of bytes, it is necessary to convert the data from 8-bit parallel data to serial data. Data, similar to reception, TDM is numbered by time slot, and subsequent processing is numbered by channel number, so it is also necessary to separate the time division multiplexing data transmission processing module from other modules with channel number.

For the present invention, one multi-channel HDLC controller can support 32 channels, and four multi-channel HDLC controllers can support a total of 128 channels.

The multi-channel HDLC controller of the present invention can be used as a part of the communication module of the SOC chip to realize the connection between the multi-channel HDLC and the system, and supports the BD mode, and can actively transmit data to the memory space specified by the user. The multi-channel HDLC controller must have an independent AHB slave port, which can be regarded as a part of the AHB bus interface, and is used for the system to configure the HDLC controller. At the same time, the multi-channel HDLC controller must also be an AHB Master, which can be viewed as As a part of the AHB bus interface, it can actively transmit data according to the requirements of the BD, and mark the status of this frame of data on the BD after the data transmission is completed.

The multi-channel HDLC controller adopts the standard AHB bus interface, which is the most common in SOC chips, which makes the HDLC controller a standard module and can be easily transplanted to other SOC chips.

The SOC chip is actually a multi-layer AHB bus system. At the same time, as long as different AHBMasters access different AHB Slave spaces, the operation of each AHB Master will not be affected; at the same time, there are multiple memory spaces in the SOC chip, of which SRAM space and SDRAM space can be used to store information about the operation of the HDLC controller.

The SRAM space is relatively small and supports BURST operation. Reading and writing data from the SRAM space can return a 32-bit data per clock, which provides a feasible material basis for storing some temporary parameters in the memory. Therefore, some temporary parameters required for the operation of each channel are stored in the SRAM space. In, for example, each channel’s receiving temporary CRC (32 bits), sending temporary CRC (32 bits), receiving buffer temporary pointer (32 bits), sending buffer temporary pointer (32 bits), receiving buffer temporary available length ( 14 bits), send buffer temporary available length (14 bits) and other information. The capacity of the SDRAM space is larger than that of the SRAM space, and is used to store the BD table of each channel and the buffer pointed to by the BD table.

For the multi-channel HDLC controller, it is actually unknown which area is the high-speed memory space and which area is the medium-speed large-capacity space. Some temporary parameters, BD table and the buffer pointed to are placed in the same memory space. But from the perspective of optimizing the process, it is best to store some temporary parameters needed for operation in the high-speed memory space, and store the BD table and buffer data of each channel in the medium-speed large-capacity memory space.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be Modifications or equivalent replacements of the technical solutions without departing from the spirit and scope of the technical solutions of the present invention shall be covered by the scope of the claims of the present invention.

Claims (8)

1. A multi-channel advanced data link controller is characterized in that it includes a time division multiplexing data receiving processing module, a receiving channel processor, a receiving monitor, a receiving buffer, a receiving engine, a sending engine, a sending buffer, a sending A monitor, a sending channel processor, a time-division multiplexing data sending processing module, and an AHB bus interface; where The time-division multiplexing data receiving and processing module is used to receive data from the serial interface, and convert it into 8-bit parallel data, and output it to the receiving channel processor; The receiving channel processor is used to use the channel number as the serial number to remove the zero inserted in the received data and output it to the receiving monitor; The receiving monitor is used to store data in the receiving buffer according to the channel number, monitor the capacity of the receiving buffer, and send a data request to the receiving engine; the receiving buffer is used to temporarily store received data; The receiving engine is used to perform cyclic redundancy check processing on the data, read and write the buffer descriptor, and perform data transmission according to the requirements of the buffer descriptor, and then write the corresponding interrupt into the memory; The sending engine is used to read and write the buffer descriptor, and perform data transmission according to the requirements of the buffer descriptor, and perform cyclic redundancy check processing at the same time, and then write the corresponding interrupt into the memory; The sending buffer is used to temporarily store the sending data; The transmission monitor is configured to read data from the transmission buffer and transmit it to the transmission channel processor according to the application of the transmission channel processor, and send data to the transmission channel processor according to the capacity of the transmission buffer. Send engine application data as described above; The sending channel processor is used to perform a zero-insertion operation on the data transmitted by the sending monitor with the channel as the number; The time-division multiplexing data transmission processing module is used to read the channel number from the time slot number, and read the channel data according to the channel number, and convert 8-bit parallel data into serial data output; The AHB bus interface is connected with the receiving engine and the sending engine, and is used to convert the behavior of the internal bus to the behavior of the AHB bus. 2. The multi-channel advanced data link controller according to claim 1, wherein the receiving monitor monitors that the capacity of the receiving buffer reaches a threshold value, and then sends a data request to the receiving engine. 3. The multi-channel advanced data link controller according to claim 2, wherein the threshold value is 4 bytes or 16 bytes or a frame of data. 4. The multi-channel advanced data link controller according to claim 1, wherein the condition for the transmission monitor to apply for data to the transmission engine is that the channel is in an enabled state, and the transmission buffer 4 bytes or more than 16 bytes are free for this channel. 5. The multi-channel advanced data link controller according to claim 1, characterized in that, the temporary parameters required for the operation of each channel, the buffer descriptor table and the buffer descriptor table of each channel are stored in the memory space. The buffer data pointed to by the region descriptor table. 6. The multi-channel advanced data link controller according to claim 5, wherein the temporary parameters required for the operation of each channel are stored in a high-speed memory space, and the buffer descriptor table of each channel And the buffered data is stored in the medium-speed large-capacity memory space. 7. The multi-channel advanced data link controller according to claim 1, wherein the receiving engine receives the data application from the receiving monitor or the sending engine receives the data from the sending monitor. After the application, it is necessary to read the temporary parameters and the buffer descriptor table from the memory through the AHB bus interface. 8. The multi-channel advanced data link controller according to claim 1, wherein the receiving buffer/transmitting buffer is implemented by a first-in-first-out buffer, and its capacity is dynamically allocable.

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