CN100442645C

CN100442645C - Method and device for measuring reflected voltage of transformer

Info

Publication number: CN100442645C
Application number: CNB2005101318050A
Authority: CN
Inventors: 杨大勇
Original assignee: System General Corp Taiwan
Current assignee: Fairchild Taiwan Corp
Priority date: 2005-12-15
Filing date: 2005-12-15
Publication date: 2008-12-10
Anticipated expiration: 2025-12-15
Also published as: CN1983783A

Abstract

The invention provides a method and a device for sampling a reflected voltage signal of a transformer. A plurality of sampling signals are used to generate a plurality of holding voltages by sequentially sampling the reflected voltage of the transformer. The buffer circuit generates a buffer signal from a higher voltage of the plurality of holding voltages. The sampling switch periodically transmits the buffer signal according to the output of the buffer circuit to generate a feedback signal. The feedback signal is proportional to the output voltage of the transformer. The reflected voltage signal is added to a threshold signal to generate a level shifted signal. Once the switching signal is disabled, the discharge-time signal is enabled. The discharge-time signal is disabled once the level-shift signal is lower than the output of the buffer circuit. The pulse width of the discharge-time signal is related to the discharge time of the transformer. When the discharge-time signal is enabled, the plurality of sampling signals are enabled to generate a plurality of holding voltages.

Description

Method and device for measuring reflected voltage of transformer

技术领域 technical field

本发明涉及一种电源转换器的控制电路，且特别涉及一种切换模式电源转换器的切换控制电路。The invention relates to a control circuit of a power converter, and in particular to a switching control circuit of a switching mode power converter.

背景技术 Background technique

电源转换器已经广泛用来提供稳定的输出电压。为了安全，一个离线的电源转换器必须在初级侧和次级侧之间提供电气的绝缘。并需要光耦合器和次级侧调整器来调节离线的电源转换器的输出电压。为了减少组件的数量和从电源转换器的次级侧去除反馈电路，伦道夫.D·W·谢利(Randolph D.W.Shel1y)在专利号为4,302,803的美国专利“带多路反馈转换器的整流器-转换器电源”中披露过一种初级侧的控制技术。在较新的技术中，则有杨大勇(Ta-yung Yang)等人的6,721,192号美国专利“调节初级侧的输出电压和输出电流的PWM(脉宽调制)控制器”，杨大勇(Ta-yung Yang)等人的6,836,415号美国专利“有改进的载荷调整的初级侧稳定脉宽调制控制器”，杨大勇(Ta-yung Yang)等人的6,853,563号美国专利“初级侧控制反馈电源转换器”，以及杨大勇(Ta-yung Yang)等人的6,862,194号美国专利“初级侧PWM控制下具有恒定电压和恒定电流输出的反馈电源转换器”。然而，为了测量来自变压器的信号，前面的技术不能获得准确的结果。Power converters have been widely used to provide a stable output voltage. For safety, an off-line power converter must provide electrical isolation between the primary and secondary sides. An optocoupler and a secondary-side regulator are required to regulate the output voltage of the off-line power converter. In order to reduce the number of components and remove the feedback circuit from the secondary side of the power converter, Randolph D.W. Shelly (Randolph D.W. Shelly) in U.S. Patent No. 4,302,803 "Rectifier with Multiple Feedback Converter- A primary-side control technique is disclosed in "Converter Power". Among the newer technologies, there is Ta-yung Yang et al. US Patent No. 6,721,192 "PWM (Pulse Width Modulation) Controller for Regulating Output Voltage and Output Current on the Primary Side", Ta-yung Yang (Ta-yung Yang) et al. yung Yang et al., US Patent No. 6,836,415 "Primary Side Stable Pulse Width Modulation Controller with Improved Load Regulation," and Ta-yung Yang et al. ", and US Patent No. 6,862,194 "Fedback Power Converter with Constant Voltage and Constant Current Output Under Primary Side PWM Control" by Ta-yung Yang et al. However, for measuring the signal from the transformer, the previous techniques cannot obtain accurate results.

发明内容 Contents of the invention

本发明的目的就是要为电源转换器的切换控制电路提供用以测量反射电压信号和变压器的放电时间的精确取样电路。经由使用取样自变压器的信号，可以不使用光耦合器和次级侧调整器而能够调节电源转换器的输出。除此之外，变压器的放电时间能够用于准谐振电源转换器，以跟低谷电压同步和达到柔性切换的效果。The object of the present invention is to provide an accurate sampling circuit for measuring the reflected voltage signal and the discharge time of the transformer for the switching control circuit of the power converter. By using a signal sampled from the transformer, the output of the power converter can be regulated without the use of optocouplers and secondary side regulators. In addition, the discharge time of the transformer can be used in the quasi-resonant power converter to synchronize with the valley voltage and achieve the effect of flexible switching.

多次取样电路耦接并从变压器线圈接收反射电压信号。多次取样电路包括信号产生器，其目的是接收切换信号和反射电压信号，用以产生放电时间信号和多个取样信号。当切换信号禁用时，多个取样信号顺序产生，其中上述多个取样信号用V_SP1...V_SPN来表示，其中N为大于或者等于2的整数，其中首先生成取样信号V_SPN，......，最后才生成取样信号V_SP1。切换信号经由开关切换变压器，即上述切换信号用于导通或者关闭上述开关，当导通上述开关时，在上述变压器的初级侧产生初级侧切换电流，当关闭上述开关时，在上述变压器的次级侧产生次级侧切换电流，从而调节变压器的输出。取样保持电路包括多个保持电容器以及缓冲电路，其中所述取样保持电路接收多个取样信号，以对反射电压信号进行取样。被多个取样信号多次取样的反射电压信号分别被储存在多个保持电容器中。因此，多个保持电容器根据多个取样信号的取样操作以产生多个保持电压。缓冲电路与多个保持电容器相耦接，根据多个保持电压的最高电压，产生缓冲信号。比较电路透过比较缓冲信号和电平位移信号来产生停止信号。电平位移信号的产生是经由反射电压信号加上门限信号。一旦电平位移信号低于缓冲信号，停止信号便启用。A multi-sampling circuit is coupled to receive the reflected voltage signal from the transformer coil. The multi-sampling circuit includes a signal generator whose purpose is to receive switching signals and reflected voltage signals to generate discharge time signals and multiple sampling signals. When the switching signal is disabled, a plurality of sampling signals are generated sequentially, wherein the above-mentioned plurality of sampling signals are represented by V _SP1 ...V _SPN , where N is an integer greater than or equal to 2, wherein the sampling signals V _SPN are generated first, .. ..., the sampling signal V _SP1 is generated at last. The switching signal switches the transformer through the switch, that is, the switching signal is used to turn on or off the switch. When the switch is turned on, a primary side switching current is generated on the primary side of the transformer. When the switch is turned off, the secondary side of the transformer is The primary side generates the secondary side switching current, which regulates the output of the transformer. The sample and hold circuit includes a plurality of holding capacitors and a buffer circuit, wherein the sample and hold circuit receives a plurality of sampling signals to sample the reflected voltage signal. Reflected voltage signals sampled a plurality of times by the plurality of sampling signals are respectively stored in a plurality of holding capacitors. Accordingly, a plurality of holding capacitors operates according to sampling of a plurality of sampling signals to generate a plurality of holding voltages. The buffer circuit is coupled to the plurality of holding capacitors, and generates a buffer signal according to the highest voltage of the plurality of holding voltages. The comparison circuit generates a stop signal by comparing the buffer signal with the level shift signal. The level-shifted signal is generated by adding a threshold signal to the reflected voltage signal. Once the level-shifted signal is lower than the buffered signal, the stop signal is enabled.

当切换信号禁用时，放电时间信号被启用。当停止信号启用时，放电时间信号被禁用。因此，放电时间信号的启用时间等于变压器的放电时间。另外，在停止信号产生后，反馈信号系根据缓冲信号而产生。停止信号更决定多个取样信号的动作。反馈信号从而与变压器的输出电压成比例。When the toggle signal is disabled, the discharge time signal is enabled. When the stop signal is enabled, the discharge time signal is disabled. Therefore, the enable time of the discharge time signal is equal to the discharge time of the transformer. In addition, after the stop signal is generated, the feedback signal is generated according to the buffer signal. The stop signal further determines the actions of multiple sampling signals. The feedback signal is thus proportional to the output voltage of the transformer.

前面的概要说明和下面的详细说明仅仅是举例性的描述，并且其目的是对权利要求中的发明作进一步的说明。看了后面的说明和附图，更多的目的和优点将更为清楚。The foregoing general description and the following detailed description are exemplary descriptions only and are intended to further explain the invention as claimed. Further purposes and advantages will become clearer after reading the following description and drawings.

附图说明 Description of drawings

附图是用来进一步理解本发明的，与说明书不可分割，是说明书组成的一部分。附图表示了本发明的实施例，与说明书一起用来解释本发明的原理。The accompanying drawings are used to further understand the present invention, and are inseparable from the description, and are a part of the description. The drawings illustrate the embodiments of the invention and together with the description serve to explain the principles of the invention.

图1为切换电路的示意图。Figure 1 is a schematic diagram of a switching circuit.

图2A表示功率开关打开时切换电路的信号流。Figure 2A shows the signal flow of the switching circuit when the power switch is turned on.

图2B表示功率开关关闭时切换电路的信号流。Figure 2B shows the signal flow of the switching circuit when the power switch is turned off.

图2C表示功率开关关闭时切换电路的信号流。FIG. 2C shows the signal flow of the switching circuit when the power switch is turned off.

图3表示每一个切换周期中切换电路的各种波形。Figure 3 shows various waveforms of the switching circuit in each switching cycle.

图4为本发明的多次取样电路的方块图。FIG. 4 is a block diagram of the multi-sampling circuit of the present invention.

图5为根据本发明的一个实施例的多次取样电路。FIG. 5 is a multi-sampling circuit according to an embodiment of the present invention.

图6表示本发明的多次取样电路的主要波形。Fig. 6 shows the main waveforms of the multi-sampling circuit of the present invention.

图7表示根据本发明的一个实施例的脉宽调制遮没单元。Figure 7 shows a pulse width modulation blanking unit according to one embodiment of the present invention.

图8表示根据本发明的一个实施例的振荡单元。Fig. 8 shows an oscillating unit according to an embodiment of the present invention.

具体实施方式 Detailed ways

图1表示切换电路，包括变压器10，其有辅助线圈N_A，初级线圈N_P，和次级线圈N_S。初级线圈N_P耦接至输入电压V_IN。由电阻器51和52构成的分压器连接于辅助线圈N_A，目的是从辅助线圈N_A的电压信号获取反射电压信号V_DET。为了调节切换电路的输出电压V_O和输出电流I_O，切换信号V_PWM经由功率开关，例如晶体管20，以切换变压器10。Figure 1 shows a switching circuit comprising a transformer 10 having an auxiliary winding N _A , a primary winding N _P , and a secondary winding N _S . The primary coil N _P is coupled to the input voltage V _IN . A voltage divider composed of resistors 51 and 52 is connected to the auxiliary winding _NA for the purpose of obtaining a reflected voltage signal V _DET from the voltage signal of the auxiliary winding _NA . In order to adjust the output voltage V _O and the output current I _O of the switching circuit, the switching signal V _PWM passes through a power switch, such as the transistor 20 , to switch the transformer 10 .

参照图1和图2A，当切换信号V_PWM启用(逻辑高电平)，即产生初级侧切换电流I_P，以将能量储存在变压器10中。在这个阶段的切换电路的各种波形显示在图3的周期T₁中。初级侧切换电流I_P的峰值I_P1可由下式给出：Referring to FIG. 1 and FIG. 2A , when the switching signal V _PWM is enabled (logic high level), the primary side switching current I _P is generated to store energy in the transformer 10 . Various waveforms of the switching circuit at this stage are shown in period T1 of FIG. ₃ . The peak value I _P1 of the primary side switching current I _P can be given by:

${I I}_{P P 11} = = \frac{{V V}_{IN IN}}{{L L}_{P P}} \times \times {T T}_{ON ON} - - - - - - ((11))$

这里L_P是变压器10的初级线圈N_P的电感T_ON是切换信号V_PWM的导通时间。Here L _P is the inductance of the primary coil N _P of the transformer 10 and T _ON is the on-time of the switching signal V _PWM .

参照图1和图2B，当切换信号V_PWM禁用(逻辑低电平)，储存在变压器10中的能量释放到变压器10的次级侧，并且经由整流器40释放到切换电路的输出端。从而产生次级侧切换电流I_S。这个阶段的各种波形显示在图3的周期T₂中。次级侧切换电流I_S的峰值I_S1可由下式给出：Referring to FIGS. 1 and 2B , when the switching signal V _PWM is disabled (logic low level), the energy stored in the transformer 10 is released to the secondary side of the transformer 10 and released to the output terminal of the switching circuit via the rectifier 40 . This results in a secondary side switching current I _S . Various waveforms at this stage are shown in period _T2 of Figure 3. The peak value I _S1 of the secondary side switching current I _S can be given by:

${I I}_{S S 11} = = \frac{(({V V}_{O o} + + {V V}_{F f}))}{{L L}_{S S}} \times \times {T T}_{DS DS} - - - - - - ((22))$

这里V_O是切换电路的输出电压；V_F是整流器40的正向压降；L_S是变压器10的次级线圈N_S的电感；T_DS是变压器10的放电时间，其也代表次级侧切换电流Is的放电时间。Here V _O is the output voltage of the switching circuit; V _F is the forward voltage drop of the rectifier 40; L _S is the inductance of the secondary coil _NS of the transformer 10; T _DS is the discharge time of the transformer 10, which also represents the secondary side Discharge time of switching current Is.

同时，在变压器10的辅助线圈N_A上产生电压信号V_AUX。图3中显示的电平V_AUX1可由下式给出：At the same time, a voltage signal V _AUX is generated at the auxiliary winding N _A of the transformer 10 . The level V _AUX1 shown in Figure 3 is given by:

${V V}_{AUX AUX 11} = = \frac{{T T}_{NA NA}}{{T T}_{NS NS}} \times \times (({V V}_{O o} + + {V V}_{F f})) - - - - - - ((33))$

同时，储存在变压器10中的能量将给晶体管20的寄生电容C_J充电，以在晶体管20的寄生电容C_J的两端产生电压V_DS。电压V_DS可由下式给出：At the same time, the energy stored in the transformer 10 will charge the parasitic capacitance C _J of the transistor 20 to generate a voltage V _DS across the parasitic capacitance C _J of the transistor 20 . The voltage V _DS can be given by:

${V V}_{DS DS} = = {V V}_{IN IN} + + [[\frac{{T T}_{NP NP}}{{T T}_{NS NS}} \times \times (({V V}_{O o} + + {V V}_{F f}))]] - - - - - - ((44))$

这里V_IN是切换电路的输入电压；T_NA，T_NP和T_NS分别是变压器10的辅助线圈N_A，初级线圈N_P，和次级线圈N_S的线圈匝数。Here V _IN is the input voltage of the switching circuit; T _NA , T _NP and T _NS are the coil turns of the auxiliary coil _NA , the primary coil _NP , and the secondary coil _NS of the transformer 10, respectively.

参照图1和图2C，当储存在变压器10中的能量被完全释放时，次级侧切换电流I_S下降为零。同时，因为电压V_DS高于输入电压V_IN，电压V_DS开始给输入电压V_IN回充。这个阶段的各种波形显示在图3的周期T₃中。电压V_DS在周期T_Q结束时减少到谷底电压。电压V_DS的减量斜率决定于谐振频率f_R。谐振频率f_R和周期T_Q分别由式(5)和(6)给出：Referring to FIG. 1 and FIG. 2C, when the energy stored in the transformer 10 is fully released, the secondary side switching current I _S drops to zero. At the same time, since the voltage V _DS is higher than the input voltage V _IN , the voltage V _DS starts to recharge the input voltage V _IN . Various waveforms at this stage are shown in period T3 of FIG. ₃ . Voltage V _DS decreases to the valley voltage at the end of period T _Q . The decreasing slope of the voltage V _DS is determined by the resonant frequency f _R . The resonant frequency f _R and period T _Q are given by equations (5) and (6) respectively:

${f f}_{R R} = = \frac{11}{22 π π \sqrt{{L L}_{P P} \times \times {C C}_{JJ JJ}}} - - - - - - ((55))$

${T T}_{Q Q} = = \frac{11}{((44 \times \times {f f}_{R R}))}$

${T T}_{Q Q} = = \frac{π π \sqrt{{L L}_{P P} \times \times {C C}_{JJ JJ}}}{22} - - - - - - ((66))$

这里C_JJ是晶体管20的寄生电容器C_J的电容。Here C _JJ is the capacitance of the parasitic capacitor C _J of the transistor 20 .

当电压V_DS开始下降时，电压信号V_AUX开始减少。电压信号V_AUX跟电压V_DS相关，其可由下式给出：When the voltage V _DS starts to drop, the voltage signal V _AUX starts to decrease. The voltage signal V _AUX is related to the voltage V _DS which can be given by:

${V V}_{AUX AUX} = = \frac{{T T}_{NA NA}}{{T T}_{NP NP}} \times \times (({V V}_{DS DS - -} {V V}_{IN IN})) - - - - - - ((77))$

因此，如图6所示，可以从切换信号V_PWM的下降边到电压信号V_AUX的下降角测出式(2)中的放电时间T_DS。Therefore, as shown in FIG. 6 , the discharge time T _DS in formula (2) can be measured from the falling edge of the switching signal V _PWM to the falling angle of the voltage signal V _AUX .

参照图1，电阻器51和52构成分压器，其连接在变压器10的辅助线圈N_A和接地参考之间，目的是产生反射电压信号V_DET，其可由下式给出：Referring to Figure 1, resistors 51 and 52 form a voltage divider connected between the auxiliary winding N _A of the transformer 10 and a ground reference for the purpose of generating a reflected voltage signal V _DET which can be given by:

${V V}_{DET DET} = = \frac{{R R}_{5252}}{{R R}_{5151} {+ + R R}_{5252}} \times \times {V V}_{AUX AUX} - - - - - - ((88))$

这里R₅₁和R₅₂分别是电阻器51和52的电阻。Here _R51 and _R52 are the resistances of resistors 51 and 52, respectively.

图4为本发明的多次取样电路700。多次取样电路700连接到脉宽调制遮没单元500，振荡单元600，和透过分压器连接到变压器10的辅助线圈N_A。多次取样电路700包括取样单元100，信号产生单元200，和延时单元300。FIG. 4 is a multi-sampling circuit 700 of the present invention. The multi-sampling circuit 700 is connected to the PWM blanking unit 500, the oscillation unit 600, and the auxiliary coil N _A connected to the transformer 10 through a voltage divider. The multiple sampling circuit 700 includes a sampling unit 100 , a signal generating unit 200 , and a delay unit 300 .

进一步参照图4，延时单元300连接于脉宽调制遮没单元500，以接收切换信号V_PWM。延时单元300通过延时单元300的反相器产生反相切换信号/V_PWM。当切换信号V_PWM禁用时，延时单元300产生延时信号V_DL。信号产生单元200连接到延时单元300，以接收延时信号V_DL，反相切换信号/V_PWM和反射电压信号V_DET。信号产生单元200产生放电时间信号S_DS，和多个取样信号V_SPN...V_SP1。取样单元100连接于振荡单元600，脉宽调制遮没单元500，和信号产生单元200，用来接收多个取样信号V_SPN...V_SP1，反射电压信号V_DET，振荡单元600产生的脉冲信号PLS，和脉宽调制遮没单元500产生的消除信号CLR。多个取样信号V_SPN...V_SP1顺序控制取样单元100，以对反射电压信号V_DET进行取样，产生缓冲信号V_HD和电压反馈信号V_V。Further referring to FIG. 4 , the delay unit 300 is connected to the PWM blanking unit 500 to receive the switching signal V _PWM . The delay unit 300 generates an inverted switching signal /V _PWM through an inverter of the delay unit 300 . When the switching signal V _PWM is disabled, the delay unit 300 generates a delay signal V _DL . The signal generation unit 200 is connected to the delay unit 300 to receive the delay signal V _DL , the inverted switching signal /V _PWM and the reflected voltage signal V _DET . The signal generation unit 200 generates a discharge time signal S _DS and a plurality of sampling signals V _SPN . . . V _SP1 . The sampling unit 100 is connected to the oscillating unit 600, the pulse width modulation blanking unit 500, and the signal generating unit 200, and is used to receive multiple sampling signals V _SPN ... V _SP1 , the reflected voltage signal V _DET , and the pulse generated by the oscillating unit 600 signal PLS, and the cancellation signal CLR generated by the PWM blanking unit 500 . A plurality of sampling signals V _SPN . . . V _SP1 sequentially control the sampling unit 100 to sample the reflected voltage signal V _DET to generate a buffer signal V _HD and a voltage feedback signal V _V .

本发明的主要目的是提供测量电压信号和变压器放电时间的精确取样电路。另外，本发明可以不使用光耦合器和次级侧调整器来调节输出。The main object of the present invention is to provide an accurate sampling circuit for measuring the voltage signal and the discharge time of the transformer. In addition, the present invention can regulate the output without the use of optocouplers and secondary side regulators.

请参照图1和图5所示，根据本发明的一个实施例的多次取样电路700如图5所示。在反射电压信号V_DET的多次取样操作期间，产生电压反馈信号V_V和放电时间信号S_DS。电压反馈信号V_V与输出电压V_O成精确比例。放电时间信号S_DS代表次级侧切换电流I_S的放电时间T_DS。在次级侧切换电流I_S下降为零之前，反射电压信号V_DET即被取样和测量。因此，次级侧切换电流I_S的变化不影响整流器40正向压降V_F。Please refer to FIG. 1 and FIG. 5 . A multi-sampling circuit 700 according to an embodiment of the present invention is shown in FIG. 5 . During the multi-sampling operation of the reflected voltage signal V _DET , the voltage feedback signal V _V and the discharge time signal S _DS are generated. The voltage feedback signal V _V is precisely proportional to the output voltage V _O. The discharge time signal S _DS represents the discharge time T _DS of the secondary side switching current I _S . Before the secondary side switching current I _S drops to zero, the reflected voltage signal V _DET is sampled and measured. Therefore, the variation of the secondary side switching current I _S does not affect the forward voltage drop V _F of the rectifier 40 .

信号产生单元200包括第一信号产生器，第二信号产生器，门限信号156，和脉冲产生器190。脉冲产生器190产生取样脉冲信号供多次取样操作。反射电压信号V_DET加上门限信号156以产生电平位移反射信号。第一信号产生器包括计数器171，与门165和与门166以产生多个取样信号V_SPN...V_SP1。第二信号产生器包括D触发器170，与非门163，与门164和比较器155，以产生放电时间信号S_DS。The signal generating unit 200 includes a first signal generator, a second signal generator, a threshold signal 156 , and a pulse generator 190 . The pulse generator 190 generates a sampling pulse signal for multiple sampling operations. The reflected voltage signal V _DET is added to the threshold signal 156 to generate a level-shifted reflected signal. The first signal generator includes a counter 171 , an AND gate 165 and an AND gate 166 to generate a plurality of sampling signals V _SPN . . . V _SP1 . The second signal generator includes a D flip-flop 170 , a NAND gate 163 , an AND gate 164 and a comparator 155 to generate a discharge time signal S _DS .

进一步参阅图5和图6所示，延时单元300包括反相器161，反相器162，电流源180，晶体管181，和电容器182，以当切换信号V_PWM禁用时产生延迟时间T_d。反相器161的输入端输入切换信号V_PWM。反相器161的输出端连接于反相器162的输入端，与门164的第一输入端，和D触发器170的时钟输入端。反相器162的输出控制晶体管181的导通与截止。电容器182跟晶体管181并联。电流源180用来给电容器182充电。因此，电源180的电流和电容器182的电容决定延时单元300的延迟时间T_d。电容器182还产生延时信号V_DL。Referring further to FIG. 5 and FIG. 6 , the delay unit 300 includes an inverter 161 , an inverter 162 , a current source 180 , a transistor 181 , and a capacitor 182 to generate a delay time T _d when the switching signal V _PWM is disabled. The input terminal of the inverter 161 inputs the switching signal V _PWM . The output terminal of the inverter 161 is connected to the input terminal of the inverter 162 , the first input terminal of the AND gate 164 , and the clock input terminal of the D flip-flop 170 . The output of the inverter 162 controls the on and off of the transistor 181 . Capacitor 182 is connected in parallel with transistor 181 . Current source 180 is used to charge capacitor 182 . Therefore, the current of the power supply 180 and the capacitance of the capacitor 182 determine the delay time T _d of the delay unit 300 . Capacitor 182 also generates a delayed signal V _DL .

供给电压V_CC拉升了D触发器170的D端输入。D触发器170的输出端连接与门164的第二输入端。与门164输出放电时间信号S_DS。从而当切换信号V_PWM禁用时，放电时间信号S_DS为启用。与非门163的输出端连接于D触发器170的复位输入端。与非门163的第一输入端连接于电容器182，以接收延时信号V_DL。与非门163的第二输入端连接于比较器155的输出端。电平位移反射信号供给比较器155的负极输入端。比较器155的正极输入端由缓冲信号V_HD所提供。因此，在延迟时间T_d之后，一旦电平位移反射信号低于缓冲信号V_HD，放电时间信号S_DS将为禁用。另外，当切换信号V_PWM启用时，放电时间信号S_DS也为禁用。The supply voltage V _CC pulls up the D terminal input of the D flip-flop 170 . The output terminal of the D flip-flop 170 is connected to the second input terminal of the AND gate 164 . The AND gate 164 outputs a discharge time signal S _DS . Thus, when the switching signal V _PWM is disabled, the discharge time signal S _DS is enabled. The output terminal of the NAND gate 163 is connected to the reset input terminal of the D flip-flop 170 . A first input terminal of the NAND gate 163 is connected to the capacitor 182 to receive the delayed signal V _DL . The second input end of the NAND gate 163 is connected to the output end of the comparator 155 . The level-shifted reflected signal is supplied to the negative input of comparator 155 . The positive input terminal of the comparator 155 is provided by the buffered signal V _HD . Therefore, after the delay time T _d , once the level-shifted reflected signal is lower than the buffered signal V _HD , the discharge time signal S _DS will be disabled. In addition, when the switching signal V _PWM is enabled, the discharge time signal S _DS is also disabled.

取样脉冲信号被送至计数器171的时钟输入端和与门165和166的第三输入端。计数器171的输出端分别连接于与门165和166的第二输入端。与门165和166的第一输入端由所提供放电时间信号S_DS所提供。与门165和166的第四输入端由延时信号V_DL所提供。因此，依据取样脉冲信号多个取样信号V_SPN...V_SP1将顺序产生。另外，于放电时间信号S_DS的启用期，多个取样信号V_SPN...V_SP1将顺序产生。然而，在放电时间信号S_DS的始端插入了延迟时间T_d以阻止多个取样信号V_SPN...V_SP1的产生。这样，在延迟时间T_d，多个取样信号V_SPN...V_SP1将被禁用。The sampling pulse signal is supplied to the clock input terminal of the counter 171 and the third input terminals of the AND gates 165 and 166 . The output terminals of the counter 171 are respectively connected to the second input terminals of the AND gates 165 and 166 . The first input terminals of the AND gates 165 and 166 are provided by the discharge time signal S _DS . The fourth input terminals of the AND gates 165 and 166 are provided by the delayed signal V _DL . Therefore, a plurality of sampling signals V _SPN . . . V _SP1 will be sequentially generated according to the sampling pulse signal. In addition, during the enabling period of the discharge time signal S _DS , a plurality of sampling signals V _SPN . . . V _SP1 will be sequentially generated. However, a delay time T _d is inserted at the beginning of the discharge time signal S _DS to prevent a plurality of sampling signals V _SPN . . . V _SP1 from being generated. Thus, during the delay time T _d , the plurality of sampling signals V _SPN . . . V _SP1 will be disabled.

多个取样信号V_SPN...V_SP1从而用来对反射电压信号V_DET进行取样。多个取样信号V_SPN...V_SP1控制开关例如121...122以分别于多个保持电容器例如110...111上获取多个保持电压。为了给保持电容器110放电，开关123跟保持电容器110并联。为了给保持电容器111放电，开关124跟保持电容器111并联。A plurality of sampling signals V _SPN . . . V _SP1 are thus used to sample the reflected voltage signal V _DET . A plurality of sampling signals V _SPN . . . V _SP1 control switches such as 121 . In order to discharge the holding capacitor 110 , a switch 123 is connected in parallel with the holding capacitor 110 . In order to discharge the holding capacitor 111 , a switch 124 is connected in parallel with the holding capacitor 111 .

取样单元100的缓冲电路包括多个运算放大器例如150...151，二极管130...131，和电流源135，以产生缓冲信号V_HD。运算放大器150...151的正极输入端分别连接于多个保持电容器110...111。运算放大器150...151的负极输入端连接于缓冲电路的输出端。二极管130连接在运算放大器150的一个输出端与缓冲电路的输出端之间。二极管131连接在运算放大器151的一个输出端，与缓冲电路的输出端之间。这样，便可从多个保持电压的最高电压获取缓冲信号V_HD。电流源135用来进行终止。由脉冲信号PLS控制导通/截止的开关125连接于缓冲电路。开关125周期性地将缓冲信号V_HD传送至电容器115，以产生电压反馈信号V_V。因此，电压反馈信号V_V跟切换电路的输出电压V_O成比例。多个取样信号V_SPN...V_SP1在延迟时间T_d之后开始产生多个保持电压，从而避免电压信号V_AUX的尖峰干扰(spikeinterference)。当切换信号V_PWM禁用使得晶体管20截止时，将产生电压信号V_AUX的峰值。The buffer circuit of the sampling unit 100 includes a plurality of operational amplifiers such as 150 . . . 151 , diodes 130 . . . 131 , and a current source 135 to generate a buffered signal V _HD . The positive input terminals of the operational amplifiers 150...151 are respectively connected to a plurality of holding capacitors 110...111. The negative input terminals of the operational amplifiers 150...151 are connected to the output terminals of the buffer circuit. The diode 130 is connected between one output terminal of the operational amplifier 150 and the output terminal of the buffer circuit. The diode 131 is connected between one output terminal of the operational amplifier 151 and the output terminal of the buffer circuit. In this way, the buffered signal V _HD can be obtained from the highest voltage of the plurality of hold voltages. Current source 135 is used for termination. The switch 125 whose ON/OFF is controlled by the pulse signal PLS is connected to the buffer circuit. The switch 125 periodically transmits the buffered signal V _HD to the capacitor 115 to generate a voltage feedback signal V _V . Therefore, the voltage feedback signal V _V is proportional to the output voltage V _O of the switching circuit. The plurality of sampling signals V _SPN . . . V _SP1 start to generate a plurality of holding voltages after a delay time T _d , so as to avoid spike interference of the voltage signal V _AUX . When the switching signal V _PWM is disabled so that the transistor 20 is turned off, a peak value of the voltage signal V _AUX will be generated.

请参阅图6所示，当次级侧切换电流I_S下降到零时，电压信号V_AUX开始减少，然后这由比较器155检测到，使放电时间信号S_DS禁用。因此，放电时间信号S_DS的脉冲宽度跟次级侧切换电流I_S的放电时间T_DS相关。同时，当放电时间信号S_DS禁用时，多个取样信号V_SPN...V_SP1禁用，并且多次取样操作停止。这时，产生于缓冲电路输出端的缓冲信号V_HD代表终止电压。因此，一旦次级侧切换电流I_S下降到零，终止电压将跟取样到的电压信号V_AUX有关。缓冲信号V_HD从多个保持电压的较高电压获取，其中当电压信号V_AUX已经开始减少时，其将忽略所取样的电压。Referring to FIG. 6 , when the secondary side switching current I _S drops to zero, the voltage signal V _AUX starts to decrease, which is then detected by the comparator 155 , disabling the discharge time signal S _DS . Therefore, the pulse width of the discharge time signal S _DS is related to the discharge time T _DS of the secondary side switching current _IS . Meanwhile, when the discharge time signal S _DS is disabled, the multi-sampling signals V _{SPN .} . . V _SP1 are disabled, and the multi-sampling operation stops. At this time, the buffer signal V _HD generated at the output terminal of the buffer circuit represents the termination voltage. Therefore, once the secondary side switching current I _S drops to zero, the termination voltage will be related to the sampled voltage signal V _AUX . The buffered signal V _HD is taken from the higher of the multiple hold voltages, where it ignores the sampled voltage when the voltage signal V _AUX has started to decrease.

另外，一旦切换信号V_PWM启用，就确保了切换信号V_PWM的导通时间T_ON的最小值。切换信号V_PWM的导通时间T_ON的最小值进一步确保了放电时间T_DS的最小值，其确保了在多次取样电路700中取样电压信号V_AUX的适切的多次取样操作。放电时间T_DS跟切换信号V_PWM的导通时间T_ON相关。参照式(1)，(2)，和(3)和式(9)给出的次级侧电感L_S，放电时间T_DS可以由式(10)表达。In addition, once the switching signal V _PWM is enabled, a minimum value of the on-time T _ON of the switching signal V _PWM is ensured. The minimum value of the on-time T _ON of the switching signal V _PWM further ensures the minimum value of the discharge time T _DS , which ensures proper multi-sampling operation of the voltage signal V _AUX in the multi-sampling circuit 700 . The discharge time T _DS is related to the conduction time T _ON of the switching signal V _PWM . Referring to equations (1), (2), and (3) and the secondary side inductance L _S given by equation (9), the discharge time T _DS can be expressed by equation (10).

${L L}_{S S} = = {((\frac{{T T}_{NS NS}}{{T T}_{NP NP}}))}^{22} \times \times {L L}_{P P} - - - - - - ((99))$

${T T}_{DS DS} = = ((\frac{{V V}_{IN IN}}{{V V}_{O o} + + {V V}_{F f}})) \times \times \frac{{T T}_{NS NS}}{{T T}_{NP NP}} \times \times {T T}_{ON ON} - - - - - - ((1010))$

图7表示根据本发明的一个实施例的脉宽调制遮没单元500。脉宽调制遮没单元500包括PWM电路和遮没电路520。PWM电路包含与非门511，D触发器515，与门519，反相器512，反相器518，和电压回路误差放大器513。参照图4和图6，反相器512连接于振荡单元600，以接收脉冲信号PLS。反相器512的输出端连接于D触发器515的时钟输入端，使切换信号V_PWM启用。供给电压V_CC拉升D触发器515的D端输入。D触发器515的输出端连接于与门519的第一输入端。与门519的第二输入端连接于反相器512的输出端。与门519产生切换信号V_PWM。D触发器515的复位输入端连接于与非门511的输出端。为了周期地关闭切换信号V_PWM，与非门511的第一输入端由复位信号RST所提供。电压回路误差放大器513依据电压反馈信号V_V产生复位信号RST。与非门511的第二输入端连接于遮没电路520的输出端，以接收遮没信号V_BLK。FIG. 7 shows a pulse width modulation blanking unit 500 according to one embodiment of the present invention. The pulse width modulation blanking unit 500 includes a PWM circuit and a blanking circuit 520 . The PWM circuit includes a NAND gate 511 , a D flip-flop 515 , an AND gate 519 , an inverter 512 , an inverter 518 , and a voltage loop error amplifier 513 . 4 and 6, the inverter 512 is connected to the oscillation unit 600 to receive the pulse signal PLS. The output terminal of the inverter 512 is connected to the clock input terminal of the D flip-flop 515 to enable the switching signal V _PWM . The supply voltage V _CC pulls up the D terminal input of the D flip-flop 515 . The output terminal of the D flip-flop 515 is connected to the first input terminal of the AND gate 519 . The second input end of the AND gate 519 is connected to the output end of the inverter 512 . The AND gate 519 generates the switching signal V _PWM . The reset input terminal of the D flip-flop 515 is connected to the output terminal of the NAND gate 511 . In order to periodically turn off the switching signal V _PWM , the first input terminal of the NAND gate 511 is provided by the reset signal RST. The voltage loop error amplifier 513 generates a reset signal RST according to the voltage feedback signal V _V . The second input terminal of the NAND gate 511 is connected to the output terminal of the blanking circuit 520 to receive the blanking signal V _BLK .

参照图7，遮没电路520包括与非门523，电流源525，晶体管526，反相器521，电容器527，和反相器522。切换信号V_PWM提供至反相器521的输入端和与非门523的第一输入端。反相器521的输出端用以导通/截止晶体管526。反相器522的输出端连接于与非门523的第二输入端。电流源525的电流和电容器527的电容决定遮没信号V_BLK的脉冲宽度。反相器518接收遮没信号V_BLK并且产生消除信号CLR。参照图6，消除信号CLR和遮没信号V_BLK互为反相。消除信号CLR控制开关123和124的导通与截止。当切换信号V_PWM启用时，遮没电路520输出遮没信号V_BLK，目的是使V_PWM禁用，防止D触发器515被复位。Referring to FIG. 7 , the blanking circuit 520 includes a NAND gate 523 , a current source 525 , a transistor 526 , an inverter 521 , a capacitor 527 , and an inverter 522 . The switching signal V _PWM is provided to the input terminal of the inverter 521 and the first input terminal of the NAND gate 523 . The output terminal of the inverter 521 is used to turn on/off the transistor 526 . The output terminal of the inverter 522 is connected to the second input terminal of the NAND gate 523 . The current of the current source 525 and the capacitance of the capacitor 527 determine the pulse width of the blanking signal V _BLK . The inverter 518 receives the blanking signal V _BLK and generates a cancel signal CLR. Referring to FIG. 6, the cancel signal CLR and the blanking signal V _BLK are inverse phases of each other. The cancellation signal CLR controls the on and off of the switches 123 and 124 . When the switching signal V _PWM is enabled, the blanking circuit 520 outputs a blanking signal V _BLK to disable V _PWM and prevent the D flip-flop 515 from being reset.

由于当切换信号V_PWM关闭时，电压信号V_AUX从变压器10反射而得，因此V_PWM必须维持最小切换频率，以多次取样电压信号V_AUX确保变压器10的切换。Since the voltage signal V _AUX is reflected from the transformer 10 when the switching signal V _PWM is turned off, V _PWM must maintain a minimum switching frequency to ensure the switching of the transformer 10 by sampling the voltage signal V _AUX multiple times.

图8表示根据本发明的一个实施例的振荡单元600。运算放大器201，电阻器210，晶体管250构成了第一电压电流转换器。第一电压电流转换器产生参考电流I₂₅₀以响应参考电压V_REF。多个晶体管，例如251，252，253，254和255构成了电流镜，其目的是响应参考电流I₂₅₀以产生充电电流I₂₅₃和放电电流I_D。第一开关230连接在晶体管253的漏极和电容器215之间。第二开关231连接在电容器215和晶体管255的漏极之间。第一比较器205产生脉冲信号PLS以决定切换频率。第三开关232的第一端由高门限(high-threshold)电压V_H所供应。第四开关233的第一端由低门限(low-threshold)电压V_L所供应。第三开关232的第二终端和第四开关233的第二终端连接于比较器205的负极端。反相器260的输入端连接于比较器205的输出端。反相器260的输出端产生反相脉冲信号/PLS。脉冲信号PLS控制第二开关231和第四开关233的导通与截止。反相脉冲信号/PLS控制第一开关230和第三开关232的导通与截止。Fig. 8 shows an oscillating unit 600 according to one embodiment of the present invention. The operational amplifier 201, the resistor 210, and the transistor 250 constitute a first voltage-to-current converter. The first voltage-to-current converter generates a reference current I ₂₅₀ in response to a reference voltage V _REF . A plurality of transistors, such as 251, 252, 253, 254 and 255 form a current mirror whose purpose is to generate a charging current I ₂₅₃ and a discharging current I _D in response to a reference current I ₂₅₀ . The first switch 230 is connected between the drain of the transistor 253 and the capacitor 215 . The second switch 231 is connected between the capacitor 215 and the drain of the transistor 255 . The first comparator 205 generates the pulse signal PLS to determine the switching frequency. The first terminal of the third switch 232 is supplied by a high-threshold voltage V _H . The first terminal of the fourth switch 233 is supplied by a low-threshold voltage V _L . The second terminal of the third switch 232 and the second terminal of the fourth switch 233 are connected to the negative terminal of the comparator 205 . The input terminal of the inverter 260 is connected to the output terminal of the comparator 205 . The output terminal of the inverter 260 generates an inverted pulse signal /PLS. The pulse signal PLS controls the turn-on and turn-off of the second switch 231 and the fourth switch 233 . The antiphase pulse signal /PLS controls the on and off of the first switch 230 and the third switch 232 .

如上所述，本发明提供了电源转换器的切换控制器中的精确多次取样电路。为调节电源转换器的输出电压和输出电流，多次取样电路能够使得电源转换器在不使用光耦合器和次级侧调整器下来测量变压器的电压信号和其放电时间。As described above, the present invention provides an accurate multi-sampling circuit in a switching controller of a power converter. To regulate the output voltage and output current of the power converter, the multi-sampling circuit enables the power converter to measure the voltage signal of the transformer and its discharge time without using an optocoupler and a secondary-side regulator.

以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的结构及技术内容作出些许的更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the structure and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but if they do not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1, a kind of sample circuit is used for receiving reflected voltage signal to generate feedback signal and discharge time signal from the ancillary coil of transformer, it is characterized in that this sample circuit comprises:

Delay unit, receive switching signal, and when above-mentioned switch signal forbidden, produce time delayed signal, wherein above-mentioned switching signal is switched above-mentioned transformer via switch, be that above-mentioned switching signal is used for conducting or closes above-mentioned switch, when the above-mentioned switch of conducting, at the primary side generation primary side switch current of above-mentioned transformer, when closing above-mentioned switch, at the primary side generation primary side switch current of above-mentioned transformer;

The signal generation unit receives above-mentioned time delayed signal, above-mentioned switching signal and above-mentioned reflected voltage signal, to produce above-mentioned discharge time signal and a plurality of sampled signal, wherein above-mentioned a plurality of sampled signal V _SP1V _SPNRepresent that wherein N is greater than or equal to 2 integer, wherein at first generates sampled signal V _SPN..., just generate sampled signal V at last _SP1

Sampling unit, it comprises a plurality of maintenance capacitors and buffer circuit, wherein said sampling unit receives above-mentioned a plurality of sampled signal,, above-mentioned reflected voltage signal supplies with above-mentioned a plurality of maintenance capacitor respectively so that being taken a sample, wherein above-mentioned a plurality of maintenance capacitor produces a plurality of sustaining voltages, wherein above-mentioned buffer circuit is coupled to above-mentioned a plurality of maintenance capacitor, and with the highest sustaining voltage in a plurality of sustaining voltages as buffering signals; And

Comparison circuit, be coupled to above-mentioned buffer circuit, be used for more above-mentioned buffering signals and level shift signal, to produce stop signal, wherein above-mentioned level shift signal produces and adds threshold signal from above-mentioned reflected voltage signal, and in case above-mentioned level shift signal is lower than above-mentioned buffering signals, above-mentioned stop signal is enabled; Wherein, when above-mentioned switch signal forbidden, above-mentioned discharge time signal is for enabling; Above-mentioned stop signal makes the discharge time signal forbidding; The enabling time of above-mentioned discharge time signal equals the discharge time of above-mentioned transformer; After above-mentioned time delayed signal stopped, above-mentioned a plurality of sampled signals began to produce; Above-mentioned stop signal stops above-mentioned a plurality of sampled signal; And after producing stop signal, produce above-mentioned feedback signal according to above-mentioned buffering signals, it is proportional that wherein above-mentioned feedback signal is caught up with the output voltage of stating transformer.

2, sample circuit according to claim 1 is characterized in that wherein said signal generation unit comprises:

The sampling pulse generator periodically produces sample-pulse signal, to carry out repeatedly sampling operation;

First signal generator, between above-mentioned discharge time signal time suitable to moulding, produce above-mentioned a plurality of sampled signal according to above-mentioned sample-pulse signal with order, wherein be inserted in the top of above-mentioned discharge time signal time of delay, and above-mentioned a plurality of sampled signal was forbidden during above-mentioned time of delay; And

The secondary signal generator produces above-mentioned discharge time signal, and wherein when above-mentioned switch signal forbidden, above-mentioned discharge time signal is for enabling; When above-mentioned stop signal produced, above-mentioned discharge time signal was forbidding; And when above-mentioned switching signal was enabled, above-mentioned discharge time signal was forbidding.

3, sample circuit according to claim 1, it is characterized in that wherein said sampling unit also comprises the sampling switch that is connected to above-mentioned buffer circuit, above-mentioned sampling switch is controlled by pulse signal cycle ground, be used for transmitting above-mentioned buffering signals to output capacitor, producing above-mentioned feedback signal, wherein above-mentioned switching signal catches up with that to state pulse signal relevant.

4, sample circuit according to claim 1 is characterized in that wherein said feedback signal is produced by the above-mentioned reflected voltage signal of repeatedly taking a sample, and in case the primary side switch current of above-mentioned transformer drops to zero, above-mentioned feedback signal is promptly measured.

5, sample circuit according to claim 1, it is characterized in that wherein said switching signal has minimum ON time, wherein in a single day above-mentioned switching signal is enabled, and above-mentioned minimum ON time is used for providing minimum discharge time for the repeatedly sampling operation of above-mentioned reflected voltage signal.

6, sample circuit according to claim 1 is characterized in that wherein said switching signal has minimum switching frequency carrying out the switching of above-mentioned transformer, thereby implements the repeatedly sampling operation of above-mentioned reflected voltage signal.

7, a kind of repeatedly sample circuit is used for receiving reflected voltage signal from the coil of transformer to generate feedback signal and discharge time signal, it is characterized in that this repeatedly sample circuit comprise:

Signal generator receives switching signal and above-mentioned reflected voltage signal, and with generation discharge time signal and a plurality of sampled signal, and when above-mentioned switch signal forbidden, order produces above-mentioned a plurality of sampled signal, wherein above-mentioned a plurality of sampled signal V _SP1V _SPNRepresent that wherein N is greater than or equal to 2 integer, wherein at first generates sampled signal V _SPN..., just generate sampled signal V at last _SP1Wherein above-mentioned switching signal is switched above-mentioned transformer via switch, be that above-mentioned switching signal is used for conducting or closes above-mentioned switch, when the above-mentioned switch of conducting, primary side at above-mentioned transformer produces the primary side switch current, when closing above-mentioned switch, at the primary side generation primary side switch current of above-mentioned transformer;

Sample-and-hold circuit, it comprises a plurality of maintenance capacitors and buffer circuit, wherein said sample-and-hold circuit receives above-mentioned a plurality of sampled signal, so that above-mentioned reflected voltage signal is taken a sample, supply with above-mentioned a plurality of maintenance capacitor respectively, the sampling operation of the above-mentioned a plurality of sampled signals of wherein above-mentioned a plurality of maintenance capacitor foundations is to produce a plurality of sustaining voltages, and wherein above-mentioned buffer circuit is according to the ceiling voltage generation buffering signals of above-mentioned a plurality of sustaining voltages; And

Comparison circuit, more above-mentioned buffering signals and level shift signal produce stop signal, wherein above-mentioned level shift signal produces and adds threshold signal from above-mentioned reflected voltage signal, and in case above-mentioned level shift signal is lower than above-mentioned buffering signals, above-mentioned stop signal is for enabling; Wherein, when above-mentioned switch signal forbidden, above-mentioned discharge time signal is for enabling; Above-mentioned stop signal makes above-mentioned discharge time signal be forbidding; The enabling time of above-mentioned discharge time signal equals the discharge time of above-mentioned transformer; After producing above-mentioned stop signal, above-mentioned feedback signal produces according to above-mentioned buffering signals; Above-mentioned stop signal stops above-mentioned a plurality of sampled signal; And it is proportional that above-mentioned feedback signal is caught up with the output voltage of stating transformer.

8, repeatedly sample circuit according to claim 7 is characterized in that wherein said signal generator comprises:

First signal generator, between the time suitable to moulding of above-mentioned discharge time signal, produce a plurality of sampled signals according to above-mentioned sample-pulse signal with order, wherein be inserted into the top of above-mentioned discharge time signal time of delay, and above-mentioned a plurality of sampled signal is forbidding during above-mentioned time of delay; And

The secondary signal generator produces above-mentioned discharge time signal, wherein in a single day above-mentioned switch signal forbidden, and above-mentioned discharge time signal is for enabling; In case above-mentioned stop signal produces, above-mentioned discharge time signal is forbidding; And when above-mentioned switching signal was enabled, above-mentioned discharge time signal was forbidding.

9, repeatedly sample circuit according to claim 7, it is characterized in that wherein said sample-and-hold circuit also comprises the sampling switch that is connected to above-mentioned buffer circuit, above-mentioned sampling switch is controlled by pulse signal cycle ground, be used for transmitting above-mentioned buffering signals to output capacitor producing above-mentioned feedback signal, wherein above-mentioned switching signal catches up with that to state pulse signal relevant.

10, repeatedly sample circuit according to claim 7, the above-mentioned reflected voltage signal that it is characterized in that wherein repeatedly taking a sample are producing above-mentioned feedback signal, and in case the primary side switch current of above-mentioned transformer drops to zero, above-mentioned feedback signal is promptly measured.

11, repeatedly sample circuit according to claim 7, it is characterized in that wherein said switching signal has minimum ON time, wherein in a single day above-mentioned switching signal is enabled, and above-mentioned minimum ON time is used for providing minimum discharge time for the repeatedly sampling operation of above-mentioned reflected voltage signal.

12, repeatedly sample circuit according to claim 7 is characterized in that wherein said switching signal has minimum switching frequency carrying out the switching of above-mentioned transformer, thereby implements the repeatedly sampling operation of above-mentioned reflected voltage signal.

13, a kind of repeatedly sample circuit is used for receiving the reflected voltage signal that comes from transformer to generate feedback signal and discharge time signal, it is characterized in that this repeatedly sample circuit comprise:

Signal generator receives switching signal and above-mentioned reflected voltage signal, produces a plurality of sampled signals with order, and when above-mentioned switch signal forbidden, produces above-mentioned a plurality of sampled signal, wherein above-mentioned a plurality of sampled signal V _SP1V _SPNRepresent that wherein N is greater than or equal to 2 integer, wherein at first generates sampled signal V _SPN..., just generate sampled signal V at last _SP1Wherein above-mentioned switching signal is used for switching above-mentioned transformer, be that above-mentioned switching signal is used for conducting or off switch, when the above-mentioned switch of conducting, primary side at above-mentioned transformer produces the primary side switch current, when closing above-mentioned switch, at the primary side generation primary side switch current of above-mentioned transformer;

Sample-and-hold circuit, it comprises a plurality of maintenance capacitors and buffer circuit, wherein said sample-and-hold circuit receives above-mentioned a plurality of sampled signal, so that above-mentioned reflected voltage signal is taken a sample, supply with above-mentioned a plurality of maintenance capacitor respectively, wherein above-mentioned a plurality of maintenance capacitor produces a plurality of sustaining voltages, and wherein above-mentioned buffer circuit is according to the ceiling voltage generation buffering signals of above-mentioned a plurality of sustaining voltages; And

Comparison circuit, via more above-mentioned buffering signals and level shift signal, produce stop signal, wherein above-mentioned level shift signal produces and adds threshold signal from above-mentioned reflected voltage signal, and, produce above-mentioned stop signal in case above-mentioned level shift signal is lower than above-mentioned buffering signals; Wherein, in case above-mentioned stop signal produces, above-mentioned feedback signal produces according to above-mentioned buffering signals; Above-mentioned stop signal stops above-mentioned a plurality of sampled signal; And it is proportional that above-mentioned feedback signal is caught up with the output voltage of stating transformer.

14, repeatedly sample circuit according to claim 13, the above-mentioned reflected voltage signal that it is characterized in that repeatedly taking a sample produces above-mentioned feedback signal, and in case the primary side switch current of above-mentioned transformer drops to zero, above-mentioned feedback signal is promptly measured.

15, repeatedly sample circuit according to claim 13, it is characterized in that wherein said switching signal has minimum ON time, wherein in a single day above-mentioned switching signal is enabled, and above-mentioned minimum ON time is used for providing minimum discharge time for the repeatedly sampling operation of above-mentioned reflected voltage signal.