CN100442515C - integrated circuit - Google Patents

Abstract

An electronic device configured with an electronic component comprising an integrated circuit, having an input and an output, and comprising: a semiconductor substrate comprising a doping of a first doping type having a first doping concentration (n1) and having at least one active element; at least one capacitor; and at least one resistor; an insulating layer provided on a semiconductor substrate, the insulating layer being interrupted in certain areas, wherein the capacitor is defined as a MOS capacitor a third dielectric layer on the insulating layer, in some regions on the third dielectric layer, a second layer having a resistance value is provided to form the resistor, the resistor is electrically coupled to the capacitor and connected to the output through a third current source lead; and a protective layer disposed on the entire circuit.

Description

integrated circuit

technical field

The invention relates to an electronic device provided with electronic components comprising an integrated circuit comprising at least one active component and at least one capacitor and at least one resistor electrically coupled to the active component on said semiconductor substrate semiconductor substrate. The invention further relates to transmitters, receivers, peripheral circuits, current source circuits, filter modules, electronic components and integrated circuits.

Today, capacitor-resistor networks are used in many devices for electronic data processing or mobile communications. These networks are typically fabricated on ceramic substrates by thick film techniques. A disadvantage of this technique is that the capacitance of the capacitor and/or the resistance value of the resistor can only be produced within a wide tolerance range. Additionally, no active components such as diodes can be integrated in these networks.

For example, EP0192989 discloses an integrated circuit comprising transistors, capacitors and resistors. The two electrodes of the capacitor and the resistor are formed through the polysilicon layer.

Since polysilicon is compatible with standard semiconductor manufacturing processes, polysilicon is widely used as an electrode or resistor material in semiconductor devices. A disadvantage of using polysilicon as an electrode or resistor material is that it is difficult to control the grain size of the polysilicon during the fabrication of the polysilicon layer. A further disadvantage is that it is difficult to control the doping level during the manufacture of the doped polysilicon layer.

These two effects have the result that the capacitance value of the capacitor and/or the resistance value of the resistor can only be set with a wide tolerance range.

Furthermore, polysilicon has a low resistivity, so that high resistance points can only be produced in circuits by resistive bending, which takes up more space.

It is therefore an object of the present invention to provide an electronic device comprising an electronic component configured with an improved integrated circuit comprising a semiconductor substrate, at least one active component, at least one capacitor and at least one resistor.

This object is achieved by an electronic device provided with electronic components comprising an integrated circuit having inputs and outputs and comprising: a semiconductor substrate comprising a first dopant having a first doping concentration (n1) A dopant of a heterotype and having at least one active element; at least one capacitor comprising a first electrode, a second electrode, and a first dielectric layer; and at least one resistor comprising a material selected from the group consisting of : β-tantalum, Ta _x N _Y (0<x≤1, 0<y≤1), Ta _1-xy Si _x N _y (0<x≤1, 0<y≤1), Ta _1-xy Al _x N _y (0<x≤1, 0<y≤1), Ni _x Cr _y (0<x≤1, 0<y≤1), Ni _x Cr _x Al _z (0<x≤1, 0< y≤1, 0<z≤1), _Six Cr _x O _z (0<x≤1, 0<y≤1, 0<z≤≤1), _Six Cr _x N _z (0<x≤1 , 0<y≤1, 0<z≤1), Ti _x W _y (0<x≤1, 0<y≤1), Ti _x W _y N _z (0<x≤1, 0<y≤1 , 0<z≤1), Ti _x N _y (0<x≤1, 0<y≤1) and Cu _x Ni _y (0<x≤1, 0<y≤1), the resistors and MOS The capacitor is electrically coupled to the active element, wherein the active element is a diode serving as an overvoltage protection device, the diode being composed of a first semiconductor having a dopant of the first doping type at a second doping concentration (n2) region, and a second semiconductor region having a dopant of a second doping type with a third doping concentration, wherein the diode is electrically connected to the input through a first current source lead, and the second doping concentration ( n2) lower than the first doping concentration (n1) of the substrate (1); providing an insulating layer on the semiconductor substrate, which is interrupted in certain regions, wherein the capacitor is defined as a MOS capacitor, The semiconductor substrate of the MOS capacitor is used as a first electrode, the semiconductor substrate is grounded through a fourth current source lead, a first oxide layer is provided between the semiconductor substrate and the first dielectric layer, and the capacitor A second electrode coupled to the first current source lead; a third dielectric layer on the insulating layer, in some regions on the third dielectric layer, a second layer having a resistance value is provided to form the a resistor electrically coupled to the second electrode of the capacitor and connected to the output through the third current source lead; and a protective layer disposed over the entire circuit.

Layers of these materials can be provided with a high degree of uniformity so that resistors can be fabricated whose resistance values lie within narrow tolerances.

A further advantage is that these materials have high resistivity values. Due to these higher resistivity values, the external dimensions of the resistor can be reduced. This saves valuable semiconductor material and ensures lower process costs. A further advantage is that these materials have low TCR values (temperature coefficient of resistance) of 0 to 100 ppm/K. This allows the resistance value of the resistor to change only slightly during operation of the electronic device.

If the capacitor is advantageously constructed as a MOS (Metal Oxide Semiconductor) capacitor, the resulting capacitor has a capacitance value within narrower tolerances than a capacitor with two electrodes of semiconductor material, eg polysilicon.

The advantageous embodiments of the integrated circuit configuration of the invention make it possible to broaden the range of applications of electronic components and thus electronic devices.

The present invention further relates to a transmitter, a receiver, each comprising an electronic component having an integrated circuit, and an electrical component, a peripheral circuit, a current source circuit and a filter module, each comprising an integrated circuit as described above.

The invention will now be described in more detail with reference to five accompanying drawings in which:

1 and 2 are each a schematic cross-sectional view of a semiconductor substrate having a diode, a MOS capacitor and a resistor,

3 is a schematic cross-sectional view of a semiconductor substrate with diodes, MOS capacitors and resistors, and additional capacitors,

Figures 4 and 5 show possible circuit configurations.

Detailed ways

The electronic device may be, for example, a device for electronic data processing, such as a computer, a laptop or a PDA (Personal Digital Assistant). Alternatively, the electronic device may be a mobile data transmission device such as a mobile phone.

A mobile phone device includes, for example, a power supply unit, a display device, a speaker, a microphone, an input device, a memory device, an antenna, a transmitter, a receiver, peripheral circuits, a filter module, and a current source circuit. The transmitter, receiver, peripheral circuitry, filter module, and current source circuitry may each include electronic components having an integrated circuit comprising at least one active element provided on the semiconductor substrate and electrically coupled to the semiconductor substrate. Semiconductor substrate of at least one capacitor and at least one resistor of active elements, wherein the resistor comprises a material selected from the group consisting of: β-tantalum, Tax _{N y} (0<x≤1, 0<y≤1) , Ta _1-xy Six _{N y} (0<x≤1, 0<y≤1), Ta _1-xy Al _x N _y (0<x≤1, 0<y≤1), Ni _x Cr _y ( 0<x≤1, 0<y≤1), Ni _x Cr _y Al _z (0<x≤1, 0<y≤1, 0<z≤1), _Six Cr _y O _z (0<x≤ 1, 0<y≤1, 0<z≤1), _Six Cr _y N _z (0<x≤1, 0<y≤1, 0<z≤1), Ti _x W _y (0<x≤ 1, 0<y≤1), Ti _x W _y N _z (0<x≤1, 0<y≤1, 0<z≤1), Ti _x N _y (0<x≤1, 0<y≤ 1) and Cu _x Ni _y (0<x≤1, 0<y≤1).

The active element may be, for example, a diode or a transistor. In circuit configurations diodes are used, for example, as overvoltage protection devices. The diodes may be, for example, pn diodes, zener diodes, back-to-back diodes (diodes connected in reverse series), front-to-back diodes (diodes connected in series), or floating gate diodes.

The transistor can be, for example, a bipolar transistor or a field effect transistor (FET), such as a junction field effect transistor (JFET), a P-channel metal-oxide-semiconductor field-effect transistor (PMOS-FET), an N-channel metal-oxide-semiconductor field-effect transistor (FET), Effect Transistor (NMOS-FET) or Complementary Metal-Oxide-Semiconductor Field-Effect Transistor (CMOS-FET).

Fig. 1 is a schematic cross-sectional view of a semiconductor substrate 1 with pn diodes, MOS capacitors and resistors. The semiconductor substrate 1 includes, for example, Si having a first dopant type dopant of a first doping concentration n1, or a Group III/IV semiconductor such as Si having a first doping type dopant having a first doping concentration n1. Dopant GaAs, or SiC semiconductor with first dopant type dopant with first doping concentration n1, or SiGe semiconductor with first dopant type dopant with first dopant concentration n1. In this semiconductor substrate 1 there is a first semiconductor region 2 comprising Si with a first doping type dopant of a second doping concentration n2, or a group III/IV semiconductor such as GaAs of the first dopant type dopant of n2, or SiC semiconductor of the first dopant type dopant of the second doping concentration n2. The doping concentration n2 in the first semiconductor region 2 is lower than the doping concentration n1 in the semiconductor substrate 1 . A smaller second semiconductor region 3 is present in the first semiconductor region 2, the second semiconductor region 3 comprising Si with a second doping type dopant of a third doping concentration n3, or a Group III/IV semiconductor, Such as GaAs with the second dopant type dopant of the third doping concentration n3, or SiC with the second dopant type dopant of the third doping concentration n3. The dopant of the first doping type used may be, for example, B, Al or Ga, and the dopant of the second doping type used may be, for example, P, As or Sb. The first semiconductor region 2 and the second semiconductor region 3 form a pn diode.

On the semiconductor substrate 1 is provided an insulating layer 4 comprising, for example, SiO ₂ , SiO ₂ doped with a doped oxide such as boron oxide or phosphorous oxide, or SiN(H). The insulating layer 4 is interrupted in certain regions. In these regions, a first oxide layer 5 , preferably comprising SiO ₂ , is located on the semiconductor substrate 1 . On the oxide layer 5 there is a first dielectric layer 6 comprising, for example, Si ₃ N ₄ , _Six O _y N _z (0<x≤1, 0<y≤1, 0<z≤ 1), Ta ₂ O ₅ , (Ta ₂ O ₅ ) _x -(Al ₂ O ₃ ) _1-x (0<x≤1), (Ta ₂ O ₅ ) _x -(TiO ₂ ) _1-x (0 ＜x≤1), (Ta ₂ O ₅ ) _x -(Nb ₂ O ₅ ) _1-x (0＜x≤1), (Ta ₂ O ₅ ) _x -(SiO ₂ ) _1-x (0＜x ≤1), TiO ₂ , ZrO ₂ , HfO ₂ or Nb ₂ O ₅ . On the first dielectric layer 6 is located a first conductive layer 7 , which may comprise for example poly-Si, Ta or Al. On the first conductive layer 7 there is provided a second oxide layer 8, preferably comprising _SiO2 . On the second oxide layer 8 there is a second dielectric layer 9 comprising, for example, Si ₃ N ₄ , _Six O _y N _z (0<x≤1, 0<y≤1, 0<z ≤1), Ta ₂ O ₅ , (Ta ₂ O ₅ ) _x -(Al ₂ O ₃ ) _1-x (0<x≤1), (Ta ₂ O ₅ ) _x -(TiO ₂ ) _1-x ( 0＜x≤1), (Ta ₂ O ₅ ) _x -(Nb ₂ O ₅ ) _1-x (0＜x≤1), (Ta ₂ O ₅ ) _x -(SiO ₂ ) _1-x (0＜ x≤1), TiO ₂ , ZrO ₂ , HfO ₂ or Nb ₂ O ₅ .

A first layer 10 having a resistance value is provided on the second dielectric layer 9, and the layer 10 includes, for example, β-tantalum, Tax _{N y} (0<x≤1, 0<y≤1), Ta _{1-xy Six} N _y (0<x≤1, 0<y≤1), Ta _{1- xy} Al _x N _y (0<x≤1, 0<y≤1), Ni _x Cr _y (0<x≤1 , 0<y≤1), Ni _x Cr _y Al _z (0<x≤1, 0<y≤1, 0<z≤1), _Six Cr _y O _z (0<x≤1, 0<y ≤1, 0<z≤1), _Six Cr _y N _z (0<x≤1, 0<y≤1, 0<z≤1), Ti _x W _y (0<x≤1, 0<y ≤1), Ti _x W _y N _z (0<x≤1, 0<y≤1, 0<z≤1), Ti _x N _y (0<x≤1, 0<y≤1) or Cu _x Ni _y (0<x≤1, 0<y≤1).

The third dielectric layer 11 is located on the insulating layer 4, and the layer 11 includes, for example, Si ₃ N ₄ , Six _{O y} N _z (0<x≤1, 0<y≤1, 0<z≤1), Ta ₂ O ₅ , (Ta ₂ O ₅ ) _x -(Al ₂ O ₃ ) _1-x (0<x≤1), (Ta ₂ O ₅ ) _x -(TiO ₂ ) _1-x (0<x≤1) , (Ta ₂ O ₅ ) _x -(Nb ₂ O ₅ ) _1-x (0<x≤1), (Ta ₂ O ₅ ) _x -(SiO ₂ ) _1-x (0<x≤1), TiO _2. ZrO ₂ , HfO ₂ or Nb ₂ O ₅ . On said third dielectric layer 11, we find in some regions a second layer 12 with a resistance value comprising, for example, β-tantalum, Tax _{N y} (0<x≤1, 0<y ≤1), Ta _1-xy Si _x N _y (0<x≤1, 0<y≤1), Ta _{1- xy} Al _x N _y (0<x≤1, 0<y≤1), Ni _x Cr _y (0<x≤1, 0<y≤1), Ni _x Cr _y Al _z (0<x≤1, 0<y≤1, 0<z≤1), _Six Cr _y O _z (0 <x≤1, 0<y≤1, 0<z≤1), _Six Cr _y N _z (0<x≤1, 0<y≤1, 0<z≤1), Ti _x W _y (0 <x≤1, 0<y≤1), Ti _x W _y N _z (0<x≤1, 0<y≤1, 0<z≤1), Ti _x N _y (0<x≤1, 0 <y≤1) or Cu _x Ni _y (0<x≤1, 0<y≤1). Preferably, the second layer 12 having a resistance value includes β-tantalum, Tax _{N y} (0<x≤1, 0<y≤1), Ti _x W _y N _z (0<x≤1, 0<y ≤1, 0<z≤1) or Ti _x N _y (0<x≤1, 0<y≤1). A protective layer 13 is provided over the entire assembly, eg comprising an organic or inorganic material, or a combination of inorganic materials, or a combination of organic and inorganic materials. The organic material used can be, for example, polybenzocyclobutene or polyimide, and the inorganic material used can be, for example, SiN(H), SiO ₂ or Six _{O y} N _z (0<x≤ 1, 0<y≤1, 0<z≤1).

The second semiconductor region 3 of the pn diode is electrically connected to the input 15 of the circuit arrangement and to the first conductive layer 7 via a first current source lead 14, the first layer 10 having a resistance value is connected to ground through the second current source lead. The first conductive layer 7 is structured such that it is in physical and electrical contact with the second layer 12 having a resistance value. For this purpose, the first conductive layer 7 and the second layer 12 having a resistance value can be structured such that they are arranged partially overlapping or adjacent to each other. The second layer 12 having a resistance value is electrically connected to an output 18 of the circuit arrangement through a third current source lead 17 . The semiconductor substrate 1 is grounded via the fourth current source lead 19 . Current source leads 14, 16, 17, 19 are formed through contact holes filled with conductive material. The current source lead may comprise one or several conductive materials, for example in the form of a layer sequence. Thus, for example, the first current source lead 14 may comprise a material having a resistive value provided in the form of a third layer 20 having a resistive value, and a material 21 having a good electrical conductivity, such as Al, Al doped with Cu, or Al doped with Si. The fourth current source lead 19 may be made of a material having a resistive value, provided for example in the form of a fourth layer 22 having a resistive value, and a material 23 having good electrical conductivity, such as Al, Al doped with Cu or Al doped with Al structure of Si.

In this embodiment of the invention, a MOS capacitor is formed by the following layers: a semiconductor substrate 1 . An oxide layer 5 , a first dielectric shield layer 6 , a first conductive layer 7 , a second oxide layer 8 , a second dielectric layer 9 and a first resistance layer 10 . The MOS capacitor in this embodiment has a double stack structure. The semiconductor substrate 1 serves here as a first electrode, the first resistive layer 10 serves as a second electrode, and the first conductive layer 7 serves as an intermediate electrode of a MOS capacitor.

Alternatively, the first resistive layer 10 may be omitted in this structure, in which case the current source lead 16 will serve as the second electrode of the MOS capacitor.

Depending on the material used for the first conductive layer 7, for example, the second oxide layer 8 may be omitted. For example, if Ta or Al is used as the material of the first conductive layer 7, the second oxide layer 8 may be omitted. In addition, the first oxide layer 5 may also be omitted.

Alternatively, the MOS capacitor may have a single stack structure. In this embodiment, a MOS capacitor is formed, for example, by the semiconductor substrate 1 , the first oxide layer 5 , the first dielectric layer 6 and the first resistive layer 10 . Alternatively, it is also possible in this embodiment of the MOS capacitor to omit the first resistive layer 10 again, and then form the second electrode of the MOS capacitor via the second current source lead 16 .

Alternatively, the MOS capacitor may have a multi-stack structure. Depending on the number of layer stacks the MOS capacitor will have, a corresponding number of oxide layers, dielectric layers and conductive layers are deposited between the first and second electrodes of the MOS capacitor. Alternatively, the oxide layer may be omitted in a multi-stack structure, and a corresponding number of dielectric layers and conductive layers are deposited between the first and second electrodes of the MOS capacitor.

FIG. 2 is a schematic cross-sectional view of a semiconductor substrate 1 having a pn diode, a MOS capacitor and a resistor, wherein the MOS capacitor has a single-stack structure. In this embodiment, the second current source lead 16 is not grounded.

A pn diode formed by the first semiconductor region 2 and the second semiconductor region 3 occurs in the semiconductor substrate 1 . The insulating layer 4 is provided on the semiconductor substrate 1 and is disconnected in several regions. In these regions, the first dielectric layer 6 is located on the semiconductor substrate 1 . The third dielectric layer 11 is located on the insulating layer 4 . In several regions, the second resistive layer 12 is located on the third dielectric layer 11 . A protective layer 13 is present on the dielectric layer 11 and the second resistive layer 12 . The second semiconductor region 3 is electrically connected to an input 15 of the circuit arrangement via a first current source lead 14 . The second current source lead 16 forms the second electrode of the MOS capacitor. In addition, a second current source lead 16 connects the MOS capacitor to the second resistive layer 12 . The MOS capacitor is electrically connected to the second semiconductor region 3 and is electrically connected to the input 15 of the circuit arrangement through a first current source lead 14 and a second current source lead 16 in electrical contact. The second resistive layer 12 is connected to an output 18 of the circuit arrangement via a third current source lead 17 . The semiconductor substrate 1 is grounded via the fourth current source lead 23 .

Fig. 3 is a schematic cross-sectional view of a semiconductor substrate 1 with pn diodes, MOS capacitors, resistors and further capacitors. In this embodiment of the circuit arrangement according to the invention, the second current source lead 16 is not directly electrically connected to the second resistive layer 12 , but is constructed such that it additionally serves as a second electrode of a further capacitor. The second resistive layer 12 is configured such that it functions as a resistor on the one hand and as a first electrode of a further capacitor on the other hand. The fourth dielectric layer 24 present between the second resistive layer 12 and those regions of the second current source lead 16 serving as the second electrode of the further capacitor forms the dielectric of the further capacitor, the fourth dielectric layer 24 may comprise , such as Si ₃ N ₄ , Six _{O y} N _z (0<x≤1, 0<y≤1, 0<z≤1), Ta ₂ O ₅ , (Ta ₂ O ₅ ) _x -(Al ₂ O ₃ ) _1-x (0<x≤1), (Ta ₂ O ₅ ) _x -(TiO ₂ ) _1-x (0<x≤1), (Ta ₂ O ₅ ) _x -(Nb ₂ O ₅ ) _1-x (0<x≤1), (Ta ₂ O ₅ ) _x -(SiO ₂ ) _1-x (0<x≤1), TiO ₂ , ZrO ₂ , HfO ₂ or Nb ₂ O ₅ . A protective layer 13 is provided over the entire assembly. In this embodiment the second current source lead is not grounded.

Alternatively, one or several of the current source leads 14, 16, 17 or 19 can be constructed such that they can be used as inductive elements, so that the circuit configuration includes inductors as well as diodes, MOS capacitors and resistors, alternatively having, for example, a helical A two-dimensional or three-dimensional MEMS (“Micro-Electro-Mechanical System”) inductor with eg a helical structure can be provided on the protective layer 13 and can be integrated with the circuit configuration via the first and/or second current source leads 14 , 16 .

The finished electronic components can be equipped with, for example, standard semiconductor housings, flip-chip housings, plastic housings, chip-scale packages or ceramic housings. Electrical contact of electronic components may be affected by wire bonds or bumps. These bumps may include, for example, NiV/Cu/(Pb _0.35 Sn _0.65 ), NiV/Cu(Pb _0.4 Sn _0.6 ), NiCr/Cu/Ni/Au, or other material or lead-free material combinations.

Fig. 4 shows a possible circuit configuration of a network with at least one diode D, resistor R and MOS capacitor C _MOS . Resistor R is present between input 15 and output 18 . Diode D is located between input 15 and ground. The first connection terminal of the MOS capacitor C _MOS is located between the input 15 and the resistor R. The second connection terminal of the MOS capacitor C _MOS is grounded. For n, it is correct that n=1, 2, 3, 4, . . . ∞. For m, depending on the structure of the MOS capacitor, it is correct that m=1, 2, 3, 4, . . . ∞. For a MOS capacitor with a single stack structure, such as that shown in FIG. 2, it is true that m=1. For a MOS capacitor with a double stack structure, such as that shown in Fig. 1, it is true that m=2. For a MOS capacitor with a multi-stack structure, m=3, 4, . . . ∞.

Diode D, resistor R and MOS capacitor C _MOS may assume different, alternative configurations.

FIG. 5 shows a possible circuit configuration of a network with at least one diode D, a resistor R and a MOS capacitor C _MOS and a further capacitor _CA. Resistor R is located between input 15 and output 18 . An additional capacitor _CA is present between input 15 and resistor R. Diode D is connected between input 15 and ground. The first connection terminal of the capacitor C _MOS is located between the input 15 and the further capacitor _CA. The second connection terminal of the capacitor C _MOS is grounded. For n, it is correct that n=1, 2, 3, 4, . . . ∞. For m, depending on the structure of the MOS capacitor, m=1, 2, 3, 4, . . . ∞.

Diode D, resistor R, MOS capacitor C _MOS and further capacitor _CA can also have different, alternative configurations.

Example

The electronic component shown in FIG. 1 with the circuit configuration shown in FIG. 4 comprises a semiconductor substrate 1 of Si, using B as a dopant of the first doping type with a first doping concentration n1, wherein FIG. 4 The circuit arrangement shown comprises a resistor R arranged between the input 15 and the output 18 of the circuit arrangement, a MOS capacitor _CMOS arranged between the input 15 and ground, and a pn diode D arranged between the input 15 and ground. The semiconductor substrate 1 has a first semiconductor region 2 comprising Si using B as a dopant of a first doping type with a second doping concentration n2. The doping concentration n1 is greater than the doping concentration n2. A smaller second semiconductor region 3 is present in each first semiconductor region 2 , comprising Si using P as a dopant of the second doping type with a third doping concentration n3. An insulating layer 4 of SiO ₂ is provided on the semiconductor substrate 1 .

The insulating layer 4 is broken in some regions. In these regions, a first oxide layer 5 of SiO ₂ appears on the semiconductor substrate 1 . A first dielectric layer 6 of Si ₃ N ₄ is located on the oxide layer 5 . A first conductive layer 7 of polysilicon is located on the first dielectric layer 6 and a second oxide layer 8 of SiO ₂ is provided on the first conductive layer 7 . A second dielectric layer 9 of Si ₃ N ₄ is provided on the second oxide layer 8 . A first layer 10 having a resistance value and made of β-tantalum is provided on the second dielectric layer 9 .

A third dielectric layer 11 of Si ₃ N ₄ appears on the insulating layer 4 and has a resistance value in some regions and a second layer 12 made of β-tantalum appears on the third dielectric layer 11 . A protective layer 13 of Si ₃ N ₄ is provided over the entire assembly.

The second semiconductor region 3 of the pn diode is electrically connected to the input 15 of the circuit arrangement and is electrically connected to the first conductive layer 7 via the first current source lead 14 . The first current source lead 14 comprises a layer sequence of a third resistive layer 20 of β-tantalum and Si-doped Al as a layer of a well-conducting material 21 . The first layer 10 having a resistance value is grounded via the second current source lead 16 . The first conductive layer 7 is structured so as to partially overlap the second layer 12 having a resistance value. The second layer 12 having a resistance value is electrically connected to the output 18 of the circuit arrangement through a third current source lead 17 of Al doped with Si. The semiconductor substrate 1 is grounded via a fourth current source lead 19 comprising a fourth layer 22 having a resistance value and made of β-tantalum and Al doped with Si as good conductive material 23 .

Such a circuit configuration is used as a low-pass filter in mobile phone applications.

Claims (7)

1. one kind has input (15) and exports the integrated circuit of (18), comprising:

Semiconductor substrate (1), described Semiconductor substrate comprise the dopant of first doping type with first doping content (n1) and have at least one active element;

At least one capacitor that comprises first electrode, second electrode and first dielectric layer (6); With

At least one resistor, described resistor comprise the material that is selected from following: β-tantalum, Ta _xN _Y(0＜x≤1,0＜y≤1), Ta _1-x-ySi _xN _y(0＜x≤1,0＜y≤1), Ta _1-x-yAl _xN _y(0＜x≤1,0＜y≤1), Ni _xCr _y(0＜x≤1,0＜y≤1), Ni _xCr _xAl _z(0＜x≤1,0＜y≤1,0＜z≤1), Si _xCr _xO _z(0＜x≤1,0＜y≤1,0＜z≤1), Si _xCr _xN _z(0＜x≤1,0＜y≤1,0＜z≤1), Ti _xW _y(0＜x≤1,0＜y≤1), Ti _xW _yN _z(0＜x≤1,0＜y≤1,0＜z≤1), Ti _xN _y(0＜x≤1,0＜y≤1) and Cu _xNi _y(0＜x≤1,0＜y≤1), described resistor and mos capacitance device are electrically coupled to active element, it is characterized in that:

Described active element is the diode as overvoltage protective device, described diode is formed by first semiconductor regions (2) of the dopant of first doping type with second doping content (n2) and second semiconductor regions (3) of dopant with second doping type of the 3rd doping content, wherein said diode by first current source go between (14) be electrically connected to input (15), and described second doping content (n2) is lower than first doping content (n1) of substrate (1);

Be provided at the insulating barrier (4) on the Semiconductor substrate (1), described insulating barrier interrupts in some zone, wherein said capacitor is restricted to the mos capacitance device, the Semiconductor substrate of described mos capacitance device (1) is as first electrode, described Semiconductor substrate (1) is by the 4th current source lead-in wire (19) ground connection, between described Semiconductor substrate (1) and first dielectric layer (6) first oxide skin(coating) (5) is set, second electrode of described capacitor is coupled to described first current source lead-in wire (14);

Be positioned at the 3rd dielectric layer (11) on the insulating barrier (4), in some zones on described the 3rd dielectric layer, be provided with the second layer (12) forming described resistor with resistance value, described resistor be electrically coupled to described capacitor second electrode and by the 3rd current source go between (17) be connected to output (18); And

Be arranged on the protective layer (13) on the entire circuit.

2. integrated circuit according to claim 1, wherein said mos capacitance device is a kind of single laminated construction with second current source lead-in wire, this second current source lead-in wire forms and is connected to first current source lead-in wire and resistor.

3. integrated circuit according to claim 1, wherein said mos capacitance device is a kind of double stack construction with first conductive layer, this first conductive layer is as second electrode and be arranged to connect first current source lead-in wire and resistor.

4. integrated circuit according to claim 1, wherein:

Setting has the other capacitor of first electrode and second electrode, is provided with between this first electrode and second electrode as dielectric the 4th dielectric layer (24);

Described mos capacitance device is a kind of single laminated construction with second current source lead-in wire, and this second current source lead-in wire forms and is connected to first current source lead-in wire;

Described second current source lead-in wire is constructed to make it to be used as second electrode of other capacitor extraly;

Described second resistive layer (12) is constructed to make it on the one hand as resistor, is used as first electrode of other capacitor on the other hand.

5. integrated circuit according to claim 1 further comprises first resistive layer (10) that is positioned at described first dielectric layer (6) top, and described first resistive layer (10) is with second electrode of described mos capacitance device.

6. integrated circuit according to claim 1, one of them or several current source lead-in wire (14,16,17,19) are constructed to make them to be used as inductance element, to limit inductance.

7. integrated circuit according to claim 1 further comprises the MENS inductance, and described MENS inductance is positioned on the protective layer and has two dimension or three-dimensional structure, and integrated by first and/or second current source lead-in wire (14,16) and circuit arrangement.

Images