CN100438036C - Memory device and method for fabricating the same - Google Patents

Abstract

Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Description

Memory device and manufacturing method thereof

technical field

The present invention relates to a memory device and a manufacturing method thereof, and more particularly, to a memory device capable of improving data retention time and a manufacturing method thereof.

Background technique

As semiconductor devices have been increasingly miniaturized, the size of each pattern has been gradually reduced. Especially in memory devices such as dynamic random access memory (DRAM) devices, due to large-scale integration, the length of the gate electrode is drastically reduced in proportion to the reduction in transistor size in the cell region, and as a gate As a result of the reduction in electrode size, the junction of the source and drain has played an important role in the electric field and potential applied to the body of the transistor in the cell.

FIG. 1 is a cross-sectional view illustrating the structure of a conventional memory device.

As shown, a field oxide layer 120 for isolating device elements is formed in a predetermined area of the substrate 110 . Then, the gate insulating layer 130, the first gate conductive layer 140, the second gate conductive layer 150 and the gate hard mask layer 160 are sequentially formed on the substrate 110, and are sequentially subjected to gate mask processing and etching processing, thereby A plurality of gate structures 155 are obtained.

Impurities are then ion-implanted to form a plurality of bit line contact junctions 170A and a plurality of storage node contact junctions 170B, and then spacers 171 are formed on each sidewall of the gate structure 155 . Then, a plurality of bit line contact plugs 190A connected to the bit line contact junction 170A and a plurality of storage node contact plugs 190B connected to the storage node contact junction 170B are formed. The bit line contact plug 190A and the storage node contact plug 190B are respectively used to connect to a bit line and a storage node. It should be noted that FIG. 1 only illustrates a single bitline contact junction and a single bitline contact plug.

However, conventional memory devices have the problem of short channel effect, that is, since the gate electrode is shortened, the channel region is susceptible to voltages provided by the gate structure, depletion layers of source and drain junctions, electric fields, and potentials. As a result of this unfavorable short-channel effect, the threshold voltage is drastically reduced, thereby making it difficult to control the threshold voltage of the memory device.

Furthermore, since the storage device has been miniaturized, high-concentration ions must be implanted into the bit line contact junction 170A and the storage node contact junction 170B. However, due to excessive ion implantation for obtaining a high doping concentration, the edge region A of the storage node contact junction 170B in the cell region will have a high level of electric field, and thus, the junction leakage current at the junction portion of the storage node contact junction 170B increases. . Such an increase in junction leakage current causes a decrease in data retention time, that is, a degradation in recovery characteristics of the memory device.

Contents of the invention

Accordingly, an object of the present invention is to provide a memory device and a method of manufacturing the same that can increase a data retention time by reducing junction leakage current generated at a storage node contact junction.

According to an aspect of the present invention, there is provided a memory device, which includes: a substrate provided with a trench; a bit line contact junction formed under the trench; a plurality of storage node contact junctions formed outside the trench; gate structures, each gate structure is formed on the substrate between the bit line contact and a storage node contact.

According to another aspect of the present invention, there is provided a memory device, which includes: a substrate provided with a trench; a first contact junction formed under the trench; a plurality of second contact junctions formed outside the trench; gate structures, each gate structure is formed on the substrate disposed between the first contact junction and a second contact junction; the first contact junction formed on the first contact junction by filling the space generated between the gate structures a contact plug; and a plurality of second contact plugs formed on the second contact junction by filling a space generated between the gate structures.

According to still another aspect of the present invention, there is provided a method for manufacturing a memory device, comprising the steps of: etching part of the substrate to obtain trenches; forming a plurality of gate structures, so that each part of the gate structures is disposed in the trenches; inside the trench; using the gate structure as a mask to perform ion implantation so as to form a first contact junction under the trench and form a plurality of second contact junctions outside the trench; and form a first contact plug on the first contact junction and A plurality of second contact plugs are formed on the corresponding contact junctions.

Description of drawings

The above and other objects and features of the present invention will be better understood through the description of the preferred embodiments given below in conjunction with the accompanying drawings, wherein:

FIG. 1 is a cross-sectional view illustrating the structure of a conventional memory device.

FIG. 2 is a cross-sectional view illustrating the structure of a memory device manufactured according to a first embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a memory device according to a first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating the structure of a memory device according to a second embodiment of the present invention.

5 is a cross-sectional view illustrating the structure of a memory device according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating the structure of a memory device according to a fourth embodiment of the present invention.

7A to 7G are cross-sectional views illustrating a method of manufacturing a memory device according to a fourth embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating the structure of a memory device according to a fifth embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating the structure of a memory device according to a sixth embodiment of the present invention.

Detailed ways

A memory device and a manufacturing method thereof according to preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a cross-sectional view illustrating the structure of a memory device according to a first embodiment of the present invention.

As shown, a field oxide layer 220 is formed in a substrate 210, and a trench 200 is formed in a predetermined region of the substrate. A first contact junction 270A is formed in the substrate 210 below the trench 200 , and a plurality of second contact junctions 270B are formed in the substrate 210 outside the trench 200 . It should be noted that although many first contact junctions 270A are formed, only a single first contact junction 270A is illustrated in FIG. 2 .

A plurality of gate structures 255 are formed on each portion of the substrate 210 between the first contact junction 270A and the second contact junction 270B. Here, each gate structure includes a first insulating layer 230, a polysilicon layer 240, a metal layer 250, and a second insulating layer 260 for a hard mask. Furthermore, respective portions of the selected gate structures 255 are disposed within the trenches 200 , and the polysilicon layer 240 and the metal layer 250 of those gate structures 255 are recessed where the trenches 200 are formed.

A spacer 271 is formed on each sidewall of the gate structure 255 . A first contact plug 290A is formed on the first contact junction 270A and fills a space generated between the gate structures 255 formed on the trench 200 . A plurality of second contact plugs 290B are respectively formed on the second contact junctions 270B, and fill corresponding spaces generated between the gate structures 255 formed outside the trenches 200 .

Although not illustrated, the bit line is connected to the first contact junction 270A via the first contact plug 290A, and the storage node is connected to the second contact junction 270B via the second contact plug 290B. That is, the first contact plug 290A and the second contact plug 290B are respectively a bit line contact plug and a storage node contact plug, and the first contact junction 270A and the second contact junction 270B are respectively a bit line contact junction and a storage node contact junction.

As mentioned above, in the memory device manufactured according to the first embodiment of the present invention, the bit line contact junction of the transistor in the cell region is formed in the trench, and the storage node contact junction is formed outside the trench. Many channels are formed between every two bit line contact junctions and storage node contact junctions. Therefore, the sidewalls of the trench constitute the channel, and as a result, the channel length of the transistor in the cell is extended. Compared with the conventional memory device, every two storage nodes contact the increase between the junction and the channel region. Thus, the leakage current level of the storage node contact junction is reduced, thereby increasing the data retention time.

3A to 3F are cross-sectional views illustrating a method of manufacturing a memory device according to a first embodiment of the present invention. Here, the same reference numerals described in FIG. 2 are also used in these figures.

As shown in FIG. 3A , a field oxide layer 220 is formed on a silicon-based substrate 210 .

As shown in FIG. 3B , predetermined portions of the substrate 210 are selectively etched to form trenches 200 . Although the depth D of the trench 200 varies depending on design rules, the depth of the trench 200 is preferably in the range of about 20 nm to about 150 nm.

As shown in FIG. 3C , a first insulating layer 230 made of silicon oxide is formed on the above completed substrate structure, and a polysilicon layer 240 and a metal layer 250 are sequentially formed thereon. At this time, the polysilicon layer 240 has a concave shape consistent with the shape of the trench 200 .

As shown in FIG. 3D, a metal layer 250 is formed on the polysilicon layer 240 by using a material selected from metal and metal silicide. At this time, the metal layer has a recessed portion where the polysilicon layer 240 is recessed. Then, a second insulating layer 260 for a hard mask is formed on the metal layer 250 . Typically, the second insulating layer 260 is made of silicon nitride.

As shown in FIG. 3E , through gate masking and etching, the first insulating layer 230 , the polysilicon layer 240 , the metal layer 250 and the second insulating layer 260 are selectively etched, thereby obtaining a plurality of gate structures 255 . In order to restore damage to the substrate structure during etching and improve characteristics of the first insulating layer 230, a re-oxidation process may be performed. Afterwards, ion implantation is performed by using the gate structure 255 as a mask to form a first contact junction 270A in the substrate 210 located below the trench 200 , and form a plurality of second contact junctions 270A in the substrate 210 located outside the trench 200 . Junction 270B.

As shown in FIG. 3F , a spacer 271 is formed on each sidewall of the gate structure 255 . At this time, the spacer 271 is formed using nitride or oxide. Then, a conductive layer for a contact plug is formed over the gate structure 255, which is continuously applied with a CMP process until the conductive layer is exposed. After the CMP process, a first contact plug 290A is formed on the first contact junction 270A, and at the same time, a plurality of second contact plugs 290B are formed on the second contact junction 270B. Although a single first contact junction 270A and first contact plug 290A are illustrated, it should be noted that there are multiple first contact junctions 270A and first contact plug 290A.

Although not illustrated, the first contact junction 270A is connected to the bit line through the first contact plug 290A, and the second contact junction 270B is connected to the storage node through the second contact plug 290B. However, the first contact junction 270A and the second contact junction 270B may be respectively connected to the bit line and the storage node without using the first contact plug 290A and the second contact plug 290B.

According to the first embodiment of the present invention, the first contact junction 270A connected to the bit line is formed in the substrate in the trench 200, so the sidewall of the trench 200 constitutes the channel region of the transistor in the cell region.

FIG. 4 is a cross-sectional view illustrating the structure of a memory device according to a second embodiment of the present invention.

Here, the memory device according to the second embodiment includes the same configuration elements described in FIG. 2, and therefore, detailed descriptions about such configuration elements will be omitted. The memory device manufactured according to the second embodiment differs from the memory device manufactured according to the first embodiment in that the side wall B of the trench 300 is formed perpendicular to the surface of the recessed portion of the substrate 310 , and the plurality of gate structures 355, the first contact junction 370A and the second contact junction 370B are arranged such that the portion of the substrate 310 where the sidewall B of the trench 300 is arranged is arranged at the center of each channel region.

5 is a cross-sectional view illustrating the structure of a memory device according to a third embodiment of the present invention.

Here, the memory device according to the third embodiment of the present invention includes the same configuration elements described in FIG. 2, and therefore, detailed descriptions about such configuration elements will be omitted. The memory device fabricated according to the third embodiment differs from the memory device shown in FIG. 2 in that the sidewall C of the trench 400 is positively sloped, ie narrows as it extends toward the bottom of the trench 400 .

FIG. 6 is a cross-sectional view illustrating the structure of a memory device according to a fourth embodiment of the present invention.

As shown in the figure, a field oxide layer 620 is formed in a substrate 610 , and a trench 600 is formed in a predetermined area of the substrate 610 . A first contact junction 670A is formed in the substrate 610 below the trench 600 , and a plurality of second contact junctions 670B are formed in the substrate 610 outside the trench 600 . It should be noted that although a plurality of first contact junctions 670A are formed, only a single first contact junction 670A is illustrated in FIG. 6 .

A plurality of gate structures 655 are formed on portions of the substrate 610 disposed between the first contact junction 670A and the second contact junction 670B. Here, each gate structure 655 includes a first insulating layer 630, a planarized polysilicon layer 640A, a metal layer 650, and a second insulating layer 660 for a hard mask. Again, respective portions of selected gate structures 655 are disposed within trenches 600 . A spacer 671 is formed on each sidewall of the gate structure 655 . A first contact plug 690A is formed on the first contact junction 670A while filling a space generated between the gate structures 655 partially disposed within the trench 600 . A plurality of second contact plugs 690B are formed on the corresponding second contact junctions 670B while filling corresponding spaces generated between the gate structures 655 formed outside the trenches 600 .

Although not illustrated, the bit line is connected to the first contact junction 670A through the first contact plug 690A, and the storage node is connected to the second contact junction 670B through the second contact plug 690B. That is, the first contact plug 690A and the second contact plug 690B are respectively a bit line contact plug and a storage node contact plug, and the first contact junction 670A and the second contact junction 670B are respectively a bit line contact junction and a storage node contact junction.

As described above, in the memory device manufactured according to the fourth embodiment of the present invention, the bit line contact junction of the transistor in the cell region is formed inside the trench, while the storage node contact junction is formed outside the trench. Many channels are formed between every two bit line contact junctions and storage node contact junctions. Therefore, the sidewalls of the trench become part of the channel, and as a result, the channel length of the transistor in the cell is extended. Compared with conventional memory devices, the distance between every two storage node contact junctions and the channel region is increased. Thus, the leakage current level at the storage node contact junction is reduced, thereby increasing the data retention time.

7A to 7G are cross-sectional views illustrating a method of manufacturing a memory device according to a fourth embodiment of the present invention. Here, the same reference numerals described in FIG. 6 are used for the same configuration elements in these figures.

As shown in FIG. 7A , a field oxide layer 620 is formed on a silicon-based substrate 610 .

As shown in FIG. 7B , predetermined portions of the substrate 610 are selectively etched to form trenches 600 . Although the depth D of the trench 600 varies according to design rules, the depth D of the trench 600 is preferably in the range of about 20 nm to 150 nm.

此时，多晶硅层640具有与沟槽600外形一致的凹陷外形。亦即，多晶硅层640具有凹陷部分，其导致随后将被形成的金属层在多晶硅层640被凹陷的相同位置处被凹陷。As shown in FIG. 7C, a first insulating layer 630 made of silicon oxide is formed on the above completed substrate structure, and a polysilicon layer 640 is formed thereon. Preferably, the polysilicon layer 640 has a thickness equal to or less than about

At this time, the polysilicon layer 640 has a concave shape consistent with the shape of the trench 600 . That is, the polysilicon layer 640 has a recessed portion, which causes a metal layer to be formed subsequently to be recessed at the same position where the polysilicon layer 640 is recessed.

However, due to the properties of the metal used, voids are created into which the polymer produced in the subsequent etching process penetrates. As a result, polymer penetration may prevent etching from being performed effectively. To solve this problem, a different method is proposed in the first embodiment of the present invention, and the proposed method will be described in detail with reference to the accompanying drawings.

As shown in FIG. 7D , before forming the metal layer on the polysilicon layer 640 , a chemical mechanical polishing (CMP) process is performed to remove the trench 600 , so as to obtain a planarized polysilicon layer 640A. At this time, the polishing pad used for the above CMP treatment is made of high molecular polymer, and the average size of the polishing particles is preferably in the range of about 10 nm to about 1000 nm. Furthermore, the surface of the polishing pad is formed into a sponge structure with a pore diameter of less than about 100 μm, and the concentration of the slurry polishing particles is preferably in the range of about 0.5% by weight to 5% by weight.

As shown in FIG. 7E, the aforementioned metal layer 650 based on metal or metal silicide is formed on the planarized polysilicon layer 640A. In particular, the metal layer is preferably formed using a material selected from tungsten or a tungsten compound. Thereafter, a second insulating layer 660 for a hard mask is formed on the metal layer 650 . Typically, the second insulating layer 660 is made of silicon nitride.

As shown in FIG. 7F , the first insulating layer 630 , the planarized polysilicon layer 640A, the metal layer 650 and the second insulating layer 660 are selectively etched through gate masking and etching to obtain a plurality of gate structures 655 . In order to restore damage to the substrate structure in the etching process and improve characteristics of the first insulating layer 660, a re-oxidation process may be performed. Thereafter, an ion implantation process is performed using the gate structure 655 as a mask to form a first contact junction 670A in the substrate 610 below the trench 600 and to form a plurality of second contact junctions in the substrate 610 outside the trench 600. 670B.

As shown in FIG. 7G , a spacer 671 is formed on each sidewall of the gate structure 655 . At this time, the spacer 671 is made using nitride or oxide. Thereafter, a conductive layer for a contact plug is formed on the gate structure 655 and then CMP processing is continuously performed thereon until the conductive layer is exposed. After the CMP process, a first contact plug 690A is formed on the first contact junction 670A, while a plurality of second contact plugs 690B are formed on the second contact junction 670B. Although a single first contact junction 270A and first contact plug 290A are illustrated, it should be noted that there are multiple first contact junctions 670A and first contact plugs 690A.

Although not illustrated, the first contact junction 670A is connected to the bit line through the first contact plug 690A, and the second contact junction 670B is connected to the storage node through the second contact plug 690B. Of course, the first contact junction 670A and the second contact junction 670B can be respectively connected to the bit line and the storage node without using the first contact plug 690A and the second contact plug 690B.

According to the fourth embodiment of the present invention, the first contact junction 670A connected to the bit line is formed in the substrate under the trench 600, so the sidewall of the trench 600 constitutes the channel of the transistor in the cell region.

FIG. 8 is a cross-sectional view illustrating the structure of a memory device according to a fifth embodiment of the present invention.

Here, the memory device according to the fourth embodiment includes the same configuration elements described in FIG. 6, so a detailed description about such configuration elements will be omitted. However, the memory device fabricated according to the fifth embodiment differs from the memory device fabricated according to the fourth embodiment in that the side wall B of the trench 700 is formed perpendicular to the surface of the recessed portion of the substrate 710 and a plurality of The gate structure 755, the first contact junction 770A and the second contact junction 770B are arranged such that the portion of the substrate 710 where the sidewall B is arranged is arranged in the center of each channel region.

FIG. 9 is a cross-sectional view illustrating the structure of a memory device according to a sixth embodiment of the present invention.

Here, the memory device according to the sixth embodiment of the present invention includes the same configuration elements described in FIG. 6 . However, the difference between the memory device fabricated according to the sixth embodiment and the memory device shown in FIG. 6 is that the sidewall C of the trench 800 is positively inclined, ie, narrows toward the bottom of the trench 800 .

According to the first to sixth embodiments of the present invention, a predetermined portion of the substrate connected to the bit line is recessed, so that the sidewall of the recessed portion of the substrate becomes a part of the channel. As a result, the length of the channel is extended, which in turn leads to a reduction in leakage current at the storage node contact junction. Therefore, the data retention time of the memory device can be increased. In particular, the second and third embodiments and the fifth and sixth embodiments provide the effect of improving the tolerance with respect to misalignment during the gate patterning process.

This application contains subject matter related to two Korean Patent Applications No. KR2004-0058871 and 2004-0059670 filed with the Korean Patent Office on Jul. 27, 2004 and Jul. 29, 2004, respectively, the entire contents of which are hereby incorporated by reference as refer to.

Although the invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various modifications can be made without departing from the spirit and scope of the invention as defined in the following claims: changes and modifications.

Explanation of representative symbols of main parts

110, 210...810 Substrate

120, 220...820 field oxide layer

130, 230...830 The first insulating layer

140, 240...840 polysilicon layer

150, 250...850 metal layer

155, 255...855 grid structure

160, 260...860 second insulation layer

170A, 270A...870A first contact junction

170B, 270B...870B second contact junction

171, 271...871 spacers

190A, 290A...890A first contact plug

190B, 290B...890B Second contact plug.

Claims (27)

1. memory device comprises:

Substrate with groove;

Be formed on the bit line contact knot of described beneath trenches;

Be formed on the outer a plurality of storage node contact knots of described groove; And

A plurality of grid structures, its each be formed on the substrate between described bit line contact knot and the storage node contact knot.

2. memory device as claimed in claim 1, wherein said groove has sidewall, and described each sidewall is the part of raceway groove.

3. memory device as claimed in claim 1, the sidewall slope of wherein said groove makes described groove narrow down with downward bottom near described groove.

4. memory device as claimed in claim 1, the sidewall of wherein said groove is formed the surface perpendicular to the sunk part of described substrate.

5. memory device as claimed in claim 1, wherein said grid structure, described bit line contact knot and described storage node contact knot are provided so that the substrate of position at each sidewall place of described groove partly is arranged at the center in respective channels district.

6. memory device as claimed in claim 1, wherein each described grid structure second insulating barrier of comprising first insulating barrier, polysilicon layer, metal level and being used for hard mask.

7. memory device as claimed in claim 1, wherein each described grid structure comprises polysilicon layer, the metal level of first insulating barrier, complanation and is used for second insulating barrier of hard mask.

8. memory device as claimed in claim 6, wherein said first insulating barrier and described second insulating barrier use Si oxide and silicon nitride to form respectively.

9. memory device as claimed in claim 7, wherein said first insulating barrier and described second insulating barrier use Si oxide and silicon nitride to form respectively.

10. memory device comprises:

Substrate with groove;

Be formed on the first contact knot of described beneath trenches;

Be formed on the outer a plurality of second contact knots of described groove;

A plurality of grid structures, each described grid structure are formed on the substrate between the described first contact knot and the described second contact knot;

First contact plug, its by be filled in the space that produces between the described grid structure be formed on described first the contact tie; And

A plurality of second contact plugs, its by be filled in the space that produces between the described grid structure be formed on described second the contact tie.

11. the memory device as claim 10 further comprises:

Bit line, it contacts knot via described first contact plug and is connected with described first; And

A plurality of storage nodes, it contacts knot via described second contact plug respectively and is connected with described second.

12. as the memory device of claim 10, wherein said groove has sidewall, each described sidewall is the part of raceway groove.

13. as the memory device of claim 10, the sidewall slope of wherein said groove makes described groove narrow down with downward bottom near described groove.

14. as the memory device of claim 10, the sidewall of wherein said groove is formed the surface perpendicular to the sunk part of described substrate.

15. as the memory device of claim 10, wherein said grid structure, the described first contact knot and the described second contact knot are provided so that the substrate at each place, sidewall position of described groove partly is arranged at the center in respective channels district.

16. as the memory device of claim 10, each described grid structure second insulating barrier of comprising first insulating barrier, polysilicon layer, metal level and being used for hard mask wherein.

17. as the memory device of claim 10, wherein each described grid structure comprises polysilicon layer, the metal level of first insulating barrier, complanation and is used for second insulating barrier of hard mask.

18. as the memory device of claim 16, wherein said first insulating barrier and described second insulating barrier use Si oxide and silicon nitride to form respectively.

19. as the memory device of claim 17, wherein said first insulating barrier and described second insulating barrier use Si oxide and silicon nitride to form respectively.

20. as the memory device of claim 10, further comprise a plurality of septs, it is formed on each sidewall of described grid structure.

21. a method that is used to make memory device, included step is:

The etching part substrate is to obtain groove;

Form a plurality of grid structures, make each part of described grid structure be set in the described groove;

Use described grid structure to carry out ion and inject processing to form the first contact knot in described beneath trenches and to become a plurality of second contacts to tie in described trench profile as mask; And

Tie formation first contact plug and tie a plurality of second contact plugs of formation in described first contact in corresponding contact.

22. as the method for claim 21, the step that wherein forms described a plurality of grid structures may further comprise the steps:

On described substrate, form first insulating barrier, polysilicon layer, metal level and second insulating barrier in regular turn; And

Come described first insulating barrier of patterning, described polysilicon layer, described metal level and described second insulating barrier by carrying out mask process and etch processes.

23. as the method for claim 21, the step that wherein forms described a plurality of grid structures may further comprise the steps;

On described substrate, form first insulating barrier;

On described first insulating barrier, form polysilicon layer;

Carry out planarization process to obtain the polysilicon layer of complanation;

On the polysilicon layer of described complanation, form metal level;

On described metal level, form second insulating barrier; And

Come described first insulating barrier of patterning, the polysilicon layer of described complanation, described metal level and described second insulating barrier by using grid mask process and etch processes.

24. as the method for claim 21, the step that wherein forms described first contact plug and described second contact plug comprises the following steps:

On described grid structure, be formed for the conductive layer of contact plug; And

Described conductive layer is carried out chemical mechanical polish process till described second insulating barrier appears, obtain described first contact plug and described a plurality of second contact plug thus.

25. the method as claim 21 further comprises: the step that before carrying out described ion injection processing, described grid structure is reoxidized processing.

26. as the method for claim 21, wherein said first contact knot and the described second contact knot are formed bit line contact knot and storage node contact knot respectively.

27., after the step that forms described first contact plug and described a plurality of second contact plugs, further comprise the steps: as the method for claim 21

Form bit line, it contacts knot via described first contact plug and is connected with described first; And

Form a plurality of storage nodes, it contacts knot via described second contact plug respectively and is connected with described second.

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