CN100437830C - shift register circuit - Google Patents

Abstract

The invention discloses a shift register circuit, which is provided with a plurality of stages of shift buffer units and generates a sampling signal to a corresponding data latch circuit according to a signal provided by a timing control circuit. The 1 st level shift buffer unit of the shift register circuit is provided with a de-energizing circuit and a sampling circuit, receives the signal of the timing control circuit, captures a correct sampling signal and outputs the sampling signal to the corresponding data latch circuit and the next level shift buffer unit; the de-energizing circuit of the 1 st level shift buffer unit receives the sampling signal of the 2 nd level shift buffer unit and stops the action of the sampling circuit of the 1 st level shift buffer unit.

Description

shift register circuit

technical field

The invention relates to a shift register circuit (Shift Register) used in a display driving circuit, in particular to a shift register circuit capable of improving the incompleteness of output timing signals.

Background technique

Liquid crystal display (LCD) has gradually replaced traditional image tube (CRT) displays due to its advantages of lightness, lightness, power saving, and radiation-free, and is widely used in desktop computers, personal digital assistants, notebook computers, digital cameras and mobile phones. Electronic products such as telephones. With the maturity of thin film transistor manufacturing and packaging technology, and in order to meet the requirements of large-size display screens, signal lines for driving integrated circuit chips (IC) and providing data signals, clock signals or control signals are fabricated on a liquid crystal display panel. The driving circuit of the liquid crystal display panel is installed on the edge of the display to provide a smaller packaging area and improve the structural strength.

Active Matrix Liquid Crystal Display (AMLCD) uses an electric field to control the light transmittance of liquid crystals to achieve the purpose of displaying images. Please refer to FIG. 1 , which is a circuit structure diagram of an active matrix liquid crystal display. The display circuit structure 1 includes a driving system 10 and a liquid crystal display panel 100 .

Wherein, the drive system 10 has a timing control circuit (Timing Controller) 12, a data drive circuit (Data Driver) 14, a scan drive circuit (Scan Driver) 16, a display signal input terminal (R/G/B Data) 18. Wherein, the timing control circuit 12 provides the horizontal clock signal HCK and the horizontal start signal HST to the data driving circuit 14, meanwhile, also generates the vertical clock signal VCK and the vertical start signal VST to the scanning driving circuit 16; the display signal input terminal 18 The display data D is sent to the data driving circuit 14 .

The data driving circuit 14 includes a shift register circuit (Shift Register) 142, multiple data latch circuits (Data Latch) 144, multiple DC/AC conversion circuits and buffer circuits (D/A Converter and Buffer) 146. Wherein, the shift register circuit has a multi-stage (Stage) shift buffer unit, receives the horizontal clock signal HCK and the horizontal start signal HST, generates a sampling signal (sampling signal) and outputs it step by step, and feeds it into the data latch circuit 144 in sequence , the DC/AC conversion circuit and the buffer circuit 146, and to the pixel components 102 in the same row in the pixel matrix.

The liquid crystal display panel 100 has a pixel array (pixel array), and each pixel element 102 in the pixel array is electrically connected to a thin film transistor 104, and the source of the thin film transistor 104 is electrically connected to the data driving circuit 14, and the gate is electrically connected to the To the scan driving circuit 16 to act as a switch to control the operation of the pixel element 102 .

Please refer to FIG. 2 , which is a schematic diagram of a typical shift register circuit. The shift register circuit 142 has a multi-stage shift register unit, wherein the shift register unit _SR1 of the first stage is controlled by the inverted horizontal clock signal XHCK and the horizontal start signal HST output by the timing control circuit 12 to generate a sampling The signal S ₁ is fed into the data latch circuit 144 and the shift register unit SR ₂ of the second stage; the shift register unit SR _N of the Nth stage receives the sampling signal S _{N-1 of the shift register unit of the N-1} stage, and inverts Controlled by the horizontal clock signal XHCK and the horizontal clock signal HCK, a sampling signal _SN is generated and fed into the data latch circuit 144 and the N+1-th shift register unit SR _N+1 .

Please refer to FIG. 3A and B at the same time. FIG. 3A is a timing diagram of the horizontal clock signal, the inverted horizontal clock signal and the horizontal start signal initially output by the timing control circuit; FIG. 3B is the horizontal clock signal arriving at the data driving circuit, Timing diagram of inverted horizontal clock signal and horizontal start signal. As shown in Figure 3A, the clock signals HCK, XHCK and the start signal HST are a synchronous clock when they are initially output. Under ideal conditions, this synchronous clock will maintain this state and input to the data drive circuit. Meanwhile, the data driving circuit can pick up a 50% cycle inverted horizontal clock signal XHCK as the duty cycle of the control signal.

But in reality, the output synchronous clock reaches the data drive circuit through different transmission paths, and because each path has different parasitic capacitance and parasitic resistance, the original synchronous signal at the time of output will change when it reaches the data drive circuit. It is an asynchronous phenomenon, as shown in Fig. 3B. Therefore, when the data driving circuit is about to capture signals at time points _t1 to _t1 ', because the horizontal start signal HST is not synchronized with the horizontal clock signal HCK, the correspondingly captured inverted horizontal clock signal XHCK will no longer maintain 150 % of the cycle, this abnormal clock output (glitch) will cause malfunctions of many circuits using the clock signal as the reference clock signal, thereby affecting the normal operation of the system.

Please refer to FIG. 3C , which is a timing diagram of an input signal and an output signal of an ideal shift register circuit. The shift register circuit receives the horizontal start signal HST and the inverted horizontal clock signal XHCK, wherein the shift register unit SR ₁ of the first stage receives the start signal HST as a pulse input between the time point t and t', At the same time, the inverted clock signal XHCK is captured to generate a sampling signal S ₁ and output to the corresponding data latch circuit and the second-level shift register unit SR ₂ , and the subsequent shift register units of each level will sequentially output the sampling signals .

Please refer to FIG. 3D , which is a timing diagram of the input signal and output signal of the register circuit. Among them, the first-stage shift register unit SR ₁ receives the start signal HST as a pulse input between time points t ₁ and t ₁ ', and extracts the inverted clock signal X HCK, due to signal delay during transmission , at this time, the inverting acquisition signal is exactly 0 input, so a correct sampling signal output cannot be obtained, which seriously affects the accuracy of sampling and even the correctness of screen display.

In view of this, the present invention provides a design of a shift register circuit, which can improve the incompleteness of the output clock signal, make the display data sampling and data writing more accurate, and avoid the gap between the clock signal and the data driving circuit. Long-distance transmission causes the signal to be out of sync, resulting in the failure of the data drive circuit to operate normally.

Contents of the invention

The purpose of the present invention is to provide a shift register circuit, which can solve the problem of incomplete clock signal output by the traditional shift register circuit.

The invention discloses a shift register circuit, which has a multi-stage shift buffer unit, and generates a sampling signal to a corresponding data latch circuit according to a signal provided by a timing control circuit. Wherein, the shift register circuit includes a first-stage shift register unit, which is coupled to the timing control circuit and the corresponding data latch circuit, has a disable circuit and a sampling circuit, and receives signals provided by the timing control circuit , to capture a correct sampling signal and output it to the corresponding data latch circuit and the shift register unit of the next stage; and the shift register units from the second stage to the Nth stage each have a sampling circuit and are connected in series step by step And the second-level shift register unit is connected to the first-level shift register unit. The disabling circuit of the shift register unit of the first stage receives the sampling signal of the shift register unit of the second stage, and stops the operation of the sampling circuit of the shift register unit of the first stage.

A method for improving the asynchronous signal of a drive circuit of a display, the drive circuit has a timing control circuit, a shift register circuit and a scan drive circuit, wherein the shift register circuit consists of a multi-stage shift buffer unit and a plurality of latches The circuit is composed of a circuit, and the method includes: the timing control circuit provides a clock signal and a start signal; the first-stage shift register unit receives the clock signal and the start signal, and when the start signal is high, the first-stage shift register The unit extracts the next clock signal corresponding to the start signal as a sampling signal, so as to prevent the data driving circuit from being unable to operate normally due to incomplete sampling.

Description of drawings

Fig. 1 is an active matrix liquid crystal display circuit structure diagram;

2 is a schematic diagram of a typical shift register circuit;

3A is a timing diagram of each signal of the timing control circuit;

FIG. 3B is a timing diagram of signals arriving at the data driving circuit;

3C is a timing diagram of input and output signals of an ideal shift register circuit;

3D is a timing diagram of input and output signals of the shift register circuit;

4 is a schematic diagram of a shift register circuit structure according to an embodiment of the present invention;

FIG. 5A is a circuit diagram of a first-stage shift register unit according to an embodiment of the present invention;

FIG. 5B is a timing diagram corresponding to each node signal;

FIG. 6A is an ideal timing diagram of input and output signals of the first-stage shift register unit according to an embodiment of the present invention;

6B is a timing diagram of input and output signals of a shift register circuit according to an embodiment of the present invention;

FIG. 7A is a circuit diagram of a first-stage shift register unit according to an embodiment of the present invention;

FIG. 7B is a timing diagram corresponding to each node signal;

FIG. 8A is a circuit diagram of a first-stage shift register unit according to an embodiment of the present invention;

FIG. 8B is a timing diagram corresponding to each node signal;

9A is a timing diagram of an input signal and an output signal of a first-stage shift register unit according to an embodiment of the present invention;

FIG. 9B is a schematic timing diagram corresponding to each node signal; and

FIG. 10 is a flowchart of a method for synchronizing signals of a driving circuit according to an embodiment of the present invention.

Description of reference symbols

1 Display Circuit Structure 10 Drive System

102 pixel components 104 thin film transistors

100 liquid crystal display panel 16 scanning drive circuit

18 display signal input terminal 246 buffer circuit

12, 22 timing control circuit 14, 24 data drive circuit

142, 242 shift register circuit

144, 244 multiple data latch circuits

HST horizontal start signal VST vertical start signal

HCK horizontal clock signal XHCK horizontal inversion clock signal

VCK vertical clock signal XVXK vertical inversion clock signal

CK clock signal XCK inverted clock signal

AND gate ST start signal

VDD first power supply VSS second power supply

Q, Q ₁ , Q ₂ output signals

C, C ₁ , C ₂ clock trigger signal input terminal

D, D ₁ , D ₂ data input terminals R, R ₁ , R ₂ reset terminals

NOT ₁ , NOT ₂ inverter

DFF, DFF ₁ , DFF ₂ D-type flip-flop

S ₁ , S ₂ ,..., S _N sampling signal

SR ₁ , SR ₂ , ..., _SRN shift buffer unit

N ₁ , N ₂ , N ₃ , N ₄ , N ₅ , N ₆ , N ₇ transistors

t, t', t ₁ , t ₁ ', t ₂ , t ₂ ', t ₂ ", t ₃ , t ₃ ', t ₄ , t ₄ ', t ₅ , t ₆ , t ₇ , t ₈ time points

Detailed ways

The invention provides a shift register circuit design, especially a sampling signal related to the shift register circuit in the display data circuit. In the present invention, the duration of the initial signal is different, combined with the circuit design of the first-stage shift register unit, so as to control the shift register unit to output correct sampling signals. The structure of the display of the present invention is the same as that of FIG. 1 , so no more details are given here.

Please refer to FIG. 4 , which is a schematic diagram of a shift register circuit structure according to an embodiment of the present invention. The shift register circuit 24 has a multi-stage shift register unit, wherein the shift register unit SR ₁ of the first stage is controlled by the inverted clock signal XCK and the start signal ST output by the timing control circuit, and has a sampling circuit and a demultiplexing circuit. capable circuit. In an embodiment of the present invention, its start signal ST has two different effects on the sampling circuit of the first-stage shift register unit SR ₁ : one is that the start signal ST can be regarded as a trigger signal, thus acting as The duration (duration) of the start signal ST does not affect its sampling action, it simply triggers the sampling circuit of the first-stage shift register unit SR ₁ to make it capture a complete sampling signal; the other is based on the start The duration of the signal ST overlaps with the rising period of the inverted clock signal XCK to capture a complete sampling signal. Therefore, the duration of the start signal ST needs to be longer than one and half periods of the inverted clock signal XCK.

When the first-stage shift register unit SR ₁ generates a sampling signal S ₁ and feeds it into the data latch circuit and the second-stage shift register unit SR ₂ ; the second-stage shift register unit SR ₂ is received by the first-stage shift register Controlled by the unit sampling signal S ₁ , the inverted clock signal XCK and the clock signal CK, a sampling signal S ₂ is generated and fed into the data latch circuit, the disabling circuit of the first-stage shift register unit SR ₁ and the third-stage shift Inside cache unit SR ₃ . The sampling signal _S2 drives the disabling circuit of the first-stage shift register unit _SR1 to stop the sampling operation of the first-stage shift register unit _SR1 until the next sampling operation starts.

Please refer to FIG. 5A and B at the same time. FIG. 5A is a circuit diagram of the first-stage shift register unit in the first embodiment of the present invention, and FIG. 5B is a timing diagram corresponding to each node signal. As shown in Figure 5A, the first stage shift register unit SR ₁ is composed of a D-type flip-flop DFF, two inverters (also called NOT gate, NOTGate) NOT ₁ , NOT ₂ and an AND gate (AND Gate) AND composed of.

In the present invention, the data input terminal D of the D-type flip-flop DFF is connected to a voltage level VDD, so that the data input terminal D remains at a high logic level, and its clock trigger signal input terminal C is started by the timing control circuit. The start signal ST is used as the input signal, and its output terminal feeds out a signal Q ₁ to one input terminal of the AND gate AND, while the other input terminal of the AND gate AND receives the inverted clock signal XCK, and the reset terminal R of the flip-flop DFF receives The sampling signal S ₂ of the second-stage shift register unit SR ₂ is converted by the inverter NOT ₂ , and the other inverter NOT ₁ converts the inverted clock signal XCK into a clock signal CK, which is transmitted to subsequent stages in the shift buffer unit.

When the shift register unit of the first stage is at the time point _t2 , the data input terminal D receives a high logic level of a voltage level VDD input, and the start signal ST is just in the trigger state of the rising edge input clock trigger signal input Terminal C, that is, the start signal changes from a low state to a high state. According to the output characteristics of the D-type flip-flop, the output signal Q ₁ will present the level input by the data input terminal D, that is, the output signal Q ₁ will change from the original low The state changes to a high state and is input to an input terminal of the AND gate.

According to the signals Q ₁ and XCK at the two input terminals, the AND gate captures a high-state sampling signal S ₁ which is 50% of the duty cycle of the inverted clock signal XCK between the time point t _{2 ′} and t ₂ ″, and outputs it to In the second-stage shift register unit SR ₂ ; and the second-stage shift register unit SR ₂ receives the sampling signal S ₁ , and at the time point t ₂ ", outputs the sampling signal S ₂ to the next-stage shift register unit, data The latch circuit (not shown in the figure) and the first-stage shift register unit SR ₁ , the sampling signal S ₂ is input to the reset terminal of the D-type flip-flop after passing through the inverter of the first-stage shift register unit SR ₁ R, reset the D-type flip-flop to make the output signal Q ₁ change from high state to low state, and stop the sampling operation of the first-stage shift register unit SR ₁ .

Please refer to FIG. 6A , which is a timing diagram of an input signal and an output signal in an ideal state of the first-stage shift register unit according to the first embodiment of the present invention. The shift register circuit receives the start signal ST and the inverted clock signal XCK, wherein the first-stage shift register unit receives the start signal ST as a pulse input between the time point t and t', and simultaneously captures The inverted clock signal XCK generates a sampling signal _S1 that is output to the corresponding data latch circuit and the second-stage shift register unit, and the successive stages of shift register units will sequentially output the sample signal.

Please refer to FIG. 6B , which is a timing diagram of input signals and output signals of the shift register circuit according to the first embodiment of the present invention. Among them, the shift register unit of the first stage receives the start signal ST as a pulse input between the time points _t2 and _t2 ', and triggers the D-type flip-flop to output a high-level signal (because the data input terminal D is a high level) to an input terminal of the AND gate, and the AND gate receives two signals Q ₁ and XCK, and generates a sampling signal S ₁ at the time point t ₂ ′ to t ₂ ” and outputs it to the next-stage shift register unit, The successive levels of shift buffer units will sequentially output sampling signals.

In the shift register circuit of the present invention, even if the clock signal and the start signal are delayed during transmission, so that when entering the first-stage shift register unit, it is an asynchronous signal, the first-stage shift register will be used The circuit design of the unit achieves that the output sampling signal and the clock signal are a synchronous clock, so as to avoid the appearance of abnormal clock and seriously affect the accuracy of the display screen.

Please refer to FIG. 7A and B at the same time. FIG. 7A is a circuit diagram of the first-stage shift register unit according to the second embodiment of the present invention, and FIG. 7B is a timing diagram corresponding to each node signal. As shown in FIG. 7A , the first-stage shift buffer unit is composed of two D-type flip-flops DFF ₁ , DFF ₂ , two inverters NOT ₁ , NOT ₂ and an AND gate AND.

The difference between this embodiment and the first embodiment is that a D-type flip-flop DFF ₂ is added after DFF ₁ , wherein the output terminal of DFF ₁ feeds a signal Q ₁ to the data input terminal D ₂ of DFF ₂ , and its clock triggers The signal input terminal C ₂ takes the clock signal CK as the input signal, and its output terminal feeds out a signal Q ₂ to an input terminal of the AND gate AND, while the other input terminal of the AND gate AND receives the inverted clock signal XCK, which triggers The reset terminal R of DFF ₁ and DFF ₂ receives the sampling signal S ₂ of the second-level shift buffer unit converted by the inverter NOT ₂ , and the other inverter NOT ₁ converts the inverted clock signal XCK Becomes a clock signal CK, which is transmitted to subsequent multi-stage shift register units.

When the first-stage shift register unit is at the time point _t3 , the data input terminal D1 is connected to a voltage level VDD to keep it at a high logic level, and the start signal ST is just in the trigger state of the rising edge to input the clock trigger The signal input terminal C ₁ , that is, the start signal ST changes from a low state to a high state, and the output signal Q ₁ presents the level input by the data input terminal D ₁ , that is, the output signal Q ₁ will change from the original low state to a high state. , input to the data input terminal D ₂ of DFF ₂ ; and at the time point t ₃ ', the clock signal CK received by the clock trigger signal input terminal C ₂ is just in the trigger state of the rising edge, then DFF ₂ feeds out the signal Q ₂ is a high-level signal output, that is, the output signal _Q2 changes from a low state to a high state and outputs to an input terminal of the AND gate.

According to the signals Q ₂ and XCK at the two input terminals, the AND gate AND gate extracts a high-state sampling signal S ₁ which is 50% of the duty cycle of the inverted clock signal XCK between time points t ₄ and t ₄ ′, and outputs it to In the second-stage shift register unit SR ₂ ; and the second-stage shift register unit SR ₂ receives the sampling signal S ₁ , and at the time point t ₄ ', outputs the sampling signal S ₂ to the next-stage shift register unit, data The latch circuit (not shown in the figure) and the first-stage shift register unit SR ₁ , the sampling signal S ₂ is input to the reset terminals R ₁ and R ₂ of the flip-flops DFF ₁ and DFF ₂ after passing through the inverter NOT ₂ , Reset DFF ₁ and DFF ₂ to make the output signals Q ₁ and Q ₂ change from high state to low state, and stop the sampling operation of the first-stage shift register unit SR ₁ .

Since the D-type flip-flop belongs to an edge trigger flip flop, in the above two embodiments, a positive edge trigger (positive edge trigger) flip-flop is selected, so only when the clock trigger signal is a rising edge trigger The state starts to sample the input signal of the data input terminal D, and the output terminal Q outputs the input level of the data input terminal D. Of course, a flip-flop triggered by a negative edge can also be selected as an alternative to the above-mentioned embodiment.

Please refer to FIG. 8A and B at the same time. FIG. 8A is a circuit diagram of the first-level shift register unit according to the third embodiment of the present invention, and FIG. 8B is a timing diagram corresponding to each node signal. As shown in FIG. 8A , the first-level shift register unit is composed of seven transistors. This embodiment can be composed of NMOS thin film transistors or PMOS thin film transistors. If it is composed of NMOS thin film transistors, the first power supply V _DD is at a high voltage level, and the second power supply V _SS is at a low voltage level; if it is composed of PMOS thin film transistors, the first power supply V _DD is at a low voltage level , the second power supply V _SS is a high voltage level; in this embodiment, it is composed of NMOS.

The first-level shift register unit includes a first transistor _N1 , the gate of which is coupled to the inverted clock signal XCK, the drain is coupled to the start signal ST output by the timing control circuit (not shown in the figure), and the source is Then connect the gate of the _3rd transistor N3, the gate of the 6th transistor _N6 and the drain of the 7th transistor _N7 , its source and the junction of the gate of the _3rd transistor N3 are a node A; Transistor _N2 , its drain and gate are connected to a first power supply VDD, the source is connected to the gate of the fourth transistor _N4 , the drain of the fifth transistor _N5 and the drain of the sixth transistor _N6 ; The drain of the third transistor N ₃ is coupled to the clock signal CK, the source is connected to the drain of the fourth transistor N ₄ and the gate of the fifth transistor N ₅ , the source of the third transistor N ₃ is connected to the gate of the fourth transistor N _4. The drain connection is the output terminal of the first-stage shift register unit; and the sources of the 4th, 5th, 6th and 7th transistors are all connected to a second power supply V _SS ; and the _7th transistor N7 is used as The gate of the disabling circuit of the first-level shift register unit is coupled to the output terminal of the second-level shift register unit.

At the time point _t5 , the gate of the first transistor _N1 receives the high-level signal of the inverted clock signal XCK, so that the first transistor _N1 is turned on, and the drain receives the high-level signal of the start signal ST to pass through. Turn on the third transistor N ₃ via node A. At this time, when the first transistor N ₁ is turned on, the level of point A is the same as the input start signal, and point A is in a floating state. According to the principle of feed-though voltage drop, at the time point _t6 , when the clock signal CK is a high-level signal, in order to maintain the voltage difference between the gate of the third transistor _N3 and the source of the first transistor _N1 , so that the level at point A is higher, then the third transistor _N3 is still turned on; then at the time point _t6 to _t7 , the clock signal CK is a high level signal and passes through the third transistor _N3 , and from The output terminal outputs a sampling signal S ₁ to the shift buffer unit of the next stage, so that subsequent sampling circuits can sample in sequence. At the time point _t7 , the second-stage shift register unit SR ₂ (not shown in the figure) starts sampling operation, and at this time, the gate of the seventh transistor _N7 receives a high level from the second shift register unit The sampling signal S ₂ turns on the seventh transistor N ₇ to ground the potential of point A, then the third transistor N ₃ is turned off, and the first shift register unit SR ₁ stops the sampling operation to stop outputting the high-state sampling signal S ₁ .

Please refer to FIG. 9A , which is a timing diagram of input signals and output signals of the first-stage shift register unit according to the third embodiment of the present invention. The shift register circuit receives the start signal ST and the inverted clock signal XCK, wherein, at the time point _t5 , the first-stage shift buffer unit receives the start signal ST as a pulse input to drive the first-stage shift buffer The unit performs a sampling operation. According to the above sampling principle, the first-level shift register unit will generate a sampling signal _S1 at the time point _t6 to _t7 , and output it to the corresponding data latch circuit and the second-level shift register unit . The second-stage shift register unit receives the sampling signal S ₁ , generates a sample signal S ₂ and feeds it to the corresponding data latch circuit, the next-stage shift register unit and the disabling circuit of the first-stage shift register unit, and The disable circuit is driven to stop the sampling operation of the first-stage shift register unit, so at time points _t7 to _t8 , the first-stage shift register unit will not capture signals to avoid sampling errors.

In this embodiment, the duration of the start signal ST can be further changed, as shown in FIG. 9B , which is a generalized approach of the above-mentioned embodiment. Wherein, the duty cycle of the inverted clock signal XCK received by the shift register circuit is T, the duration of the start signal ST is set as (n+1/2)T, and n is a natural number. Since the duration of the start signal ST may increase, the disabling circuit in the first-stage shift register unit was originally designed to receive the sampling signal S ₂ of the second-stage shift register unit, and stop the first-stage shift register unit The sampling action corresponds to adding multi-level sampling signals to the sampling signal Sm, where m is greater than or equal to n+1. to avoid repeated sampling errors.

For example: when n is 5, the duration of the start signal ST is 5.5T, then the disabling circuit of the shift register unit of the first stage needs to be designed to at least receive the samples of the shift register units of the second to sixth stages Signals S ₂ -S ₆ . According to the action principle of the above-mentioned embodiment, since the duration of the start signal ST is much longer than the period of the inverted clock signal XCK, no matter how serious the delay between the start signal ST and the inverted clock signal XCK is, there will be at least one inverted clock signal. The high-state half period (XCK=1) of the phase clock signal XCK and the duration of the start signal ST (ST=1) enter the sampling circuit of the first stage shift buffer unit simultaneously, then the sampling circuit can operate normally, and sample a The high-state half period of the clock signal CK is used as the sampling signal _S1 ; but because the start signal ST lasts for a long time, there may be multiple cycles of the inverted clock signal XCK and the start signal ST input to the first stage of shifting at the same time The sampling circuit of the cache unit will cause the first-stage shift register unit to repeatedly output the sampling signal S ₁ , so it is necessary to receive the sampling signals other than the first stage through the disabling circuit to stop the first-stage shift register unit Sampling action to avoid repeated sampling errors.

Please refer to FIG. 10 , which is a flowchart of a method for synchronizing driving circuit signals according to an embodiment of the present invention. The drive circuit of the display has a timing control circuit, a data drive circuit and a scan drive circuit, wherein the data circuit includes a shift register circuit and a plurality of latch circuits, and the shift register circuit is composed of a multi-stage shift buffer unit composed of.

The drive circuit signal synchronization method at least includes the following steps: the timing control circuit provides an inverted clock signal and a start signal to the scan drive circuit and the data drive circuit (S1); Clock signal and start signal (S2); in the first-level shift register unit, when the start signal is high level, capture the 50% duty cycle of the next clock signal corresponding to the start signal as a sampling signal The duration of S ₁ (S3); output the synchronous sampling signal S ₁ , the clock signal and the inverted clock signal to the corresponding latch circuit and the second-level shift buffer unit (S4); the second-level shift The buffer unit receives the sampling signal S ₁ of the first stage, and generates the sampling signal S ₂ (S5); the sampling signal S ₂ of the second stage is output to the corresponding latch circuit and the shift buffer unit of the next stage, and feedback To the disabling circuit (S6) of the first-stage shift register unit; the first-stage shift register unit stops the sampling operation (S7) by the sampling signal _S2 of the second stage, so as to avoid repeated sampling and obtain correct sampling signal, so as to avoid the situation that the data driving circuit cannot operate normally due to the incorrect sampling signal of the known technology.

In step S7, due to the difference in the duration of the start signal and the design of the first-stage shift register unit, the synchronous signal is controlled to be generated and the sampling operation is stopped in conjunction with receiving the output of other stages or its own stage.

In the embodiments of the present invention, for the convenience of explanation, the two-phase clock signal is used as the reference signal, that is, the dual-clock driving shift register circuit is used as an illustration, but in fact, except for the application in the dual-clock shift register circuit, It can also be applied to single-phase or multi-phase clock shift register circuits, both of which can realize the functions described in the present invention. In the present invention, the first-stage shift register unit receives the start signal and the inverted clock signal from the timing control circuit for illustration. Of course, it can also receive the start signal and the clock signal to generate the sampling signal.

In addition, in the shift register circuit of the present invention, the shift register unit of the first stage is redesigned and added with a disabling circuit (the reset terminal in the first and second embodiments, the seventh transistor N in the third embodiment ₇ ), even if the clock signal and the start signal are delayed during the transmission process, so that it is an asynchronous signal when entering the first-level shift register unit, the circuit design of the first-level shift register unit will be used to realize the output The sampling signal and the clock signal are a synchronous clock to avoid the appearance of abnormal clock, which seriously affects the accuracy of the display screen. For the shift register units of the second to the Nth stages, the circuit of the general shift register unit can be used without any special modification.

The present invention uses the first-stage shift buffer unit to receive the start signal and the inverted clock signal from the timing control circuit, and then generates a clock signal and a sampling signal synchronous with the inverted clock signal, while the subsequent stages of shift buffer units The synchronized inverted clock signal, clock signal and sampling signal can be output step by step to complete the function of the shift register circuit. However, the first-stage shift register unit still needs the output of other stages or its own stage to control the generation of synchronous signals.

Although the present invention has been described above with preferred examples, it is not intended to limit the spirit and entities of the present invention to the above-mentioned examples. Those skilled in the art can easily understand and utilize other components or methods to produce the same effect. Therefore, modifications made without departing from the spirit and scope of the present invention should be included in the claims of the present invention.

Claims (10)

1. a shift register circuit has multistage shift cache unit, according to the signal that a timing control circuit is provided, produces a sampled signal to a corresponding data-latching circuit, and this shift register circuit comprises:

The 1st grade of shift cache unit, couple this timing control circuit and corresponding this data-latching circuit, have the circuit of deenergizing and a sample circuit, receive the signal that this timing control circuit provides, capture a correct sampled signal and export in corresponding this data-latching circuit and the next stage shift cache unit; With

The 2nd grade to N level shift cache unit, has a sample circuit separately, and series connection and the 2nd grade of shift cache unit are connected in the 1st grade of shift cache unit step by step;

Wherein, this circuit that deenergizes of the 1st grade of shift cache unit receives the sampled signal of the 2nd grade of shift cache unit, stops the action of this sample circuit of the 1st grade of shift cache unit.

2. shift register circuit as claimed in claim 1, wherein the 1st grade of shift cache unit by a trigger, two phase inverters and one and door form, by the replacement end of this trigger of the anti-phase back feed-in of the sampled signal of the 2nd grade of shift cache unit, to stop the sampling action of the 1st grade of shift cache unit.

3. shift register circuit as claimed in claim 1, wherein the 1st grade of shift cache unit by the triggers of two series connection, two phase inverters with one and an a plurality of logic module form, by the replacement end of this two trigger of the anti-phase back feed-in of the sampled signal of the 2nd grade of shift cache unit, to stop the sampling action of the 1st grade of shift cache unit.

4. shift register circuit as claimed in claim 1, this circuit that deenergizes of the 1st grade of shift cache unit wherein, comprise a N transistor npn npn, the source electrode of this N transistor npn npn is connected in this sample circuit, drain electrode end and is connected in the sampled signal that relative electronegative potential place, grid receive the 2nd grade of shift cache unit, when the sampled signal of the 2nd grade of shift cache unit is a high level pulse, this N transistor npn npn conducting is connected to relative electronegative potential place with sample circuit, to stop the sampling action of the 1st grade of shift cache unit.

5. shift register circuit as claimed in claim 4, wherein this timing control circuit provides an initial signal and a clock signal, and the cycle of this clock signal is T, and the cycle of this start signal equals (N+1/2) * T, N is a natural number.

6. the driving circuit of a display, this driving circuit comprises:

One timing control circuit;

One data drive circuit, couple this timing control circuit, has a shift register circuit, wherein this shift register circuit is made of multistage shift cache unit, by the signal that this timing control circuit provided, the 1st grade of shift cache unit of this shift register circuit captures a correct sampled signal, export the next stage shift cache unit to, sampled signal according to the 2nd grade of shift cache unit, the sampling action of the 1st grade of shift cache unit is stopped, and the multistage shift cache unit in back moves in regular turn; And

Scan driving circuit couples this timing control circuit, and controlled by it,

Scan the signal that driving circuit provides by this data drive circuit and this, the picture of controlling and drive this display shows.

7. driving circuit as claimed in claim 6, wherein the 1st grade of shift cache unit by a trigger, two phase inverters and one and door form, by the replacement end of this trigger of the anti-phase back feed-in of the sampled signal of one the 2nd grade of shift cache unit, to stop the sampling action of the 1st grade of shift cache unit.

8. driving circuit as claimed in claim 6, wherein the 1st grade of shift cache unit is by the triggers of two series connection, two phase inverters and one and form, by the replacement end of this two trigger of the anti-phase back feed-in of the sampled signal of one the 2nd grade of shift cache unit, to stop the sampling action of the 1st grade of shift cache unit.

9. driving circuit as claimed in claim 6, this circuit that deenergizes of the 1st grade of shift cache unit wherein, has a N transistor npn npn, the source electrode of this N transistor npn npn is connected in this sample circuit, drain electrode end and is connected in the sampled signal that relative electronegative potential place, grid receive one the 2nd grade of shift cache unit, when the sampled signal of the 2nd grade of shift cache unit is a high level pulse, this N transistor npn npn conducting is connected to relative electronegative potential place with sample circuit, to stop the sampling action of the 1st grade of shift cache unit.

10. driving circuit as claimed in claim 9, wherein this timing control circuit provides an initial signal and a clock signal, and the cycle of this clock signal is T, and the cycle of this start signal equals (N+1/2) * T, N is a natural number.

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