CN100437236C - Liquid crystal display panel and circuit layout thereon - Google Patents

Abstract

The invention provides a liquid crystal display panel and a circuit layout thereon, wherein the circuit layout of the display panel is formed on a substrate, and a central display area and a peripheral wiring area are formed on the substrate. The circuit layout of the display panel defines a plurality of chip reserved blocks in the peripheral wiring area for installing driving chips. The display panel circuit layout includes at least one first set of contact pads, at least one second set of contact pads, and at least one connection circuit. The first group of contact pads are arranged along one side of the chip reserved block. The second group of contact pads are arranged along the other side of the chip reserved block. The connecting line is connected between the first group of contact pads and the second group of contact pads in a bridging mode. The circuit layout of the invention is compatible with the existing testing procedures and can share the testing jig.

Description

LCD panel and its circuit layout

technical field

The invention relates to a circuit layout of a liquid crystal display panel, in particular to a circuit design matching a crystal glass bonding process, specifically a liquid crystal display panel and a circuit layout on it.

Background technique

In recent years, liquid crystal displays (Liquid Crystal Display, LCD) have gradually replaced traditional image tube (Cathode Ray Tube, CRT) displays due to their advantages of thinness, lightness, power saving, and no radiation, and are widely used in desktop computers, personal digital Electronic products such as assistants, notebook computers, digital cameras and mobile phones.

In a conventional liquid crystal display panel, as shown in FIG. 1 , driving chips (LSI chips) 22 , 32 for driving pixel display are packaged on a flexible printed circuit film 24 , 34 . The driver chips 22 and 32 in this package are applied to the bonding process by using the tape automatic bonding (TAB) method, that is, the flexible printed circuit films 24 and 34 will be used to make the printed wiring. The circuit boards 20 , 30 are electrically connected to the glass substrate 10 .

In order to further pursue the thinning of the display panel, as shown in Figure 2, it is a liquid crystal display panel produced by a new generation of chip-on-glass (Chip On Glass, COG) process. Compared with the liquid crystal display panel shown in FIG. 1 , the liquid crystal display panel produced by the crystal glass bonding process uses anisotropic conductive film (Anisotropic Conductive Film, ACF) to bond the driver chips (LSI chips) 42, 52 to the bare chip (Flip -chip) is electrically bonded to the contact pads on the surface of the glass substrate 10, thus saving the use of the flexible printed circuit film 34.

As shown in FIG. 2 , in the grain glass bonding process, circuit traces are usually designed directly on the glass substrate (Wire-On-Array, WOA). That is to say, in FIG. 1 , the circuit that originally must be fabricated on the printed circuit board 30 is directly fabricated on the glass substrate 10 . The technology of directly cascading each driving chip 52 through the wires on the glass substrate is a common design of the gate end of the liquid crystal display panel.

Compared with the traditional tape-and-roll automatic bonding method, the liquid crystal display panel manufactured by the grain glass bonding process can not only reduce the use of the flexible printed circuit film 34 to reduce the manufacturing cost. Designing the circuit traces directly on the glass substrate (WOA) can save the design and manufacturing costs of the printed circuit boards 20, 30, and the simplification of the printed circuit boards 20, 30 can also reduce the size and weight of the display.

Please refer to FIG. 3 , which enlarges and displays the peripheral wiring area 10 b of the signal terminal of the liquid crystal display panel in FIG. The chip reserved area 110 is arranged in the peripheral wiring area 10b of the liquid crystal display panel, and has a contact pad group 120, 130 on opposite sides thereof respectively. Wherein, the contact pad group 120 adjacent to the edge 10c of the glass substrate is used for inputting control signals and power signals. The contact pad group 130 adjacent to the central display area 10a of the display panel is used to output display signals to control the display of the pixel elements. It should be noted that there are no wires connecting the reserved chip blocks 110 to each other. Therefore, as shown in FIG. 2 , the control signal and the power signal are respectively input to each driver chip 42 mounted on the chip reserved block 110 through the flexible printed circuit film 44 .

Although the grain glass bonding process has such an advantage in cost, it is limited by the size of the frame (ie, the peripheral wiring area) 10b of the display panel, and the allowable circuit design space and the number of contacts thereon are limited. Therefore, as shown in FIG. 2 , the method of connecting the driver chips in series with the wiring on the glass substrate by the grain glass bonding process is usually only applicable to the gate driver chip 52 with a small number of contacts. As for the signal driver chips 42 with more contacts, the peripheral circuits are mainly designed on an external printed circuit board 40 , and the circuit board inputs signals to these signal driver chips 42 through the flexible printed circuit film 44 .

However, in order to further reduce the production cost, it has become an inevitable trend to form wires on the glass substrate to connect the various signal driving chips 42 in series. Moreover, since the signal driving chip 42 processes various types of signals, the required number of contacts is also large. In addition to causing strict restrictions on the circuit layout on the panel; how to make the serially connected circuit layout compatible with the existing process (this existing process matches the circuit layout in Figure 3), such as sharing existing test methods, Test fixtures, etc., have become a major challenge for this circuit layout to be introduced into mass production.

Therefore, how to make the circuit layout of the serially designed display panel compatible with the existing technology has become one of the important development goals of the circuit layout design of the current display panel.

Contents of the invention

The main purpose of the present invention is to provide a display panel, which utilizes wires on a glass substrate to cascade driving chips to reduce manufacturing costs. Moreover, the circuit layout of the display panel is compatible with existing testing procedures.

The circuit layout of the display panel provided by the present invention is formed on a substrate, and a central display area and a peripheral wiring area are formed on the substrate. In the circuit layout of the display panel, a plurality of chip reserved blocks are defined in the peripheral wiring area for device driving chips. Moreover, the circuit layout of the display panel includes at least one first group of contact pads, at least one second group of contact pads and at least one at least one connection circuit. Wherein, the first group of contact pads is arranged along a first side of the chip reserved block. The second group of contact pads is arranged along a second side adjacent to the first side of the chip reserved block. The connection line is bridged between one contact pad in the first group of contact pads and one contact pad in the second group of contact pads.

With this circuit layout, the present invention also provides a display panel, including a substrate, a plurality of pixel elements, a plurality of chip reserved areas, at least one first group of contact pads, a plurality of signal output lines, at least one second A set of contact pads, a plurality of signal transmission lines, a plurality of driver chips connected in series and at least one connection line. Wherein, the substrate area is divided into a central display area and a peripheral wiring area. A plurality of pixel element arrays are arranged in the central display area. A plurality of chip reserved blocks are arranged in the peripheral wiring area along the edge of the central display area. The first group of contact pads is arranged along a first side of the chip reserved block adjacent to the central display area. The signal output lines extend from the first group of contact pads to the central display area, and are used to control the display of the pixel elements. The second group of contact pads is arranged along a second side adjacent to the first side of the chip reserved block. The signal transmission line is located in the peripheral wiring area and connected to the second group of contact pads to transmit a control signal and a power signal required by the display. The driver chip is installed on the chip reserved block; and is electrically connected to the signal output circuit and the signal transmission circuit through the first group of contact pads and the second group of contact pads. The connection line is located in the reserved area of the chip, and is connected between one contact pad in the first group of contact pads and one contact pad in the second group of contact pads.

The present invention also provides a circuit layout of a display panel, which is formed on a substrate, and a central display area and a peripheral wiring area are formed on the substrate, and a multi-chip reserved area is defined in the peripheral wiring area. In order to drive the chip, the circuit layout of the display panel includes:

at least one first group of contact pads arranged along a first side of the chip reserved block;

at least one second group of contact pads arranged along a second side adjacent to the first side of the chip reserved block;

at least one signal transmission line, located in the peripheral wiring area, for connecting the reserved blocks of two adjacent chips; and

At least one connection line is connected between one contact pad in the first group of contact pads and the signal transmission line.

The circuit layout of the present invention is compatible with existing testing procedures and can share testing fixtures.

Description of drawings

1 is a schematic diagram of a traditional liquid crystal display panel using a tape-and-roll automatic bonding process;

2 is a schematic diagram of a conventional liquid crystal display panel using a grain glass bonding process;

FIG. 3 is an enlarged display of the circuit layout of the signal terminal of the liquid crystal display panel in FIG. 2;

4A is a schematic diagram of a preferred embodiment of the display panel of the present invention;

FIG. 4B is an enlarged view showing the circuit layout of the peripheral wiring area of FIG. 4A;

5 is a schematic diagram of a second preferred embodiment of the circuit layout of the present invention;

6 is a schematic diagram of a third preferred embodiment of the circuit layout of the present invention;

7 is a schematic diagram of a fourth preferred embodiment of the circuit layout of the present invention;

FIG. 8 is a schematic diagram of a fifth preferred embodiment of the circuit layout of the present invention.

Description of main figure numbers:

Glass substrate 10 Driver chip 22, 32, 42, 52

Printed circuit boards 20, 30 Flexible printed circuit films 24, 34, 44

Chip reserved block 110 Central display area 10a

Peripheral wiring area 10b Glass substrate edge 10c

Contact pad set 120, 130 Printed circuit board 40

Substrate 200 Pixel Components 310

Driver chip 320 Central display area 200a

Peripheral wiring area 200b Chip reserved block 210

Edges 210a, 210b, 210c of chip reserved blocks

The first group of contact pads 230 Signal output lines 232

The second group of contact pads 240 Signal transmission line 242

The third group of contact pads 220 Signal input lines 222

Connection line 250 Test pads A1, A2, A3, A4, A5, A6

Contact pads B1, B3 Signal transmission lines C1, C2, C3, C4, C6

Connection lines 252, 254a, 254b, 256, 258 Signal output line D5

Detailed ways

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

Please refer to FIG. 4A and FIG. 4B , which are schematic views of a preferred embodiment of the display panel of the present invention. As shown in FIG. 4A , the display panel includes a substrate 200 , a plurality of pixel elements 310 and a plurality of driving chips 320 . Wherein, the substrate 200 is divided into a central display area 200a and a peripheral wiring area 200b. A plurality of pixel elements 310 are arranged in an array in the central display area 200a. The driving chips 320 are arranged in the peripheral wiring area 200b along the edge of the central display area 200a.

FIG. 4B shows an enlarged view of the peripheral wiring region 200 b of FIG. 4A , and removes the driver chip 320 to show the circuit layout of the present invention. As shown in the figure, a plurality of chip reserved blocks 210 are disposed on the peripheral wiring area 200 b for the device driving chip 320 . Each reserved chip block 210 is arranged in the peripheral wiring area 200b along the edge of the central display area 200a.

The first group of contact pads 230 is arranged along a side 210 a of the reserved chip block 210 adjacent to the central display area 200 a. The signal output lines 232 extend from the first group of contact pads 230 into the central display area 200a. Thus, the driving chip 320 can control the display of the pixel element 310 . The second group of contact pads 240 is arranged along the other side 210 b of the chip reserved block 210 . The signal transmission line 242 is located in the peripheral wiring area 200 b and connected to the second set of contact pads 240 to transmit control signals and power signals required for the operation of the driving chip 320 . The third group of contact pads 220 is arranged along a side 210c of the reserved chip block 210 adjacent to the edge of the display panel. The signal input line 222 is connected to the third group of contact pads 220 and can also be used for inputting control signals and power signals.

The connection line 250 is located in the chip reserved area 210 and bridges between the first group of contact pads 230 and the second group of contact pads 240 . There is at least one test pad A1 in the first group of contact pads 230 for circuit testing. The test pad A1 is electrically connected to a contact pad B1 of the second group of contact pads through the connection line 250 , and the contact pad B1 is connected to a signal transmission line C1 . Therefore, a signal can be input to the signal transmission line C1 through the test pad A1 for detection.

Please also refer to FIG. 4A , each driver chip 320 installed on the reserved chip block 210 can be cascaded with the signal transmission line 242 through the second group of test pads 240 . Therefore, the control signal or power signal required for the operation of the driving chip 320 can be sequentially transmitted to each driving chip 320 through the signal transmission line 242 . In contrast, the control signal or power signal input to each driver chip 320 through the signal input line 222 and the third group of test pads 220 is independently input to each driver chip 320 .

As far as a preferred embodiment is concerned, the power signal required for the operation of the driver chip 320 is preferably input through the signal input line 222 and the third group of test pads 220, so as to avoid the power signal strength from dropping during signal transmission and affecting The quality of the signal output by the driver chip 320 . Secondly, as for the control signal which is not greatly affected by the signal strength, it can be selected to be sequentially transmitted to each driving chip 320 through the signal transmission line 242 and the second group of test pads 240 . It should be noted that the circuit layout of the present invention is aimed at the driving chips connected in series by traces on the glass substrate, and is not limited to the gate terminals or signal terminals of the display panel. At the same time, due to the present invention, various driving chips 320 can be connected in series by using wires on the glass substrate. Therefore, as shown in FIG. 4A , in the display panel of the present invention, there is no need to provide a corresponding flexible printed circuit film 400 for each driving chip 320 . Signals from the printed circuit board 500 can be transmitted to each driver chip 320 through a relatively small number of flexible printed circuit films 400 , thereby saving the usage of the flexible printed circuit films 400 .

FIG. 5 is a schematic diagram of a second preferred embodiment of the circuit layout of the present invention. Compared with the embodiment shown in FIG. 4B , there is no configuration of the third group of contact pads 220 in the reserved chip area 210 of this embodiment. Therefore, the control signals and power signals required for the operation of the driver chip 320 are completely transmitted through the second group of contact pads 240 and the signal transmission lines 242 . This configuration method is mainly applicable to the circuit layout of the gate terminal.

Please refer to FIG. 6 , which is a schematic diagram of a third preferred embodiment of the circuit layout of the present invention. Compared with the embodiment of FIG. 4B , in the first group of contact pads 230 of this embodiment, a test pad A2 is directly connected to the signal transmission line C2 through the connection line 252 located in the chip reserved block 210. Moreover, the test pad A2 is not connected to the signal output line 232 . Through the test pad A2, a signal can be input to the signal transmission line C2 for detection.

Please refer to FIG. 7 , which is a schematic diagram of a fourth preferred embodiment of the circuit layout of the present invention. Compared with the embodiment of FIG. 4B, in the first group of contact pads 230 of this embodiment, there are multiple (two are shown in the figure) test pads A3, A4, which are respectively connected to different signal transmission lines through connection lines 254a, 254b. C3, C4. As shown in the figure, the layout of these connecting lines 254a, 254b can be in the manner shown in FIG. Between B3; the method as shown in FIG. 6 can also be adopted, that is, it is connected between a contact pad A4 of the first group of test pads 230 and the signal transmission line C4.

Please refer to FIG. 8 , which is a schematic diagram of a fifth preferred embodiment of the circuit layout of the present invention. Compared with the embodiment in FIG. 4B , in the reserved chip area 210 of this embodiment, there is a connection line 258 bridged between two different contact pads A5 and A6 in the first group of contact pads 230 . One of the contact pads A6 is connected to the signal transmission line C6, and the other contact pad A5 is connected to the signal output line D5. Moreover, the contact pad A5 can be used as a test pad for inputting corresponding signals to the signal transmission line C6 for detection.

Cooperating with the traditional circuit layout of FIG. 3 , the traditional test process and test fixture are designed to test the contact pad group 130 located in the chip reserved area 110 . In contrast, as shown in FIG. 4B , the circuit layout of the present invention adds a second group of contact pads 240 and signal transmission lines 242 . But as far as the circuit layout of the present invention is concerned, it is not necessary to directly detect the second group of test pads 240, but by detecting the first group of test pads 230 (corresponding to the contact pad group 130 in FIG. The signal to the signal transmission line 242 is used for detection. In other words, the circuit layout of the present invention is compatible with the existing test process (the existing test process is matched with the circuit layout shown in FIG. 3 ), and can share test fixtures.

The above is to use preferred embodiments to describe the present invention in detail, rather than to limit the scope of the present invention, and those who are familiar with this type of technology can understand that it is appropriate to make slight changes and adjustments without losing the gist of the present invention without departing from the spirit and scope of the present invention.

Claims (10)

1. A circuit layout of a display panel, formed on a substrate, and forming a central display area and a peripheral wiring area on the substrate, characterized in that the peripheral wiring area defines a multi-chip reserved The blocks are used to drive chips, and the circuit layout of the display panel includes: at least one first group of contact pads arranged along a first side of the chip reserved block; at least a second group of contact pads arranged along a second side of the chip reserved block adjacent to the first side; and At least one connection line is bridged between one contact pad in the first group of contact pads and one contact pad in the second group of contact pads. 2. The circuit layout of the display panel according to claim 1, wherein the driving chips are connected in series. 3 . The circuit layout of the display panel according to claim 1 , wherein the first group of contact pads is arranged along a side of the reserved chip area adjacent to the central display area. 4 . 4. The circuit layout of the display panel according to claim 1, wherein the control signals required for the operation of the driving chip are input to the driving chip through the second group of contact pads. 5 . The circuit layout of the display panel according to claim 1 , wherein a power signal required for the operation of the driving chip is input to the driving chip through the second group of contact pads. 6. A display panel, characterized in that it comprises: A substrate, divided into a central display area and a peripheral wiring area; a plurality of pixel elements arranged in an array in the central display area; A plurality of chip reserved blocks are arranged in the peripheral wiring area along the edge of the central display area; at least one first group of contact pads arranged along a first side of the reserved chip area adjacent to the central display area; a plurality of signal output lines extending from the first group of contact pads into the central display area for controlling the display of the pixel elements; at least one second group of contact pads arranged along a second side adjacent to the first side of the chip reserved block; a plurality of signal transmission lines located in the peripheral wiring area and connected to the second group of contact pads for transmitting signals required for display; A plurality of driving chips connected in series are respectively installed on the chip reserved block, and are electrically connected to the signal output line and the The signal transmission line; At least one connection line is located in the reserved area of the chip and bridged between one contact pad in the first group of contact pads and one contact pad in the second group of contact pads. 7. The display panel according to claim 6, wherein the first group of contact pads includes at least one test pad for circuit testing. 8 . The display panel according to claim 7 , wherein the test pad is electrically connected to one contact pad in the second group of contact pads through the connection line, so as to input the detection signal. 9. A circuit layout of a display panel, formed on a substrate, and forming a central display area and a peripheral wiring area on the substrate, characterized in that the peripheral wiring area defines a multi-chip reserved The blocks are used to drive chips, and the circuit layout of the display panel includes: at least one first group of contact pads arranged along one side of the chip reserved block; at least one second group of contact pads arranged along a second side adjacent to the first side of the chip reserved block; at least one signal transmission line, located in the peripheral wiring area, for connecting the reserved blocks of two adjacent chips; and At least one connection line is connected between one contact pad in the first group of contact pads and the signal transmission line. 10 . The circuit layout of the display panel according to claim 9 , wherein the first group of contact pads is arranged along a side of the reserved chip area adjacent to the central display area. 11 .

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