CN100433819C - Method of scrambling process for analog video signal and scrambling circuit - Google Patents

Abstract

The invention relates to a method and a circuit for processing analog video signals. The method is to add a sine wave interference signal to the analog video signal of a TV set or a video disc player, and the scrambled analog video signal can be played normally in the TV set. When the home video recorder with AGC function is used to record the scrambled analog video signal, serious distortion will occur, and the image quality will obviously deteriorate when played by the video recorder, affecting normal viewing. When the scrambling circuit of the present invention works, the analog video signal is divided into two paths, one of which is used to form a time interval control signal for adding interference signals and not adding interference signals, and the sine wave signal as the interference signal is under the control of the control signal , and adding it to another analog video signal within a corresponding time interval, so as to realize scrambling processing on the analog video signal. The method of the invention is cleverly conceived and practical, and the scrambling circuit of the invention has simple structure and low cost.

Description

Method and scrambling circuit for scrambling analog video signal

technical field

The invention relates to a method and circuit for processing analog video signals, in particular to a method and circuit for adding interference signals to analog video signals.

Background technique

With the rapid development of communication satellite and broadband network technology, high-quality movies and TVs are constantly increasing, which poses a major challenge to the pay-per-view industry. Television special channel programs and DVD programs have brought consumers super-high-quality visual enjoyment, yet some people have easily used video signal recording systems from unprotected programs to make commercial-quality copies of film and television programs. Illegal copying in this form seriously violates the interests of intellectual property owners and legitimate sellers. The anti-copy technology of analog video signal is developed for the anti-copy of special channel programs. This technology can prevent the copying of TV programs by home video recorders. Chinese patent application 86102600 discloses a "method and device for processing video signals to prohibit video tape recorders from accepting the signals". Scrambling is accomplished by adding the video signal to the pulse-pair sequence of pulses followed by the sync pulse, which prevents a home video recorder from copying a normal video signal for playback. The disadvantage of the above-mentioned scrambling technology is that the circuit design is complex, mainly using discrete components, and it is not suitable for high-definition color TVs that use a large number of digital processing technologies.

Contents of the invention

The object of the present invention is to provide a method and a scrambling circuit for scrambling analog video signals which are simple in structure, low in cost and suitable for high-definition color TV.

The general technical idea of the present invention is: the analog video signal is divided into two paths, one of which is used to form the time interval control signal for adding interference signals and not adding interference signals, and the sine wave signal as the interference signal is under the control of the control signal, It is added to another analog video signal in a corresponding time interval, so as to realize the scrambling processing of the analog video signal.

A kind of technical scheme of providing the method for scrambling the analog video signal in realizing the object of the present invention is: the analog signal is divided into two paths, wherein the analog signal of one path is controlled as the sine wave of the interference signal, at each analog video signal Add it to another analog video signal immediately after the field sync pulse in a vertical blanking time interval, so that when the analog video signal containing the sine wave interference signal is input into the ordinary home video recorder, the video signal of the video recorder can be recorded The automatic gain control system in the system got an incorrect indication when measuring the level of the scrambled video signal, which in turn produced gain corrections, resulting in abnormal video recordings.

In the above method, the frequency of the sine wave interference signal added to the analog video signal is 150 to 300 kHz, and the amplitude is 0.7 to 1 V; the length of the sine wave interference signal is 5 to 10 line periods.

Another technical scheme of providing a method for scrambling analog video signals in realizing the purpose of the present invention is: divide the analog signals into two paths, and add the Add the sine wave signal as the interference signal controlled by another analog signal and the sine wave signal as the interference signal controlled by one of the analog signals immediately after each equalization pulse, tooth pulse, and line synchronization pulse in the vertical blanking period to another analog video signal, so that when the analog video signal containing the sine wave interference signal is input into the home video recorder, the automatic gain control system in the video signal recording system of the video recorder can obtain False indications, resulting in gain corrections, resulting in abnormal video recordings.

In the above method, the frequency of the sine wave interference signal added to the analog video signal is 150 to 300kHz, and the amplitude is 0.7 to 1V; The duration of the sinusoidal interference signal after each equalization pulse, tooth pulse, and horizontal sync pulse is 1.5 to 2.5 microseconds.

The present invention provides a scrambling circuit for scrambling analog video signals, which has a synchronous signal separation circuit and a summation operation amplifier circuit; its structural characteristics are: it also has a timing circuit, an analog switch circuit, and a sine wave oscillation circuit and level correction circuit; the input end of the synchronous signal separation circuit is an analog video signal input end, the horizontal synchronous signal output end or the field synchronous signal output end of the synchronous signal separation circuit is connected with the input end of the timing circuit, and the output end of the timing circuit is connected with the timing circuit The control terminal of the analog switch circuit is connected; the output terminal of the sine wave oscillator circuit is connected with the input terminal of the video analog switch; the summation operation amplifier circuit has a video analog signal input terminal, a level correction signal input terminal, a sine wave signal input terminal and The scrambled analog video signal output terminal; the output terminal of the level correction circuit is connected to the level correction signal input terminal of the summing operation amplifier circuit, and the output terminal of the analog switch circuit is connected to the sine wave signal input terminal of the summation operation amplifier circuit.

The above synchronous signal separation circuit 1 has a video synchronous signal separator whose model is LM1881. The timing circuit 2 has double monostable flip-flops of model 74LS221, and the timing circuit 2 is a timing circuit capable of delaying and adjusting the pulse width of the synchronous signal. The analog switch circuit 3 has an integrated circuit model MAX4529. The sine wave oscillation circuit 4 is composed of an integrated operational amplifier and auxiliary circuits. The summing operation amplifier circuit 6 has an integrated circuit model of AD8055, and the summation operation amplifier circuit 6 sums and linearly amplifies the analog video signal, the sine wave signal and the level correction signal together to generate a scrambled video signal output.

For the analog video signal processed by the above-mentioned scrambling circuit, when it is output to the home video recorder for recording, because the automatic gain control system in the home video recorder is interfered, the home video recorder cannot perform normal processing on the scrambled analog video signal. Record. Therefore, the analog video signal processed by the circuit of the present invention can be played directly in the TV without any influence, but when the home video recorder records the scrambled analog video signal, it will record an abnormal signal. The image is severely distorted, resulting in jitter, blurred images and other phenomena.

The present invention has positive effect: (1) automatic gain control (AGC) circuit is all placed in television receiver and video recorder, and the effect of AGC circuit is when the intensity of input signal changes, automatically controls the gain of whole receiver , so that the output signal voltage remains constant. Currently, the average or peak type is used in television receivers, and the keyed type is used in video recorders. The biggest difference between the keying type and the average value type and the peak value type is that the detection of the keying type AGC is carried out under the control of the keying pulse. Since the keying pulse comes from the horizontal return pulse of the horizontal output transformer, the AGC The detection can only be carried out during the reverse travel period. The response speed of this AGC circuit is higher than that of the other two forms of AGC circuits. Using this feature, interference can be added to the appropriate position of the video signal to achieve interference with the AGC of the video recorder. circuit but does not affect the purpose of the TV AGC circuit. According to the difference in the operating principle of the AGC circuit of the TV set and the video recorder, if after the scrambling circuit of the present invention is set on the analog video signal channel of the TV set or the video disc player, the analog video signal of the input TV set or the upcoming output video disc player can be processed Scrambling processing, that is, adding an interference signal of appropriate amplitude and duration to the signal immediately following the synchronous signal in the analog video signal to obtain a scrambled analog video signal. The scrambled analog video signal can be played normally on the TV, but if it is recorded with a home video recorder, the level of the input analog video signal is disturbed due to the function of the automatic gain control system in the home video recorder, and it is recorded to It will be an abnormal signal, so what will be produced on the television set during playback is a poor quality, unstable picture. (2) The present invention adopts sine wave signal to carry out scrambling processing to analog video signal, and its anti-copy effectiveness is higher, and sine wave scrambling has less impact on the brightness of TV signal than pulse wave scrambling, and the adjustable range of parameters Wide, the field of video signal processing is relatively broadened. (3) The scrambling circuit of the present invention is especially suitable for high-definition color TV, and has simple design and low cost. (4) After the scrambling circuit of the present invention adopts an integrated module, it has high reliability and lower cost.

Description of drawings

Fig. 1 is the original block diagram of the scrambling circuit of the present invention.

Fig. 2 is a waveform diagram of adding a sine wave interference signal after the field sync pulse of the analog video signal according to the present invention.

Fig. 3 is a waveform diagram of adding a sine wave interference signal to the back porch of the horizontal sync pulse of the analog video signal according to the present invention.

Fig. 4 is a waveform diagram of adding a sine wave interference signal after the equalization pulse in the vertical blanking period of the analog video signal according to the present invention.

Fig. 5 is a waveform diagram of adding a sine wave interference signal after the tooth pulse in the vertical blanking period of the analog video signal according to the present invention.

Fig. 6 is a waveform diagram of adding a sine wave interference signal after the horizontal sync pulse in the vertical blanking period of the analog video signal according to the present invention.

Fig. 7 is a waveform diagram at selected points of each relevant circuit when a sine wave interference signal is added after the field sync pulse in the scrambling circuit of the present invention.

Fig. 8 is a waveform diagram at selected points of each relevant circuit when a sinusoidal interference signal is added to the back porch of the horizontal sync pulse in the scrambling circuit of the present invention.

FIG. 9 is a schematic circuit diagram of the scrambling circuit of the present invention.

FIG. 10 is another schematic circuit diagram of the scrambling circuit of the present invention.

Detailed ways

(Example 1)

Referring to FIG. 1 , the scrambling circuit of this embodiment has a synchronous signal separation circuit 1 , a timing circuit 2 , an analog switch circuit 3 , a sine wave oscillation circuit 4 , a level correction circuit 5 , and a summation operation amplifier circuit 6 . The input end of the synchronous signal separation circuit 1 is an analog video signal input end, the field synchronous signal output end of the synchronous signal separation circuit 1 is connected with the input end of the timing circuit 2, and the output end of the timing circuit 2 is connected with the control end of the analog switch circuit 3 The output end of the sine wave oscillation circuit 4 is connected to the input end of the analog switch circuit 3; the summation operation amplifier circuit 6 has an analog video signal input end, a level correction signal input end, a sine wave signal input end and a scrambled analog Video signal output terminal; the output terminal of the level correction circuit 5 is connected to the level correction signal input terminal of the summing operation amplifier circuit 6, and the output terminal of the analog switch circuit 3 is connected to the sine wave signal input terminal of the summation operation amplifier circuit 6.

As shown in Fig. 9, the synchronous signal separation circuit 1 has a synchronous signal separator U1 whose model is LM1881; the timing circuit 2 is a timing circuit capable of delaying and adjusting the pulse width of the synchronous signal, and the timing circuit 2 has a double monostable circuit whose model is 74LS221 state trigger U4; the analog switch circuit 3 has an integrated circuit U3 whose model is MAX4529; the sine wave oscillation circuit 4 has an integrated operational amplifier circuit U5 whose model is LM318; It is a Zener diode of 1N4733A; the level correction circuit 5 has a variable resistance. The scrambling circuit of this embodiment also has a connector J1, and J1 has a video signal input terminal and a video signal output terminal, and its video signal output terminal is connected with the DC blocking capacitor C1 of the synchronous signal separation circuit 1 on the one hand, and connected with the DC blocking capacitor C1 of the synchronization signal separation circuit 1 on the other hand. It is connected with the resistor R1 of the operational amplifier circuit 6 . The other end of capacitor C1 is connected to pin 2 of U1; the VCC end of pin 8 of U1 is the positive power supply end, and is connected with filter capacitor C8; the SET end of pin 6 of U1 is connected with an auxiliary circuit composed of capacitor C2 and resistor R11 in parallel; The 3-pin VSO terminal of U1 is connected to the 1-pin of U4 of the timing circuit 2, the 2-pin and 3-pin of U4 are in line and connected to the power supply VCC, and grounded through the capacitor C4, and a capacitor is connected between the 14-pin and 15-pin of U4 There is a variable resistor RP2 connected between C3 and pin 15 of U4 and the power supply VCC; pin 4 of U4 is directly connected to pin 10, pin 9 of U4 is grounded, pin 11 is connected to the power supply VCC, pin 6 and pin 7 of U4 are connected There is a capacitor C6, and a variable resistor RP5 is connected between pin 7 of U4 and the power supply VCC; pin 12 of the output terminal of U4 is connected to pin 4 of the control signal input terminal of U2 of the analog switch circuit 3, and the VCC terminal of pin 8 of U2 is positive The power supply terminal is connected with a filter capacitor C9, and the other end of the capacitor C9 is grounded; the 5th pin of U2 is grounded. The 7-pin and 4-pin of the amplifier U5 of the sine wave oscillation circuit 4 are respectively connected to the power supply VCC and the power supply -VCC; the resistor R7 is connected between the inverting input terminal 2 of U5 and the output terminal 6 pin, and the inverting input terminal 2 of U5 The foot is grounded through the variable resistor R9; the negative pole of the Zener diode D1 is connected to the negative pole of the Zener diode D2, and the variable resistor R6 is connected in parallel between the positive pole of the Zener diode D1 and the positive pole of the Zener diode D2, and the Zener diode D1 The positive pole is grounded, the positive pole of the Zener diode D2 is connected to the capacitor C7, and the other end of the capacitor C7 is connected to the input terminal 6 of U5; the positive pole of the Zener diode D2 is also connected to the variable resistor R12, and the other end of the variable resistor R12 is connected to the The positive phase input terminal 3 pin of U5 is connected, and the positive phase input terminal 3 pin of U5 is also grounded through the capacitor C5; the output terminal 6 pin of U5 is connected with the variable resistor R8, and the other end of the variable resistor R8 is connected with the analog switch circuit U2 The signal input terminal is connected to 2 pins. Pin 7 of U2 is connected to the resistor R5 of the summation operational amplifier circuit 6; the other end of the resistor R5 is connected to the variable resistor RP3, the other end of the variable resistor RP3 is grounded, and the common contact of the resistor R5 and the variable resistor RP3 is connected to the resistor R4 One end is connected, and the other end of the resistor R4 is connected to the 3-pin signal input terminal of U3 of the summation operational amplifier circuit 6; the 7-pin of U3 is connected to the power supply VCC, and the 4-pin of U3 is connected to the power supply-VCC; the 2-pin of U3 is grounded through the resistor R2 , also connected to the output terminal 6 of U3 through the serial connection resistor R3 and the variable resistor RP4, and the output terminal 6 of U3 is connected to the connector J2; the video signal output from the connector J1 passes through the resistor R1 and connected to the 3 pin of U3 The two ends of the variable resistance RP1 of the level correction circuit 5 are respectively connected to the power supply VCC and the power supply -VCC, and the variable termination resistor R10 of RP1 is connected to the input terminal 3 of U3.

See Fig. 2, in the scrambling circuit of the present embodiment, in processing the input analog video signal, the sine wave signal as the interference signal can be added after the field sync pulse in each field blanking time interval of the analog video signal to an analog video signal. Figure 2 shows a partial waveform diagram of the scrambled analog video signal, where the part labeled 10 is the image information, 11 is the field blanking width, 12 is the field synchronization pulse width, 19 is the line synchronization pulse, and 20 is the sine wave signal. The sine wave signal is added to the analog video signal after the field synchronization pulse. The frequency of the sine wave can be selected from a certain value in the range of 150 to 300kHz, and the amplitude can be selected from a certain value in the range of 0.7 to 1V. Analog The length of the sine wave intercepted by the switch circuit 3 selects a certain value within the length range of 5 to 10 line periods.

See Fig. 7 and Fig. 9, during the scrambling process, the analog video signal is divided into two paths, and one path of analog video signal is separated by the synchronous signal separation circuit 1 to output the field synchronous signal, and the field synchronous signal is the first sawtooth wave in the field synchronous pulse period The rising edge of the field synchronization signal is generated, and the field synchronization signal is delayed through the timing circuit 2. As shown in Figure 7, the delay process is as follows: when the field synchronization signal passes through the first-stage monostable flip-flop U4A, the falling edge of the field synchronization pulse triggers the first The first-stage monostable trigger U4A makes it output the negative monostable signal of the previous stage, and by adjusting the variable resistor RP2 in the timing circuit 2, the negative monostable signal of the previous stage output by the first-stage monostable flip-flop U4A The negative length of the steady state signal is the length of 5 line periods; the negative monostable signal of the previous stage is connected to the second stage monostable trigger U4B, and the first stage is triggered on the rising edge of the negative monostable signal of the previous stage. The second-stage monostable trigger U4B makes it output the post-stage negative monostable signal, and by adjusting the variable resistor RP5 in the timing circuit 2, the post-stage negative monostable signal output by the second-stage monostable trigger U4B The negative-going length of the steady-state signal is 5 line period lengths. The subsequent negative monostable signal obtained by the delay of the timing circuit 2 is connected to the control signal input terminal of the analog switch circuit 3 to control the turn-on moment and turn-on time of the analog switch circuit 3 . The sine wave oscillating circuit 4 is used to generate a sine wave signal; by adjusting the variable resistors R6 and R12 in the sine wave oscillating circuit 4, the frequency of the output sine wave signal is 150 kHz, and by adjusting the variable resistor R8, the output sine wave The amplitude of the wave signal is 0.7V; the sine wave signal is transmitted to the summation operation amplifier circuit 6 through the analog switch circuit 3, and the negative monostable signal of the rear stage generated by the timing circuit 2 drops when the analog switch circuit 3 is turned on. Edge control, the turn-on time length of the analog switch circuit 3 is controlled by the length of the negative time of the negative monostable signal of the subsequent stage, so that the analog switch circuit 3 completes the interception of the passed sine wave signal within the time it is turned on , and output the intercepted sine wave signal to the summing operation amplifier circuit 6 .

The intercepted sine wave signal, another analog video signal and the level correction signal generated by the level correction circuit 5 are amplified and output after being superimposed in the summation operation amplifier circuit 6, and the variable resistor in the summation operation amplifier circuit 6 RP3 is a balancing resistor, and the variable resistor RP4 adjusts the voltage gain at the output terminal. Since the processed analog video signal will produce a shift phenomenon, resulting in image darkening and jittering, it is necessary to add a level correction signal when superimposing, so a level correction circuit 5 is provided. The output scrambled analog video signal has no effect when it is played directly, but after being recorded by a home video recorder, the image is severely distorted during playback, resulting in jitter and blurred images.

(Example 2)

See Fig. 7 and Fig. 9, the remaining part of this embodiment is basically the same as embodiment 1, and difference is: in the time-delay process of timing circuit 2, by adjusting variable resistor RP2 in timing circuit 2, the first stage The monostable trigger U4A generates a negative monostable signal of the previous stage with a length of 8 line periods; by adjusting the variable resistor RP5 in the timing circuit 2, the second-stage monostable trigger U4B generates a 8 line period The post-stage negative monostable signal of the length; by adjusting the variable resistors R6 and R12 in the sine wave oscillating circuit 4, the frequency of the sine wave signal output by the sine wave oscillating circuit 4 is 250kHz; The variable resistor R8 makes the amplitude of the sine wave output by the sine wave oscillation circuit 4 be 0.8V.

(Example 3)

See Fig. 7 and Fig. 9, the remaining part of this embodiment is basically the same as embodiment 1, and difference is: in the time-delay process of timing circuit 2, by adjusting variable resistor RP2 in timing circuit 2, the first stage The monostable trigger U4A generates a negative monostable signal of the previous stage with a length of 10 line periods; the second-stage monostable trigger U4B generates a 10 line period by adjusting the variable resistor RP5 in the timing circuit 2 The post-stage negative monostable signal of length; By adjusting the variable resistors R6 and R12 in the sine wave oscillating circuit 4, the frequency of the sine wave output by the sine wave oscillating circuit 4 is 300kHz; The variable resistor R8 makes the amplitude of the sine wave signal output by the sine wave oscillation circuit 4 be 1V.

(Example 4)

See Fig. 1, the scrambling circuit of the present embodiment has synchronous signal separation circuit 1, timing circuit 2, analog switch circuit 3, sine wave oscillation circuit 4 and level correction circuit 5, summation operation amplifier circuit 6; Synchronous signal separation circuit The input terminal of 1 is the analog video signal input terminal, the line synchronization signal output terminal of the synchronous signal separation circuit 1 is connected with the input terminal of the timing circuit 2, and the output terminal of the timing circuit 2 is connected with the control terminal of the analog switch circuit 3; sine wave oscillation The output end of the circuit 4 is connected with the input end of the analog switch circuit 3; the summation operation amplifier circuit 6 has an analog video signal input end, a level correction signal input end, a sine wave signal input end and an analog video signal output end after scrambling The output terminal of the level correction circuit 5 is connected to the level correction signal input terminal of the summing operation amplifier circuit 6, and the output terminal of the analog switch circuit 3 is connected to the sine wave signal input terminal of the summation operation amplifier circuit 6.

As shown in Figure 10, the synchronous signal separation circuit 1 has a synchronous signal separator U1 whose model is LM1881, the timing circuit has a double monostable flip-flop U4 whose model is 74LS221, and the analog switch circuit 3 has an integrated circuit U3 whose model is MAX4529. Oscillating circuit 4 has model LM318 integrated operational amplifier circuit U5, summation operational amplifier circuit 6 has model integrated circuit U3 of AD8055, and a model of Zener diode 1N4733A; level correction circuit 5 has a variable resistor. The scrambling circuit of this embodiment also has a connector J1, and J1 has a video signal input terminal and a video signal output terminal, and its video signal output terminal is connected with the DC blocking capacitor C1 of the synchronous signal separation circuit 1 on the one hand, and connected with the DC blocking capacitor C1 of the synchronization signal separation circuit 1 on the other hand. It is connected with the resistor R1 of the operational amplifier circuit 6 . The other end of capacitor C1 is connected to pin 2 of U1; the VCC end of pin 8 of U1 is the positive power supply end, and is connected with filter capacitor C8; the SET end of pin 6 of U1 is connected with an auxiliary circuit composed of capacitor C2 and resistor R11 in parallel; The 5-pin BO terminal of U1 is connected to the 1-pin of U4 of the timing circuit 2, the 2-pin and 3-pin of U4 are in line and connected to the power supply VCC, and grounded through the capacitor C4, and the 14-pin and 15-pin of U4 are connected with Capacitor C3, variable resistor RP2 is connected between pin 15 of U4 and power supply VCC; pin 4 of U4 is directly connected to pin 10, pin 9 of U4 is grounded, pin 11 is connected to power supply VCC, between pin 6 and pin 7 of U4 A capacitor C6 is connected, and a variable resistor RP5 is connected between pin 7 of U4 and the power supply VCC; pin 12 of the output terminal of U4 is connected with pin 4 of the control signal input terminal of U2 of the analog switch circuit 3, and the VCC terminal of pin 8 of U2 is The positive power supply terminal is connected to the filter capacitor C9, and the other end of the capacitor C9 is grounded; the 5th pin of U2 is grounded. The 7-pin and 4-pin of the amplifier U5 of the sine wave oscillation circuit 4 are respectively connected to the power supply VCC and the power supply -VCC; the resistor R7 is connected between the inverting input terminal 2 of U5 and the output terminal 6 pin, and the inverting input terminal 2 of U5 The foot is grounded through the variable resistor R9; the negative pole of the Zener diode D1 is connected to the negative pole of the Zener diode D2, and the variable resistor R6 is connected in parallel between the positive pole of the Zener diode D1 and the positive pole of the Zener diode D2, and the Zener diode D1 The positive pole is grounded, the positive pole of the Zener diode D2 is connected to the capacitor C7, and the other end of the capacitor C7 is connected to the input terminal 6 of U5; the positive pole of the Zener diode D2 is also connected to the variable resistor R12, and the other end of the variable resistor R12 is connected to the The positive phase input terminal 3 pin of U5 is connected, and the positive phase input terminal 3 pin of U5 is also grounded through the capacitor C5; the output terminal 6 pin of U5 is connected with the variable resistor R8, and the other end of the variable resistor R8 is connected with the analog switch circuit U2 The signal input terminal is connected to 2 pins. Pin 7 of U2 is connected to the resistor R5 of the summation operational amplifier circuit 6; the other end of the resistor R5 is connected to the variable resistor RP3, the other end of the variable resistor RP3 is grounded, and the common contact of the resistor R5 and the variable resistor RP3 is connected to the resistor R4 One end is connected, and the other end of the resistor R4 is connected to the 3-pin signal input terminal of U3 of the summation operational amplifier circuit 6; the 7-pin of U3 is connected to the power supply VCC, and the 4-pin of U3 is connected to the power supply-VCC; the 2-pin of U3 is grounded through the resistor R2 , also connected to the output terminal 6 of U3 through the serial connection resistor R3 and the variable resistor RP4, and the output terminal 6 of U3 is connected to the connector J2; the video signal output from the connector J1 passes through the resistor R1 and connected to the 3 pin of U3 The two ends of the variable resistance RP1 of the level correction circuit 5 are respectively connected to the power supply VCC and the power supply -VCC, and the variable termination resistor R10 of RP1 is connected to the input terminal 3 of U3.

See Fig. 3, Fig. 4, Fig. 5, Fig. 6, the scrambling circuit of the present embodiment is in processing the input analog video signal, can add the sine wave as interference signal on the back shoulder of each horizontal synchronous pulse of analog video signal The wave signal and the sine wave signal as the interference signal are added to the analog video signal immediately after each equalizing pulse, tooth pulse, and horizontal sync pulse in the vertical blanking period.

Figure 3 shows a partial waveform diagram of adding a sine wave interference signal to the shoulder after the horizontal sync pulse, wherein the part labeled 10 is the image information, 13 is the width of the line blanking pulse, and 14 is the width of the front shoulder of the line blanking pulse. 15 is the line sync pulse width, 16 is the back porch width of the line sync pulse, 20 is the sine wave signal, the sine wave interference signal is added at the trigger edge following the line sync pulse, and the frequency of the sine wave can be in the range of 150 to 300kHz Select a definite value within the range of 0.7 to 1V for the amplitude, and select a definite value within the range of 1.5 to 2.5 microseconds for the duration of the sine wave signal intercepted by the analog switch circuit 3. value.

Figure 4 shows a part of the waveform diagram of the interference signal added after the equalization pulse in the vertical blanking area, where the part marked 17 is the equalization pulse, 20 is the added sine wave, and the sine wave interference signal is added to each equalization pulse , the sine wave frequency can select a certain value in the range of 150 to 300kHz, the amplitude can select a certain value in the range of 0.7 to 1V, and the duration of the sine wave signal intercepted by the analog switch circuit 3 is 1.5 Select a certain value within the range of 2.5 microseconds.

Fig. 5 has provided the part waveform diagram of adding interference signal after the tooth pulse of field blanking zone, wherein the part marked as 18 is the tooth pulse width, 20 is the sine wave added, and 21 is the slotting pulse, following each Add a sine wave interference signal to the rising edge of the tooth pulse. The sine wave frequency can be selected from a certain value in the range of 150 to 300kHz, and the amplitude can be selected from a certain value in the range of 0.7 to 1V. The duration of the sine wave signal It is to choose a certain value in the range of 1.5 to 2.5 microseconds.

Fig. 6 has provided the part waveform diagram of interfering signal added after the horizontal synchronous pulse in the field blanking area, wherein the part labeled 19 is the horizontal synchronous pulse, and 20 is the added sine wave, following each horizontal synchronous pulse. Add a sine wave interference signal, the sine wave frequency can choose a certain value in the range of 150 to 300kHz, the amplitude can choose a certain value in the range of 0.7 to 1V, and the duration of the sine wave signal is 1.5 to 2.5 Choose a definite value in the range of microseconds.

See Fig. 8 and Fig. 10, in the process of scrambling, the analog video signal is divided into two paths, and one path of analog video signal is separated by the synchronous signal separation circuit 1 to output the horizontal synchronous signal, and the output horizontal synchronous signal is divided into horizontal synchronous pulse, equalized The rising edge of the pulse and tooth pulse is generated; the output line synchronization signal is delayed through the timing circuit 2, as shown in Figure 8, the delay process is as follows: when the line synchronization signal passes through the first-stage monostable flip-flop U4A, the line synchronization The falling edge of the signal triggers the first-stage monostable trigger U4A to make it output the negative monostable signal of the previous stage. By adjusting the variable resistor RP2 in the timing circuit 2, the first-stage monostable trigger U4A outputs The negative length of the negative monostable signal of the previous stage is 0.4 microseconds; the negative monostable signal of the previous stage is input into the second stage monostable flip-flop U4B, and the rising edge of the negative monostable signal of the previous stage Trigger the second-stage monostable trigger U4B to make it output the negative monostable signal of the rear stage, and adjust the variable resistor RP5 in the timing circuit 2 to make the output of the second-stage monostable flip-flop U4B output negative monostable signal. The negative-going length of the monostable signal is 1.5 microseconds. The subsequent negative monostable signal obtained by the delay of the timing circuit 2 is connected to the control signal input terminal of the analog switch circuit 3 to control the turn-on moment and turn-on time of the analog switch circuit 3 . By adjusting the variable resistors R6 and R12 in the sine wave oscillation circuit 4, the frequency of the output sine wave is 150kHz; by adjusting the variable resistor R8, the amplitude of the output sine wave is 0.7V, and the sine wave signal is passed through the analog The switch circuit 3 is output to the summing operation amplifier circuit 6, the opening moment of the analog switch circuit 3 is controlled by the falling edge of the rear stage negative monostable signal output by the timing circuit 2, and the opening time length of the analog switch circuit 3 is controlled by the rear stage The length of the negative time of the negative monostable signal is controlled, so that the analog switch circuit 3 completes the interception of the passed sine wave signal within the time it is turned on, and outputs the intercepted sine wave to the summation operational amplifier circuit 6 wave signal.

The intercepted sine wave signal and another analog video signal and the level correction circuit 5 generate a level correction signal, which is superimposed in the summation operation amplifier circuit 6 and then amplified and output. In the summation operation amplifier circuit 6, the variable resistor RP3 To balance the resistors, variable resistor RP4 adjusts the voltage gain at the output. Since the processed video signal will be shifted, resulting in image darkening and jittering, it is necessary to add a level correction signal when superimposing, so a level correction circuit 5 is provided. The output scrambled analog video signal has no effect when it is played directly, but after being recorded by a home video recorder, the image is severely distorted during playback, resulting in jitter and blurred images.

(Example 5)

See Fig. 8 and Fig. 10, the remaining part of this embodiment is basically the same as embodiment 4, and difference is: in the time-delay process of timing circuit 2, by adjusting variable resistance RP2 in timing circuit 2, the first stage The monostable trigger U4A generates a negative monostable signal with a length of 2 microseconds; by adjusting the variable resistor RP5 in the timing circuit 2, the second monostable trigger U4B generates a negative monostable signal with a length of 2 microseconds. The negative monostable signal of the latter stage; by adjusting the variable resistors R6 and R12 in the sine wave oscillating circuit 4, the frequency of the output sine wave is 250kHz; by adjusting the variable resistor R8 in the sine wave oscillating circuit 4, the output The amplitude of the sine wave is 0.8V.

(Example 6)

See Fig. 8 and Fig. 10, the remaining part of this embodiment is basically the same as embodiment 4, and difference is: in the time-delay process of timing circuit 2, by adjusting variable resistance RP2 in timing circuit 2, the first stage The monostable trigger U4A generates a 3.5 microsecond long negative monostable signal; by adjusting the variable resistor RP5 in the timing circuit 2, the second monostable trigger U4B generates a 2.5 microsecond long The post-stage negative monostable signal; by adjusting the variable resistors R6 and R12 in the sine wave oscillating circuit 4, the frequency of the output sine wave is 300kHz; by adjusting the variable resistor R8 in the sine wave oscillating circuit 4, the output The amplitude of the sine wave is 1V.

Claims (8)

1, a kind of method for processing analog video signal, it is characterized in that: the method comprises analog signal is divided into two roads, wherein one road analog signal controls as the sine wave of interference signal, in each field blanking time interval of analog video signal It is added to another analog video signal immediately after the field sync pulse, so that when the analog video signal containing sine wave interference signal is input into a common home video recorder, the automatic gain control in the video signal recording system of the video recorder The system gets an incorrect indication when measuring the level of the scrambled video signal, which in turn produces a gain correction, resulting in an abnormal video recording. 2. The method for processing analog video signals according to claim 1, characterized in that: the frequency of the sine wave interference signal added to the analog video signal is 150 to 300 kHz, and the amplitude is 0.7 to 1V; The length is 5 to 10 line periods in length. 3. A method for processing an analog video signal, characterized in that: the method comprises dividing the analog signal into two paths, and adding a function controlled by another analog signal on the rear shoulder of each horizontal sync pulse of one path of the analog video signal. The sine wave signal of the interference signal and the sine wave signal controlled by one of the analog signals as the interference signal are added to the other analog video signal immediately after each equalization pulse, tooth pulse, and line synchronization pulse in the vertical blanking period , so that when the analog video signal containing the sine wave interference signal is input to a common home video recorder, the automatic gain control system in the video signal recording system of the video recorder will get an error indication when measuring the level of the scrambled video signal, and then generate a gain Correction, resulting in abnormal video recording. 4. The method for processing analog video signals according to claim 3, characterized in that: the frequency of the sine wave interference signal added to the analog video signal is 150 to 300kHz, and the amplitude is 0.7 to 1V; The duration of the sine wave signal on the shoulder after the sync pulse and the sine wave interference signal added after each equalization pulse, tooth pulse, and horizontal sync pulse during the vertical blanking interval is 1.5 to 2.5 microseconds. 5. A scrambling circuit for scrambling analog video signals, which has a synchronous signal separation circuit (1), a summation operation amplifier circuit (6); it is characterized in that it also has a timing circuit (2), an analog switch Circuit (3), sine wave oscillation circuit (4) and level correction circuit (5); the input end of the synchronous signal separation circuit (1) is the analog video signal input end, and the line synchronous signal output of the synchronous signal separation circuit (1) terminal or field synchronous signal output end is connected with the input end of timing circuit (2), and the output end of timing circuit (2) is connected with the control end of analog switch circuit (3); The output end of sine wave oscillation circuit (4) is connected with analog The input end of the switch circuit (3) is connected; the summation operation amplifier circuit (6) has an analog video signal input end, a level correction signal input end, a sine wave signal input end and an analog video signal output end after scrambling; the level The output terminal of the correction circuit (5) is connected to the level correction signal input terminal of the summing operation amplifier circuit (6), and the output terminal of the analog switch circuit (3) is connected to the sine wave signal input terminal of the summation operation amplifier circuit (6). 6. The scrambling circuit for scrambling the analog video signal according to claim 5, characterized in that the timing circuit (2) is a timing circuit capable of delaying and adjusting the pulse width of the synchronous signal. 7. The scrambling circuit for scrambling analog video signals according to claim 6, characterized in that: the timing circuit (2) has a model of 74LS221 double monostable flip-flops. 8. The scrambling circuit for scrambling analog video signals according to claim 5, characterized in that: the analog switch circuit (3) has an integrated circuit model of MAX4529; the sine wave oscillator circuit (4) is composed of integrated The operational amplifier and its auxiliary circuit are composed; the synchronous signal separation circuit (1) has a video synchronous separator whose model is LM1881; the summation operation amplifier circuit (6) has an integrated circuit whose model is AD8055.

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