CN100433697C - Multi-channel high-speed data processor and processing method - Google Patents

Abstract

The multi-channel high-speed data processor and processing method is a high-speed data processing device in the field of wireless network security. It adopts a field programmable gate array as a basic platform and is a multi-channel high-speed data processing system. The processor specifically includes the following four modules: field programmable gate array hardware module (1), 4 times data rate interface module (2), programmable read-only memory program configuration module (3) and software system module (4) ; At first send read and write information and data information by network processor, queue scheduling module (4.1) obtains reading and writing and data information thereof from network processor, after receiving module (4.2) obtains corresponding write command from queue scheduling module (4.1) , carry out the corresponding write operation on the buffer, and the processed data is transferred to the frame verification sequence module (4.5), and then transferred to the sending data buffer module (4.3) after verification, and the data is written into the buffer after comprehensive processing and judgment. The processed data is output through the read operation of the buffer.

Description

Multi-channel high-speed data processor and processing method

technical field

The device of the invention is a high-speed data processing device in the field of wireless network security, which uses a field programmable gate array (FPGA) as a basic platform, and is a multi-channel high-speed data processing system.

Background technique

The application of services such as high-speed packet data, multimedia data and Internet promotes the upgrade of Code Division Multiple Access (CDMA) from IS-95 to CDMA20001X. The International Organization for Standardization 3GPP2 has formulated the relevant standards of CDMA20001X packet data network, and adopted the existing work results of IETF in mobile IP technology, so that the network has the ability to quickly provide IP access, interoperability with other IP networks, and better Roaming capability and IP service capability of private network, and enable the system to provide 144Kbps, 384Kbps and 2Mbps access rate and simple IP and mobile IP service functions.

In the CDMA20001X network, the end-to-end protocol (PPP) is used as the data link protocol between the mobile station MS or mobile phone and the packet data service node (PDSN). For the IP packet from the WAN to the mobile node, the packet data service node will map it to a specific end-to-end protocol connection, and send the IP packet by looking up the mapping relationship between the IP address of the destination mobile phone and the corresponding A10 connection For the mobile phone terminal; when receiving an IP packet from the Home Agent Home Agent (HA) of a registered mobile phone terminal, the packet data service node can find the corresponding R-P connection according to the IP address of the HA and the IP address of the mobile phone terminal, Send data packet; for the IP data packet from the mobile phone, the mobile phone terminal encapsulates it in the end-to-end protocol data packet and sends it to the network, after being transmitted through the wireless air interface and the base station, the packet control function (PCF ) component encapsulates the end-to-end protocol data of the mobile terminal in a general routing protocol (GRE) tunnel and transmits it to the packet data service node, and then the packet data service node on the network side unpacks and reassembles the tunnel encapsulated data packet It is routed to the IP backbone network on the network side, or sent to its home agent HA through a reverse tunnel.

When the network processor-based mobile Internet content monitoring equipment intercepts, filters and analyzes information in the CDMA packet data domain, it needs to connect the high-speed data link control protocol (HDLC) frame of the end-to-end protocol into a complete data packet, which is Sometimes it is necessary to escape or reverse the high-speed data link control protocol data frame to restore the original data. However, if this kind of work is completed by the network processor, it will increase the overhead of the system and greatly affect the performance of the system.

Contents of the invention

Technical problem: the purpose of this invention is to provide a multi-channel high-speed data processing system. We have designed a multi-channel high-speed data processing system to assist the host to work, thereby realizing high-speed real-time processing of mobile Internet content supervision data, reducing the burden on the host, and improving efficiency.

Technical solution: the present invention adopts the method of adding a field programmable gate array coprocessor to complete the multi-channel asynchronous high-speed data link control protocol processing function, and communicates with the host computer through the 4 times data rate (QDR) interface, and converts the original processing by software Some work is done by hardware, which reduces the burden on the host and improves efficiency.

With the development of microelectronics technology, Field Programmable Gate Array (FPGA) devices have been developed rapidly. Due to their characteristics of fast working speed, high integration and field programmable, etc., they have been widely used in digital signal processing. The present invention is based on the basic principle of the high-speed data link control protocol, and the field programmable gate array chip Spartan series device (XC3S2000-4FG676C) of Xilinx Company has completed the design of the present invention. The high-speed data link control protocol is a bit-oriented protocol that supports half-duplex and full-duplex communication. It is widely used in the field of data communication and is the technology of many other data link control protocols. It has strong error detection, high efficiency and synchronous transmission characteristics. At present, many network routing devices and switches use high-speed data link control protocol as their link protocol.

The high-speed data processor of the present invention mainly performs parallel decapsulation and end-to-end protocol packet antisense processing on the multi-channel high-speed data link control protocol frames from the host, and finally feeds back the result to the host for further reorganization and protocol processing. Thereby alleviating the overload of the mainframe and the pressure of excessive system overhead, ensuring the high-speed operation of the entire mobile Internet monitoring system. The multi-channel high-speed data processing system that the present invention proposes has followed the international standard of IEEE on the one hand, has realized the basic function of standard regulation---escaping/anti-escaping of high-speed data link control protocol frame and cyclic redundancy code check ( CRC) check; on the other hand, it also provides an expandable and flexible interface to expand the processor according to the actual needs in the future; in addition, after the processor is designed, it can be used on the developed software or hardware With a little modification, the processor can be transformed into other communication products, such as frame relay system, integrated services digital network (ISDN), X.25 data network, backbone and edge routers and other data environment network environments, so this High-speed data link control protocol processors still have quite broad application prospects.

The structure of the equipment of the present invention is as follows:

The invention comprises field programmable gate array hardware module, 4 times data rate interface module, programmable read-only memory program configuration module and software system module and other four parts. in:

1. Field programmable gate array hardware module

2 million field programmable gate arrays are used as the coprocessor of the host computer, which occupies a core position in the device. The field programmable gate array communicates with the 4X data rate interface through the LA_1 protocol. The I/O level output complies with the HSTL_1_DCI (1.5V) standard, for which an additional 0.75V reference level is required. The field programmable gate array receives configuration information through a serial interface with the Flash programmable read-only memory (FLASH PROM). In addition, the field programmable gate array can be directly configured and debugged through the JTAG interface. After power-on, the field programmable gate array reads data from the programmable read-only memory (PROM) by itself, and can also be reconfigured through the reset signal in the working state.

2, 4 times the data rate interface module

Connect the motherboard and the device to provide communication and data interaction between the device and the host. Additionally, all power to the device is provided by this interface.

(1) Internal integrated circuit bus interface, the interface accesses the internal integrated circuit E2PROM on the card through the internal integrated circuit (I2C) bus to obtain device information such as the device identifier, operating level and temperature, thereby identifying the device.

(2) 4 times the data rate interface, the 16-bit data interface of the device is multiplied under the double clock drive to become a logic 32-bit. The bus provides quadruple-speed input and output ports and 24-bit address line width that can work simultaneously.

(3) JTAG debugging interface, although the LA_1 standard includes the JTAG interface, but it is limited to providing a test interface (does not support the programming of the programmable read-only memory and the field programmable gate array), so the JTAG plug-in is also introduced in the design slot, directly download the program to the programmable read-only memory through the PC.

(4) Peripheral power supply module, 4 times data rate interface provides +3.3V, +1.8V and +1.5V DC voltage for the device. In addition, voltages such as 2.5V, 1.2V, 0.75V are locally generated by the device through +3.3V.

3. Programmable read-only memory program configuration module

(1) The internal integrated circuit bus programmable read-only memory circuit records coprocessor device information, including device ID, operating level and temperature and other parameters. When the system starts, the 4 times data rate interface detects it through the internal integrated circuit bus to identify the device. In addition, the internal integrated circuit programmable read-only memory itself also supports password encryption and password protection.

(2) The Flash programmable read-only memory circuit automatically configures the field programmable gate array when it is powered on. Its configuration mode is divided into two modes: master and slave. The main difference lies in the different configuration clock signal sources. In the field programmable gate array master control mode, the field programmable gate array provides a configuration clock signal for the programmable read-only memory, and in the field programmable gate array controlled mode, an external crystal oscillator provides a configuration clock signal.

4. Software system modules:

The software system module realizes the multi-channel data processing function of the whole field programmable gate array. Each driver module is written in the way of dynamic module loading.

The software system module mainly includes the following parts: queue scheduling module, receiving data buffer module, sending data buffer module, high-speed data link control protocol data packet anti-sense and flag word processing module, frame verification sequence module.

Structurally, the processor specifically includes the following four modules: a field programmable gate array hardware module; a 4 times data rate interface module; a programmable read-only memory program configuration module and a software system module; the 4 times data rate interface module The module includes: internal integrated circuit bus interface, 4 times data rate interface, JTAG interface and peripheral power supply module; the field programmable gate array hardware module is connected to the external host computer through the 4 times data rate interface, connected to the peripheral power supply module through the power line and through The JTAG interface is connected with the Flash programmable read-only memory circuit in the programmable read-only memory program configuration module, and the Flash programmable read-only memory circuit is also connected with an external PC through the JTAG interface; the programmable read-only memory program configuration module The internal integrated circuit bus programmable read-only memory circuit is connected to the external host through the internal integrated circuit bus interface; the software system module includes: queue scheduling module, receiving data buffer module, sending data buffer module, high-speed data link control protocol Data packet anti-sense and its flag word processing module and frame check sequence module, the modules included in the software system module are connected together through signal transmission; the software system module resides in the programmable read-only memory program configuration module, After the multi-channel high-speed data processor works, the program is loaded into the field programmable gate array hardware module, and the field programmable gate array hardware module is connected with the program of the host computer through the 4 times data rate interface module.

The field programmable gate array hardware module adopts 2 million "XC3S2000" field programmable gate arrays as the coprocessor of the host computer.

In the 4x data rate interface module, the peripheral power supply module uses the "TPS75525" voltage conversion chip when generating 2.5V voltage; uses the "TPS54312" voltage conversion chip when generating 1.2V voltage; when generating 0.75V voltage, Using "MAX1589EZTAFJ" chip.

In the programmable read-only memory program configuration module, the internal integrated circuit bus programmable read-only memory circuit is used to record the device information of the processor, including device identifiers, operating levels and temperature parameters. The read memory circuit performs detection to identify the multi-channel high-speed data processor, and the internal integrated circuit bus programmable read-only memory circuit itself also supports password encryption and password protection. In the programmable read-only memory program configuration module, the Flash programmable read-only memory circuit is used to automatically configure the field programmable gate array hardware module when it is powered on. There are two configuration modes: master control mode and controlled mode.

The high-speed data processing method of the multi-channel high-speed data processor is: in the software system module, firstly, the high-speed data processor sends the read-write information and data information, and the queue scheduling module obtains the read-write information and data information from the network processor, and receives the data cache After the module obtains the corresponding write command from the queue scheduling module, it performs a corresponding write operation on the buffer area of the receiving data buffer module, so as to facilitate the processing of high-speed data link control protocol data packet antisense and its flag word processing module. The effective frame signal, escape signal and high-speed data processor output data of the control signal are sent to the frame verification sequence module together, and the control signal write buffer signal, frame end signal, verification error signal and post verification are generated after verification. The data is passed into the sending data buffer module, and after the comprehensive processing and judgment of the sending data buffer module, the data data after verification is written into the buffer zone of the sending data buffer module, combined with the read information of the queue scheduling module, through the read operation of the buffer Processed data output. The software system module performs frame header search, cyclic redundancy check, antisense, discard sequence detection, frame length monitoring and frame tail search on the data of each channel. Once the information currently transmitted in a certain frame is detected When the number of digits reaches the maximum frame length or a discard sequence is detected, the state machine in the software system module ends the processing of the current frame, and searches for the frame header of a new frame again, while the remaining data in the current frame will not be processed . The software system module simultaneously processes high-speed data link control protocol data streams with up to 128 channels of parallel transmission. Its implementation adopts the method of time division multiplexing, in which the channel state memory is used to realize time division multiplexing, and each channel is stored in the channel state memory There is a fixed storage space among them, which is used to store the data processing status of the channel, that is, the channel status information. A certain length of time slice is allocated for each piece of data to be processed in each channel. At the end of each time slice , the latest state information of the current channel will be stored in the corresponding storage space in the channel state memory. When a new piece of data arrives, the state information of the channel to which this piece of data belongs that was refreshed in the previous time slice will be saved from the channel state memory. Read out and load into the state machine to prepare for a new round of data processing.

Beneficial effects: the multi-channel high-speed data processing device of the present invention has achieved good functional characteristics: the high-speed data link control protocol function stipulated in RFC1662 has been realized, and the functions of flag word detection, escape/anti-sense, and frame check sequence (FCS) have been realized , and has the characteristics of scalability and flexibility at the same time, which is convenient for future upgrades and expansions; the device of the present invention also realizes multi-channel parallel processing of high-speed data link control protocol data by adding receiving and sending modules, and improves the efficiency of the processor; The address bus of the 4x data rate interface is used as a control signal, which realizes bus multiplexing and improves bus utilization.

The invention is mainly based on field programmable gate arrays for high-speed data processing of high-speed data link control protocol data packets in mobile Internet content monitoring equipment. The present invention proposes a new design structure and implementation method in terms of hardware implementation; in terms of functions, it realizes the escape/anti-esense, cyclic redundancy code check function, and search of the frame head and frame tail in the function And its removal, the most important thing is to realize the end-to-end protocol packet processing when multiple users are online at the same time through the communication with the host, and achieve a high-speed processing capacity of 200Mbps. Functionally, it realizes high-speed processing of end-to-end protocol packets in the mobile Internet content supervision system.

Description of drawings

Figure 1 is a structural block diagram of a multi-channel high-speed data processing device based on a field programmable gate array;

Figure 24 schematic diagram of data rate interface module 2;

Fig. 3 Flash programmable read-only memory circuit 3.2 and field programmable gate array hardware module 1 connection diagram;

Fig. 4 PROM program configuration module 3 configuration flowchart;

Fig. 5 software module connection diagram;

The software status diagram of Fig. 6 equipment of the present invention;

Figure 7 is a state transition diagram of a single-channel high-speed data processor.

The above figure has: field programmable gate array hardware module 1, 4 times data rate interface module 2, programmable read-only memory program configuration module 3 and software system module 4; internal integrated circuit bus interface 2.1, 4 times data rate interface 2.2, JTAG debugging interface 2.3, peripheral power supply module 2.4; internal integrated circuit bus programmable read-only memory circuit 3.1 and Flash programmable read-only memory circuit 3.2; queue scheduling module 4.1, receiving data buffer module 4.2, sending data buffer module 4.3, High-speed data link control protocol packet antisense and flag word processing module 4.4, frame check sequence module 4.5.

Detailed ways

The structure and flow of each module of the device of the present invention will be described in detail below in conjunction with the accompanying drawings.

The device of the invention is a multi-channel high-speed data processing device based on field programmable gate array.

The system framework of the present invention as shown in Figure 1 can know that this processor specifically comprises following four modules: field programmable gate array hardware module 1; 4 times of data rate interface module 2; Programmable read-only memory program configuration module 3 and Software system module 4; said 4 times data rate interface module 2 includes: internal integrated circuit bus interface 2.1, 4 times data rate interface 2.2, JTAG interface 2.3 and peripheral power supply module 2.4; field programmable gate array hardware module 1 passes 4 times The data rate interface 2.2 connects the external host computer, connects with the peripheral power supply module 2.4 through the power line and connects with the Flash programmable read-only memory circuit 3.2 in the programmable read-only memory program configuration module 3 through the JTAG interface 2.3, and the Flash programmable read-only memory The read memory circuit 3.2 is also connected with the external PC through the JTAG interface 2.3; the internal integrated circuit bus programmable read-only memory circuit 3.1 in the programmable read-only memory program configuration module 3 is connected to the external host computer through the internal integrated circuit bus interface 2.1 ; The software system module 4 includes: queue scheduling module 4.1, receiving data buffer module 4.2, sending data buffer module 4.3, high-speed data link control protocol data packet anti-sense and flag word processing module 4.4 and frame check sequence module 4.5, the modules included in the software system module 4 are connected together through signal transmission; the software system module 4 resides in the programmable read-only memory program configuration module 3, and after the multi-channel high-speed data processor works, the program is loaded into In the field programmable gate array hardware module 1, the field programmable gate array hardware module 1 is connected with the program of the host through the 4 times data rate interface module 2.

The processor of the present invention adopts 2 million Spartan3 XC3S2000 field programmable gate arrays. The processing speed of the field programmable gate array reaches 200Mbps, and the signal connection and timing matching process are completed by the standard internal integrated circuit between the access interface part and the host computer; the digital control impedance matching (DCI) technology is used to realize it inside the field programmable gate array I/O signal lines are shorted; 2M system gate structure, 320K distributed RAM, 720K Block RAM, 40 dedicated multipliers, and 4 sets of digital clock management structures (DCM) can provide 4 different clock signals to the outside world. Up to 565 user I/Os up to 270 pairs of differential signal pairs, supporting 18 single-row I/O standards and 8 differential I/O standards. In the design of this system, the LA 14 times data rate interface module 2 is used to connect the host and the device of the present invention to provide communication and data interaction between the device of the present invention and the host. Furthermore, all power supply for the device of the invention is provided by this interface. The internal integrated circuit bus interface 2.1 accesses the I2C E2PROM on the card through the internal integrated circuit bus to obtain equipment information such as the identifier, operating level and temperature of the equipment of the present invention, thereby identifying the equipment of the present invention. The 16-bit data interface of the 4-times data rate interface 2.2 is multiplied into a logic 32-bit under the dual clock drive. It uses the LA_1 protocol, and there is a large space for selection and customization in actual use; the JTAG debugging interface 2.3 is limited to providing test interfaces ( does not support the programming of programmable read-only memory and field programmable gate array), so a JTAG slot is introduced in the design, and the program is directly downloaded to the programmable read-only memory through a PC; the peripheral power supply module 2.4 is generated in 2.5 When V voltage is used, we use TI’s TPS75525 voltage conversion chip, 5Pin TO-263 (KTT) package; when generating 1.2v voltage, we use TI’s TPS54312 voltage conversion chip, 20Pin PWP package; when generating 0.75V voltage , we use MAX1589EZTAFJ, TDFN package; use the internal integrated circuit bus programmable read-only memory circuit 3.1 to record the device information of the present invention, including parameters such as device identifier, working level and temperature. In addition, the internal integrated circuit bus programmable read-only memory circuit 3.1 itself also supports password encryption and password protection; the Flash programmable read-only memory circuit 3.2 is used to automatically configure the field programmable gate array when powered on, and has master control mode and There are two kinds of controlled modes.

The external devices associated with the device of the present invention mainly include a host computer and a PC. The device of the present invention is connected to the host computer through a 114-pin socket, and the interface signal follows the LA_1 protocol. In addition, the power supply of the device of the present invention is also introduced through the socket. The connection with the external computer is mainly through the JTAG interface, through which the field programmable gate array and the programmable read-only memory are debugged and programmed. In access to the FPGA, JTAG mode has the highest priority.

The hardware reset and software reset ports for field programmable gate arrays are also designed on our invention equipment. The hardware reset clears the memory in the configuration storage area by setting the PROG_B pin of the field programmable gate array, and then it can be restarted through JTAG mode. Programmable or programmable ROM reconfiguration. The software reset port is mainly used for program reset and debugging, and its function can be defined by the user.

The working clock of the field programmable gate array is provided by the 40MHz onboard crystal oscillator, and the 200Mhz 4 times data rate interface clock provided by the 114 slot can also be used. The above two kinds of clocks are introduced by the global clock port, and pass through the field programmable gate array. The digital clock management structure module performs frequency division and multiplication to generate a system clock.

Each module is described below.

1. Field programmable gate array hardware module 1

(1) Configuration mode of field programmable gate array hardware module 1

The Spartan field programmable gate array we use is compatible with multiple configuration modes, and the selection of each configuration mode is realized by setting the high and low levels of the mode pins by the DIP switch. The pin level configuration corresponding to different modes is shown in Table 1 below:

configuration mode M0 M1 M2 synchronous clock data width serial output Master serial mode 0 0 0 CCLK output 1 yes Controlled serial mode 1 1 1 CCLK input 1 yes Master Parallel Mode 1 1 0 CCLK output 8 no Controlled Parallel Mode 0 1 1 CCLK input 8 no JTAG mode 1 0 1 TCK input 1 no

Table 1: MODE pin configuration corresponding to each mode

Note: The JTAG mode is not restricted by the mode selection and is always available. The selection mode is assigned to it only to prevent conflicts with other configuration methods during the configuration process.

System Resources of Field Programmable Gate Array Hardware Module 1

In the single board design, we use the Spartan3XC3S2000 field programmable gate of Xilinx Company

Array, its main hardware parameters are as follows:

2M system door structure;

320K distributed RAM, 720K Block RAM;

40 dedicated multipliers;

4 sets of digital clock management structures, which can provide 4 different clock signals to the outside world;

Up to 565 user I/O;

Up to 270 pairs of differential signal pairs;

Support 18 single row I/O standards and 8 differential I/O standards.

The I/O of the field programmable gate array is divided into 8 Banks, and the I/O output power supply of each Bank is relatively independent. In principle, it can support 8 different I/O standards at the same time.

(2) Description of power supply for Field Programmable Gate Array hardware module 1

The power supply of the FPGA is mainly divided into the following parts: FPGA core power supply V _ccint ; FPGA auxiliary power supply V _ccaux output drive level V _cco ; input reference level V _ref .

Among them, some voltages such as Vccint and Vccaux are relatively fixed, and other voltages vary with the I/O standard adopted by the corresponding Bank. When powering on, each level must meet the corresponding requirements. In this design, since Bank1 to Bank3 adopt the HSTL_I standard consistent with the 4x data rate interface, 1.5Vcco and 0.75V Vref must be used in these Banks.

In this design, since Bank1 to Bank3 adopt the HSTL_I standard consistent with the 4x data rate interface, 1.5Vcco and 0.75V Vref must be used in these Banks. The detailed level configuration is shown in the table below:

Input voltage Bank1/Bank2/Bank3 Bank0/Bank4～Bank7 Vccint 1.2V 1.2V Vccaux 2.5V 2.5V Vcco 1.5V 2.5V Vref 0.75V

Table 2: List of Field Programmable Gate Array Input Levels

The digital control impedance matching technology is the I/O signal line termination implemented inside the field programmable gate array. There are often different implementation methods for different I/O standards, mainly through the VRN and The VRP pin provides a pull-up or pull-down reference resistor, and the field programmable gate array provides digitally controlled impedance matching to each I/O pin according to the corresponding termination mode of each Bank and the provided characteristic impedance value.

In this design, the digital control impedance matching is mainly configured for the HSTL_I standard. The HSTL_I standard does not start the termination when it is used as a signal output, but enables the termination when it is used as a signal input, and it is a double-terminated form that includes pull-up and pull-down reference resistors. .

The circuit of field programmable gate array hardware module 1 also includes DC 1.2V power supply for field programmable gate array module, 2.5V peripheral power supply and 0.75V reference voltage three peripheral DC voltage conversion circuits, 40MHz global clock signal generating unit and re- Set several peripheral circuits such as switching circuits. Among them, the 40MHz crystal oscillator provides the global clock for the field programmable gate array, and the frequency conversion can be realized through the internal digital clock management structure module of the field programmable gate array. In the FPGA controlled mode, a configuration clock signal is provided for the programmable read-only memory. The inter-integrated circuit programmable read-only memory communicates with the 4x data rate interface through the inter-integrated circuit, and the host computer obtains the device parameters.

2. 4x data rate interface module 2

The 4x data rate interface module 2 is the logic interface between the field programmable gate array and the host. The field programmable gate array hardware module 1 mainly performs parallel high-speed data link control on the multi-channel high-speed data link control protocol frames from the host. Protocol decapsulation and end-to-end protocol package anti-sense, and finally the results are fed back to the host for the next step of reassembly and protocol processing.

(1) Overview of interface operations

The 4X data rate interface module 2 follows the following principles:

控制信号总是在K时钟上升沿锁存；

The control signal is always latched on the rising edge of the K clock;

地址和数据信号在K时钟的上升、下降沿读取；

The address and data signals are read on the rising and falling edges of the K clock;

进程中的读写数据操作均不能被中断或者重新开始。

The read and write data operations in the process cannot be interrupted or restarted.

(2) Data transmission structure and operation timing of 4x data rate interface module 2

Data writing structure: The word writing signal has two control signals, BW1# and BW0#, which respectively control the upper 8 bits (D[15:8]) and lower 8 bits (D[7:0]) of the data input pins , and the corresponding parity bits are DP1 and DP0. A write cycle starts when W# is low when a rising edge of K is detected. The address for the write cycle is provided by A on the subsequent rising edge of K#. In the same cycle, write data is obtained on the rising edge of K and K#. The specific data write timing is: on the rising edge of K, the upper 8 bits (D[15:8]) controlled by BW1 are written into byte 0Bits[31:24], and the lower 8 bits (D[7:0] controlled by BW0 ]) write byte 1Bits[23:16]; on the rising edge of K#, the upper 8 bits (D[15:8]) controlled by BW1 are written into byte 2Bits[15:8], and the lower 8 bits controlled by BW0 Bits (D[7:0]) are written to Byte 0 Bits[7:0].

Data output structure: The data output structure corresponds to the data write structure, and a read cycle starts when R# is low when the rising edge of K is detected. At the same time, the address for the read operation is read in on A. Data is output with C and C# as the reference clock after the next K rising edge.

(3) Output register control (slave device properties)

The 4x data rate interface block 2 provides two mechanisms for registering output data. Generally, the control beat is provided by a pair of differential input clocks C and C#, which allow the user's data output to be delayed by a few nanoseconds based on the subsequent K and K# clock signals through a small phase offset. This enables the device to work in a manner similar to a traditional pipelined read device. Burst1 and Burst2 based on the byte write control signal are optional modes; Echo Clock signals CQ and CQ# provided to the host during the read operation; generate an output check digit.

(4) LA_1 protocol application of the present invention

The LA_1 protocol provides a reference solution for the application of the 4x data rate interface, and there is a large space for selection and customization in actual application. In the design of the slave device of the present invention, due to the relative independence of memory scheduling, the address signal only plays the role of a chip selection device, and there is no one-to-one mapping with the actual memory space. However, based on the versatility of the device, the design of the interface program must also include:

●Burst1 and Burst2 optional modes based on byte write control signal

●The Echo Clock signal CQ, CQ# provided to the host in the read operation

●Generate output check digit

(5) Detailed design of interface power supply module

The main power supply of the device comes from the three-way DC power supply provided by the Mictor 114 socket, and the voltage values are: 3.3V, 1.5V, and 1.8V. In addition, in order to drive the Spartan Field Programmable Gate Array and provide HSTL_I reference levels for 1 to 3 Banks, the voltage control chip must be used to locally generate 1.2V, 2.5V, and 0.75V levels on the card. Among them, 1.2V is the power supply for the FPGA core, 2.5V is the auxiliary power supply for the FPGA and 4 to 7 Bank and 0 Bank I/O power supply, and 0.75 V is the reference level for 1 to 3 Bank. When generating local levels, 3.3V generates 1.2V and 2.5V, and 1.8V generates 0.75V.

When the TPS75525 3.3/2.5V voltage conversion chip generates 2.5V voltage, we use TI's TPS75525 voltage conversion chip, 5Pin TO-263 (KTT) package. Among them, pin 1 (EN) is input enable, pin 2 (IN) is input level, pin 3 (GND) is ground, pin 4 (OUTPUT) is output level, pin 5 (FB/PG ) is input feedback/PG output in specific mode.

When the TPS543123.3/1.2V voltage conversion chip generates 1.2V voltage, we use TI's TPS54312 voltage conversion chip, 20Pin PWP package. Among them, pin 1 (AGND) is analog ground, pin 5 (BOOT) is reserved, pin 19 (FSEL) is frequency input selection, pin 3 (NC) is not connected; pins 11-13 (PGND) are power ground, Pin 6-10 (PH) is phase input/output, pin 4 (PWRGD) is Power Good indication, pin 20 (RT) frequency setting resistor input, pin 18 (SS/ENA) slow start/input enable /Output multiplexing pin, pin 17 (VBIAS) internal bias output control, pin 14-16 (VIN) input level, pin (VSENSE) error feedback amplifier input.

The MAX1589 1.8/0.75V voltage conversion chip is driven by the 1.8V power supply provided by the Mictor 114 socket, and outputs a 0.75V HSTL_I reference level. The complete chip part number is MAX1589EZTAFJ, and it adopts a standard TDFN package. Among them, pin 6 (IN) is the power input, pin 4 (GND) is the ground, pin 5 (SHDN) is used for shutdown signal, low level is active, pin 3 (RESET) is restart signal, low level is active , pin 2 (I.C.) is an internal connection, empty or grounded, pin 1 (OUT) is a voltage output, and the middle pad EP is ground.

3. Programmable read-only memory program configuration module 3

The Flash programmable read-only memory circuit 3.2 automatically has two configuration modes for the field programmable gate array when it is powered on: the master control mode and the controlled mode, the main difference of which is the configuration clock signal source. In the field programmable gate array master control mode, the field programmable gate array provides a configuration clock signal for the programmable read-only memory, and in the field programmable gate array controlled mode, an external crystal oscillator provides a configuration clock signal. In the design, the master-slave mode can be switched by adjusting the field programmable gate array configuration mode selection switch. The default mode is the field programmable gate array master control mode. We adjust the programmable read-only memory configuration rate by setting the rate configuration option in the Xilinx BitGen software. FIG. 3 is a connection diagram of the FPGA hardware module 1 and the Flash programmable read-only memory module 3.2 under the FPGA master control mode.

The field programmable gate array receives configuration information through the serial interface with the FLASH programmable read-only memory. In addition, the field programmable gate array can be directly configured and DEBUG through the JTAG interface. After power-on, the field programmable gate array reads data from the programmable read-only memory by itself, and can also be reconfigured through the reset signal in the working state.

Figure 4 is a configuration flowchart of the programmable read-only memory program configuration module 3. First, the system is powered on. If the power supply meets the power supply conditions, that is, Vccin>1V, Vccaux>2V, and VccoBank4>1V, the three conditions are met at the same time, and the configuration storage is cleared. area memory, and then judge whether the pin INT_B is high level, if it is high level, automatically detect the configuration mode pin, and then download the configuration information according to the corresponding mode, if the CRC check is correct, then the configuration is complete and enter the user mode . If the field programmable gate array needs to be reconfigured in user mode, set the PROG_B pin level low. If during the configuration process, it is detected that the PROG_B pin is at a low level, clear the memory in the configuration storage area and enter a new configuration process; CRC check, check configuration information.

4, the software module 4 of the present invention

Figure 5 is a connection diagram between software modules. Each module transmits information through signals: first, the network processor sends out read and write information and data information, the queue scheduling module 4.1 obtains the read, write and data information from the network processor, and the receiving module 4.2 obtains the corresponding write command from the queue scheduling module 4.1 Afterwards, the corresponding write operation is carried out to the buffer zone, in order to facilitate the processing of high-speed data link control protocol packet anti-escaping and flag word processing modulo 4.4, the processed control signal effective frame signal, escape signal and its processor The output data is sent to the frame verification sequence module 4.5 together, and the control signal write buffer signal, the frame end signal, the verification error signal and the data after verification are generated after verification, and then transferred to the sending data buffer module 4.3, and the data is processed and judged comprehensively. Write into the buffer, combined with the read information of the queue scheduling module 4.1, output the processed data through the read operation of the buffer.

In the software system module 4, firstly, the network processor sends out read and write information and data information, the queue scheduling module 4.1 obtains the read and write and data information from the network processor, and after the receiving module 4.2 obtains the corresponding write command from the queue scheduling module 4.1, Perform corresponding write operations on the buffer to facilitate the processing of high-speed data link control protocol data packet anti-sense and flag word processing module 4.4, the processed control signal valid frame signal, escape signal and its processor output data It is also transmitted to the frame verification sequence module 4.5, and after verification, a control signal write buffer signal, a frame end signal, a verification error signal and the data after verification are generated, and they are transferred to the sending data buffer module 4.3, and the data is written after comprehensive processing and judgment The buffer, combined with the read information of the queue scheduling module 4.1, outputs the processed data through the read operation of the buffer. The software system module 4 performs frame header search, cyclic redundancy check, antisense, discard sequence detection, frame length monitoring and frame tail search on the data of each channel. When the number of information bits reaches the maximum frame length or a discard sequence is detected, the processing of the current frame by the state machine ends, and a new frame header search is performed again, while the remaining data in the current frame will not be processed. The software system module 4 simultaneously processes high-speed data link control protocol data streams of up to 128 channels in parallel transmission, and its realization adopts the method of time division multiplexing, wherein the channel state memory is the key to realize time division multiplexing, and each channel is in the channel There is a fixed storage space in the state memory, which is used to store the data processing status of the channel, that is, the channel state information. A time slice of a certain length is allocated to each piece of data to be processed for each channel. Each time slice At the end, the latest state information of the current channel will be stored in the corresponding storage space in the channel state memory. When a new piece of data arrives, the state information of the channel to which this piece of data belongs has been refreshed in the previous time slice. Read from the state memory and load it into the state machine to prepare for a new round of data processing.

Figure 6 is a transition diagram of the software design state of this design. The present invention can simultaneously process high-speed data link control protocol data streams transmitted in parallel up to 128 channels. Its realization adopts the method of time division multiplexing, and the core part is processed by a high-speed data link control protocol that is independent in sending and receiving and can be processed in time division. device and a channel state memory. The channel state memory is the key to realize time division multiplexing, and each channel has a fixed storage space in the channel state memory to store the data processing status of the channel, that is, the channel state information. The present invention allocates a certain length of time slice for each piece of data to be processed in each channel. At the end of each time slice, the latest state information of the current channel (including: the state of the state machine at the end of the processing, the CRC check code of the data processed by the channel and the length of the unresidual data, the current time Received data that has been processed in the chip but has not yet been output, etc.) will be stored in the corresponding storage space in the channel state memory. When a new piece of data arrives, the status information of the channel to which this piece of data belongs was refreshed in the previous time slice will be read from the channel state memory and loaded into the state machine to prepare for a new round of data processing.

In order to realize the monitoring function of the data transmission of each channel by the host, in the design, a branch state is added in the idle state. The data can and can only be queried in the waiting idle state of the multi-channel for the status information of the channel, so as to ensure that the normal operation of the other channel data is not interrupted.

We use the "Top to Down" ("top to bottom") method when designing the functions of field programmable gate array devices, that is, we first design the top-level functional block diagram according to the required functions, which usually consists of several It consists of functional modules. Each module is then subdivided into sub-modules. For more complex designs, each sub-module can be divided into layers of sub-modules. The functions of each layer can be realized by hardware description language or circuit diagram.

FIG. 7 is a state transition diagram of a single-channel high-speed data processor. Perform frame header search, CRC check, antisense, discard sequence detection, frame length monitoring and frame tail search on the data of each channel. Once it is detected that the number of information bits currently transmitted in a certain frame reaches the maximum frame length or the discarding sequence is detected, the state machine ends the processing of the current frame, and searches for the frame header of a new frame again, while the remaining frames in the current frame The data will not be processed.

S1: Default state, search frame header;

S2: data processing, including anti-sense, CRC check, and detection of discarded sequences;

S3: Judging the CRC check code and the frame length, and marking the status bit.

The state machine is in the default state S1 when it starts to work, and searches for the frame header. Combined with the data stored in the state register, after the shift, the state machine thinks that the frame header has been searched after it is judged as (7E) by the logical relationship, and immediately jumps into the state S2 to process the data, including antisense and discarding sequence detection. If the state machine detects the discard sequence, the remaining data of the current frame of the channel will be discarded, that is, it will neither be processed nor sent into the FIFO, and the state will be directly changed from S2 to S1, and the frame header search of a new frame will be performed. Also gives error status. In state S2, if the frame end of the current frame or the frame head of the next frame is found, jump into state S3, first judge the CRC check code and the final frame length, and give various error judgments accordingly. Because in this design, the frame tail of the previous frame is the frame header of the next frame, so there is no need to search for the frame header in S1, and directly jump into S2;. Since the calculation of the frame length is outside the sub-state machine (but still in the main state "processing"), it is carried out synchronously and independently with the processing of the data, so when the state machine is in state S2 and is processing data, once If it is found that the frame length exceeds the maximum allowable length, it will directly jump into S1 to search for the frame header of the next frame as if the discard sequence is detected, and at the same time give an error status that the frame length is too long, and the remaining data of the current frame will not be processed. After the state machine jumps into S3 from S2, it firstly makes various wrong judgments. When it is found that there are multiple errors in the received data frame at the same time, the state machine takes the frame check sequence error as the error state with the highest priority. In addition to the normal state (the received data is neither at the frame header nor at the frame end), most of the states are judged when the frame end is found (in the S3 state), and are output together with the received data. And the beginning of a high-speed data link control protocol frame can only be judged in S1. At this time, the shift register cannot have an output, so it is necessary to set a status flag in the channel state RAM. At the beginning, set it to 1, and when the shift register is full for the first time, output the status bit.

In order to realize the anti-sense function, when the state machine detects 0x7D, it will XOR output the next data with 0X20.

In order to realize multi-channel time division multiplexing in the state machine, the variable frame length is also used to control the processing time of a channel, that is, each time a bit of data is processed, the length is reduced by 1 until it is 0, thus completing the processing of the channel .

We use the method of multi-channel high-speed data link control protocol. When receiving, add the channel number to the front of the data (considering our specific design object, it is more reasonable for the channel number to use the KEY number), and each channel is equipped with a channel The status register records the last processing of the channel (that is, the corresponding KEY number) and the CRC check value, so that the next time the CRC check value can be calculated on this basis, thereby completing the check function.

The processed data sends a corresponding ready signal. According to the information obtained when writing the state: the package processed this time contains the number and length of the complete end-to-end protocol package, and the data is read out, while the remaining stubs are stored in the field programmable gate array, to be When data with the same KEY number is input next time, a complete end-to-end protocol packet is formed and then output.

It should be understood that those skilled in the art can make various possible changes or substitutions according to the preferred examples of the present invention and its technical concept, and all these changes or substitutions should belong to the appended claims of the present invention scope of protection.

Claims (8)

1, a kind of multi-channel high-speed data processor is characterized in that this processor specifically comprises four following modules: field programmable gate array hardware module (1); 4 haplotype data rate interface modules (2); Programmable read only memory application configuration module (3) and software system module (4); Described 4 haplotype data rate interface modules (2) comprising: internal integrate circuit bus interface (2.1), 4 haplotype data rate interfaces (2.2), jtag interface (2.3) and peripheral supply module (2.4); Field programmable gate array hardware module (1) connects external host, is connected with peripheral supply module (2.4) and joins by the Flash programmable read only memory circuit (3.2) in jtag interface (2.3) and the programmable read only memory application configuration module (3) by power line by 4 haplotype data rate interfaces (2.2), and Flash programmable read only memory circuit (3.2) also joins by the PC of jtag interface (2.3) and outside; Internal integrate circuit bus programmable read only memory circuit (3.1) in the programmable read only memory application configuration module (3) connects external host by internal integrate circuit bus interface (2.1); Software system module (4), comprised: queue scheduling module (4.1), reception data cache module (4.2), transmission data cache module (4.3), high speed data link control protocol packet counter-rotating justice and banner word processing module (4.4) and Frame Check Sequence module (4.5) link together by the signal transmission between each module that software system module (4) comprises; Software system module (4) resides in the programmable read only memory application configuration module (3), after the multi-channel high-speed data processor work, program is loaded in the field programmable gate array hardware module (1), and field programmable gate array hardware module (1) links together by the program of 4 haplotype data rate interface modules (2) with external host.

2, multi-channel high-speed data processor according to claim 1 is characterized in that field programmable gate array hardware module (1) adopts the coprocessor of 2,000,000 " XC3S2000 " field programmable gate arrays as external host.

3, multi-channel high-speed data processor according to claim 1 is characterized in that in the 4 haplotype data rate interface modules (2), and peripheral supply module (2.4) has adopted " TPS75525 " voltage transitions chip when generating 2.5V voltage; When generating 1.2v voltage, adopted " TPS54312 " voltage transitions chip; When generating 0.75V voltage, adopt " MAX1589EZTAFJ " chip.

4; multi-channel high-speed data processor according to claim 1; it is characterized in that in the programmable read only memory application configuration module (3); adopt the facility information of the described processor of internal integrate circuit bus programmable read only memory circuit (3.1) record; comprise device identifier; operation level and temperature parameter; external host detects with the identification multi-channel high-speed data processor by internal integrate circuit bus programmable read only memory circuit (3.1), and internal integrate circuit bus programmable read only memory circuit (3.1) itself is also supported password encryption and cryptoguard.

5, multi-channel high-speed data processor according to claim 1, it is characterized in that in the programmable read only memory application configuration module (3), adopt Flash programmable read only memory circuit (3.2) automatically field programmable gate array hardware module (1) to be configured when powering on, configuration mode has two kinds of master mode and controlled modes.

6, a kind of high-speed data processing method of multi-channel high-speed data processor as claimed in claim 1, it is characterized in that in the software system module (4), at first send reading writing information and data message by external host processor, queue scheduling module (4.1) is obtained reading writing information and data message from external host processor, after reception data cache module (4.2) is obtained corresponding write order from queue scheduling module (4.1), the buffering area that receives data cache module (4.2) is carried out corresponding write operation, so that the processing of high speed data link control protocol packet counter-rotating justice and banner word processing module (4.4) thereof, control signal valid frame signal after the processing, escape signal and external host processor dateout are imported Frame Check Sequence module (4.5) in the lump into, after verification, produce control signal and write buffering signals, the postamble signal, data after check errors signal and the verification, import into and send data cache module (4.3), send and after data cache module (4.3) integrated treatment is judged data after the verification are write the buffering area that sends data cache module (4.3), in conjunction with the read message of queue scheduling module (4.1), export by the data after will handling the read operation of the buffering area that sends data cache module (4.3).

7, the high-speed data processing method of multi-channel high-speed data processor according to claim 6, it is characterized in that software system module (4) carries out the frame head search to the data of each passage, CRC, counter-rotating justice, abandon the detection of sequence, the monitoring of frame length and the search of postamble, in case detecting the current information transmitted figure place of a certain frame reaches maximum frame length or detects when abandoning sequence, state machine in the software system module (4) finishes the processing of present frame, and again a new frame is carried out the frame head search, and the remaining data in the present frame will be not processed.

8, the high-speed data processing method of multi-channel high-speed data processor according to claim 6, it is characterized in that software system module (4) handles the high speed data link control protocol data flow up to 128 channel parallels transmission simultaneously, its realization is to adopt time-multiplexed mode, wherein the channel status memory is used to realize time division multiplexing, each passage all has a fixing memory space among this channel status memory, in order to store the processing condition data of this passage, it is channel status information, be processed one segment length regular hour of the data allocations sheet of each each section of passage needs, when each timeslice finishes, when the up-to-date state information of prepass will be deposited in respective stored space in the channel status memory, when new one piece of data arrives, the state information that passage under this segment data is refreshed in a last timeslice will be read and be loaded into from the channel status memory in the state machine, for the data processing of a new round is prepared.

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