CN100431255C - Main circuit topology and control method of three-level double-buck half-bridge inverter - Google Patents

Abstract

The main circuit topology of a three-level double-buck half-bridge inverter is an inverter, which consists of two power switches (S ₁ ) and (S ₂ ) of the power supply (U _d1 ) and filter inductor (L ₁ ) and filter Capacitor (Cf), freewheeling diodes (D ₁ ), ( _{D 2} ) form a step-down circuit modulation filter output circuit; two power switch tubes (S ₃ ) and (S ₄ ) and Filter inductor (L ₂ ), filter capacitor (Cf), freewheeling diodes (D ₃ ), (D ₄ ) form another step-down circuit modulation filter output circuit. The voltage stress of each power tube in the main circuit is only twice the output voltage, and the three-state voltage waveform can be output on the bridge arm. Low-voltage and high-frequency power tubes can be used to increase the switching frequency, reduce the size and weight, and achieve dynamic The response performance is fast; a non-bias current half-cycle motion mode that enables the three-level double-buck half-bridge inverter to obtain optimal operating efficiency and can realize the unbiased three-level double-buck half-bridge inverter A three-state hysteresis current control method with current half-cycle operation mode.

Description

Main circuit topology and control method of three-level double-buck half-bridge inverter

Technical field:

The invention relates to a main circuit topology of a three-level double-buck half-bridge inverter and a control method thereof.

Background technique:

With the development of high-frequency power devices, the switching frequency of inverters has been greatly increased, and the development of AC power sources such as aviation power supplies, UPS systems, and high-performance motor drives has put forward higher requirements for the performance of inverters. How to achieve high frequency inverter while ensuring high efficiency is the key issue of current research. Soft switching technology can effectively reduce the switching loss of the converter. In the past ten years, domestic and foreign scholars have done a lot of research on the soft switching problem of inverters, and have obtained many valuable research results. There are mainly polar resonant inverters, resonant DC high frequency link inverters, resonant buffer network inverters and so on. These soft-switching techniques have been successfully applied in some specific occasions, but a simple and efficient method has not been obtained. N.R.Zargari proposed a highly reliable inverter circuit - double step-down inverter circuit. It is composed of two step-down circuits, which overcomes the direct problem of the traditional bridge-type inverter bridge and reduces switching loss, especially suitable for applications with high reliability requirements such as aerospace and UPS. But at present, these circuits are only used in high-voltage and high-power occasions, and high-voltage devices such as IGBTs must be used, and the performance of high-frequency is limited. The double step-down half-bridge inverter is composed of two active tubes, the modulation waveform level of the bridge arm is two levels, and the power tube has no direct problem, but the voltage stress of each power tube in this circuit is twice Output voltage; the full-bridge inverter has four active tubes, the modulation waveform level of the bridge arm is three-level, and the voltage stress of each power tube is double the output voltage, but the power tube has a straight-through problem.

Invention content:

The present invention aims at proposing a three-level dual buck half bridge inverter (Three level dual buck half bridge inverter-TLDBI) main circuit topology on the basis of a double buck inverter circuit, and proposes a three-level Nonbiased half cycle mode (NBHCM) mode of double-buck half-bridge inverter and three-state hysteresis control scheme of NBHCM. In order to greatly improve circuit performance, increase efficiency, and improve output waveform quality. It provides a simple method for the inverter to achieve high frequency, high voltage and high power operation, and has a very wide application prospect in the inverter.

In order to achieve the above object, the technical solution of the present invention is that the first power supply and the second power supply are connected in series to form a power supply circuit, and the series point is connected to "ground". In a flat step-down circuit, the positive pole of the first power supply is connected to the anode of the first power switch tube, the cathode of the first power switch tube is connected in series with the anode of the second power switch tube, and the cathode of the second power switch tube is connected to the input terminal of the first filter inductor , the output end of which is connected to the positive pole of the filter capacitor, the negative pole of the filter capacitor is connected to the negative pole of the first power supply through the "ground" line, the positive pole of the first freewheeling diode is connected to the negative pole of the first power supply, and the negative pole is connected to the first power switch tube in the first The series connection point of the two power switch tubes, the negative pole of the second freewheeling diode is connected to the cathode of the second power switch tube, and the positive pole is connected to the negative pole of the second power supply; when the inverter filter inductor outputs negative current In a flat step-down circuit, the negative pole of the second power supply is connected to the cathode of the third power switch tube, the anode of the third power switch tube is connected in series with the cathode of the fourth power switch tube, and the anode of the fourth power switch tube is connected to one end of the second filter inductor, The other end is connected to the anode of the second power supply through the filter capacitor through the "ground" line, the anode of the third freewheeling diode is connected to the series connection point of the third power switch tube and the fourth power switch tube, and the cathode of the third freewheeling diode is connected to "Ground", the anode of the fourth freewheeling diode is connected to the anode of the fourth power switch tube, and the cathode is connected to the anode of the first power supply.

The main circuit topology of the three-level double-buck half-bridge inverter of the present invention has four power switch tubes, and the voltage stress of each power switch tube is only twice the output voltage; and the bridge arm can provide a tri-state voltage ; At the same time, it also maintains the advantages of no direct connection and optimal design of the power tube of the double-buck half-bridge inverter. Three-state hysteretic current control scheme for half-cycle operation with no bias current in a level dual-buck half-bridge inverter. Therefore, the present invention realizes high frequency and high power, broadens the scope of application, and has broad application prospects.

Description of drawings

Figure 1 is a schematic diagram of the main circuit topology of the three-level double-buck half-bridge inverter.

Fig. 2 is a three-state operation waveform diagram of a three-level double-buck half-bridge inverter in a half-cycle operation mode without bias current.

FIG. 3 is an equivalent circuit corresponding to each switch state when the first filter inductor current is greater than zero (i _L1 >0) and the second filter inductor current (i _L2 =0).

Fig. 4 is an equivalent circuit corresponding to each switch state when the current of the first filter inductor is equal to zero (i _L1 =0) and the current of the second filter inductor is greater than zero (i _L2 >0).

Symbol names in Figure 1 to Figure 4: U _d1 , U _d2 - power supply, S ₁ , S ₂ , S ₃ , S ₄ - respectively the first to fourth power switch tubes, D ₁ , D ₂ , D ₃ , D ₄ -respectively for the 1st to 4th freewheeling diodes, L ₁ and L ₂ -for the first and second filter inductors, Cf-filter capacitance, C ₁ , C ₂ -capacitors, U _o -output voltage, i _L1 , i _L2 - respectively the first and second filter inductor currents, i _o - the output current, U _A , U _B - the voltages of the two bridge arms respectively, M ₁ —M ₆ - the switching modes of the 1st to 6th groups, Others are known symbols. A, B, C, D-represent the four working areas of the inverter: A is the feedback energy area (u _o <0, i _o >0), B is the output energy area (u _o >0, i _o > 0), C is the feedback energy area (u _o >0, i _o <0), and D is the output energy area (u _o <0, i _o <0).

Fig. 5 is a control block diagram of the three-state operation in the non-bias current half-cycle operation mode of the three-level double-buck half-bridge inverter.

Fig. 6 is a tri-state operation logic diagram of the non-bias current half-cycle operation mode of the three-level double-buck half-bridge inverter.

Fig. 7 is a three-state operation waveform diagram of the non-bias current half-cycle operation mode of the three-level double-buck half-bridge inverter.

Symbolic names of Figures 5 to 7: i _g - current reference signal, i _e - current error signal, ±h ₁ - hysteresis control inner loop reference, ±h ₂ - hysteresis control outer loop reference, AD - four areas , other symbols and names are consistent with those shown in Figure 1 to Figure 4.

Detailed ways:

Figure 1 is a schematic diagram of the main circuit topology of the three-level double-buck half-bridge inverter. The composition of the circuit is that when the inverter filters the inductance to output the forward current, the positive pole of the first power supply U _d1 is sequentially connected to the In the first three-level step-down circuit, two first power switch tubes S ₁ connected in series, the second power switch tube S ₂ , the first filter inductor L ₁ and filter capacitor Cf, the negative electrode of the filter capacitor Cf passes through The ground wire is connected to the negative pole of the first power supply U _d1 , the freewheeling diode _D1 is forwardly connected between the negative pole of the first power supply _Ud1 and the cathode of the first power switch _S1 , and the freewheeling diode _D2 is connected in reverse to the second Between the cathode of the power switch tube S ₂ and the negative pole of the second power supply U _d2 , the first three-level step-down circuit modulation filter output is formed; when the inverter filter inductor outputs negative current, the second power supply U The negative pole _{of d2} is sequentially connected to two third power switch tubes S ₃ , the fourth power switch tube S ₄ , the second filter inductor L ₂ and filter capacitor Cf of the second three-level step-down circuit in sequence. The negative pole of the filter capacitor Cf is connected to the positive pole of the second power supply U _d2 through the ground wire, the freewheeling diode _D3 is forwardly connected between the anode of the third power switch tube _S3 and the negative pole of the filter capacitor Cf, and the freewheeling diode _D4 is connected in reverse to the negative pole of the filter capacitor Cf Between the anode of the fourth power switch tube _S4 and the anode of the first power supply _Ud1 , a second three-level step-down circuit is formed to modulate and filter the output. Since the first power source Ud1 and the second power source Ud2 are equal, they are collectively referred to as “Ud” below and in the accompanying drawings 2, 3, 4, and 7.

Working principle and working process:

Operational characteristics of a three-level double-buck half-bridge inverter.

The three-level double-buck half-bridge inverter TLDBI can actually be regarded as a three-level power switch instead of the switch in the double-buck half-bridge inverter, so its operating characteristics are basically It is the same as the double-buck half-bridge inverter. It is also divided into biased current mode (Biased continuous current mode-BCCM) and non-biased current half cycle mode (Non-biased half cycle mode——NBHCM); NBHCM mode also has Discontinuous conduction mote-DCM area . The invention focuses on analyzing and proposing a method for realizing the three-state operation mode of the TLDBI under the NBHCM mode.

1. Three-state operation in the non-bias current half-cycle operation mode (TLDBINBHCM) of the three-level double-buck half-bridge inverter

The bridge arm of TLDBI can output a tri-state voltage waveform, so it also has two operating modes: bipolar and unipolar. We want the inverter to operate in tri-state mode and output a unipolar voltage waveform. The TLDBI of the present invention uses hysteresis current control, and the operation mode adopts the non-bias current half-cycle operation mode. The ideal waveform diagram of the three-state operation under its NBHCM mode is shown in Figure 2, which are respectively the inductor current i _L1 and i _L2 , and the bridge Arm voltage u _A and u _B , output voltage u _o , and output current i _o waveforms. In the half cycle when the power tube of the bridge arm is not working, under the action of the conductor of the corresponding filter inductor, the voltage of the bridge arm is the output voltage, but no output current is provided.

2. The working mode of the three-level double-buck half-bridge inverter under the half-cycle operation mode without bias current

When NBHCM TLDBI works in Continuous conduction mode (CCM), the switching states of the power tubes can be combined as shown in Table 1, "1" means on, and "0" means off. According to the half cycle of the inductor current, that is, in the positive half cycle of the output current, the power switches S ₁ and S ₂ work, the power switches S ₃ and S ₄ do not work, and the filter inductor current i _L1 >0, i _L2 = 0; in the negative half cycle of the output current i _o , the power switches S1 and S2 do not work, the power switches S3 and S4 work, the filter inductor current i _L1 =0, i _L2 >0. As shown in Fig. 3 and Fig. 4, there are 6 groups of switching modes M ₁ ~ M ₆ , where (S ₁ , S ₂ , S ₃ , S ₄ ) represent the switching states of power switches S ₁ ~ S ₄ in a mode, "1" means on, and "0" means off.

Combined with Table 1, it is described in detail as follows: the first bridge arm voltage UA output voltage +Ud of the "+1 state" of the three-level double-buck half-bridge inverter in the non-bias current half-cycle operation mode when the current is continuous ", the second bridge arm voltage UB outputs a negative voltage -Ud in the "-1 state" and the first bridge arm voltage UA and the second bridge arm voltage UB both output a "0 state" of 0, referred to as "+1 state", The three working states of "-1 state" and "0 state" are realized by using two groups of switch modes M1, M2, M3 and M4, M5, M6 respectively, and the switch mode groups M1, M2, M3 realize the inverter The positive half-cycle current output of the inverter, the switch mode group M4, M5, M6 realizes the negative half-cycle current output of the inverter. When the switch mode M1 is selected, the first power switch S1 is turned off, and the second power switch S2 is turned on. The third and fourth power switch tubes S3 and S4 are both turned off, the current of the first filter inductor L1 continues to flow through the first freewheeling diode D1, and still supplies power to the load, and the output of the first bridge arm voltage UA is 0, that is, the "0 state"; when switching mode M2 is selected, the four power switch tubes S1, S2, S3, and S4 of the first, second, third, and fourth are all turned off, and the current of the first filter inductor L1 passes through the second freewheeling diode D2 freewheeling, feedback energy to the power supply, the voltage UA of the first bridge arm is equal to the negative output voltage -Ud, that is, the "-1 state" is realized; when the switch mode M3 is selected, the first and second power switch tubes S1, S2 is turned on, the third and fourth power switch tubes S3 and S4 are turned off, the current of the first filter inductor L1 supplies power to the load through the first power switch tube S1 and the second power switch tube S2, and the first bridge arm voltage UA Equal to the positive output voltage + Ud, that is, to achieve "+1 state"; when the switching mode M4 is selected, the first, second, and third power switch tubes S1, S2, and S3 are turned off, and the fourth power switch tube S4 is turned on , the output of the voltage UB of the second bridge arm is 0, that is, "0 state" is realized; when the switching mode M5 is selected, the four power switch tubes S1, S2, S3, and S4 of the first, second, third, and fourth are all turned off, The current of the second filter inductor L2 continues to flow through the fourth freewheeling diode D4 to feed back energy to the power supply. The voltage UB of the second bridge arm is equal to the positive output voltage +Ud, that is, the "+1 state" is realized; when the switching mode M6 is selected, The first and second power switches S1 and S2 are turned off, the third and fourth power switches S3 and S4 are turned on, and the current of the second filter inductor L2 passes through the third and fourth power switches S3 , S4 supplies power to the load, and the voltage UB of the second bridge arm is equal to the negative output voltage -Ud, that is, the "-1 state" is realized.

Table 1 Switching state of power tube when TLDBI works in CCM under NBHCM

3. Control strategy of three-level double-buck half-bridge inverter

(1) The realization goal of the three-state operation of the three-level double-buck half-inverter (NBHCM TLDBI) with no bias current half-cycle operation mode

As mentioned above, the three-level double-buck half-bridge inverter of the present invention applies hysteresis current control, and the operation mode adopts a half-cycle operation mode without bias current. How to realize the three-state operation control of the NBHCM mode of TLDBI is the problem solved by the present invention. Firstly, the realization goal of the control is given.

From the analysis in the previous section, it can be seen that the +1 state, -1 state and 0 state of TLDBI when working in CCM under NBHCM include two groups of switch mode groups and (modules) respectively. During the positive and negative half cycles of the output current i _o The corresponding ±1 state and 0 state are respectively realized by three groups of switching modes, which is a characteristic of TLDBI different from the three-state control of traditional bridge inverters. That is, in the positive half cycle of the output current i _o , select the modules (M ₁ , M ₂ , M ₃ ) to realize the 0 state, -1 state and +1 state; in the negative half cycle of the output current i _o , Modules (M ₄ , M ₅ , M ₆ ) are selected to achieve the 0, +1 and -1 states. Table 2 is the switching mode allocation table for realizing three-state operation in the four output and feedback energy areas of A~B of the inverter, and the description is as follows:

Feedback energy area A: u _o <0, i _o >0, use M ₁ and M ₂ to realize 0 state and -1 state respectively. At this time, i _L1 >0, i _L2 =0. In state 0, i _L1 increases under the action of -u _o ; in state -1, i _L1 decreases under the action of (-U _d -u _o ).

Output energy area B: u _o >0, i _o >0, use M ₃ and M ₁ to achieve +1 state and 0 state respectively; at this time, i _L1 >0, i _L2 =0, in +1 state, i _L1 is in (U _d -u _o ) increases; in 0 state, i _L1 decreases under the action of -u _o .

Feedback energy area C: u _o >0, i _o <0, use M ₄ and M ₅ to achieve 0 state and +1 state respectively; at this time, i _L1 = 0, i _L2 >0, when in 0 state, i _L2 is in u _o increases; in +1 state, i _L1 decreases under the action of (u _o -U _d ).

Output energy D area: u _o <0, i _o <0, use M ₆ and M ₄ to realize -1 state and 0 state respectively; at this time, i _L2 = 0, i _L2 > 0, in -1 state, i _L2 is in (u _o +U _d ) rises under the action; in 0 state, i _L2 falls under the action of u _o .

Table 2 Switch mode allocation table in 4 partitions

(2) The three-state operation control scheme of the three-level double-buck half-bridge inverter (NBHCMTLDBI) with no bias current half-cycle operation mode.

There are many ways to realize three-state hysteresis control, one of which is to use multiple hysteresis loops to select the optimal switch vector group to control the inductor current ripple within the set loop width. The present invention applies this hysteresis loop control method. As analyzed in the previous section, realizing the NBHCM mode operation of TLDBI requires selecting different switching modules in the positive and negative half cycles of the output current i _o to realize it, which is different from the traditional bridge inverter. The present invention proposes a three-power The hysteresis current control method for the three-state operation of the non-bias current half-cycle operation mode of the flat double-buck half-bridge inverter:

Introduce the given signal of the current loop, that is, the current reference signal (that is, the voltage error signal) i _g , as one of the control variables of the module conversion, and select the switch mode M ₁ ~ M ₃ in the area where i _g > 0 to realize 0 state , -1 state and +1 state; in the area where i _g <0 select switch modes M ₄ ~ M ₆ to realize 0 state, +1 state and -1 state.

Set two hysteresis control inner-loop references ±h ₁ and two hysteresis control outer-loop references ±h ₂ . The current ripple of the control inductor is within the two inner loops ±h ₁ , and the other two outer loop references ±h ₂ are used as the second control variable of the module conversion.

Figure 5, Figure 6 and Figure 7 are the functional block diagram, control logic diagram and waveform diagram of the NBHCM mode tri-state operation control of TLDBI respectively. TLDBI’s NBHCM mode three-state operation has two module conversion control variables: current reference signal i _g and two hysteresis control outer loop references ± h ₂ . Feedback energy A to output energy D are within the four output and feedback energy areas Each is realized by the same switch mode group (see Table 2). Output energy area B → feedback energy area C and output energy area D → feedback energy area A module conversion is controlled by the sign of the current reference signal i _g , feedback energy area A → output energy area B and feedback energy area C → output The module switching in the energy D area is controlled by the sign of the difference between the current error signal _ie and the reference ±h ₂ of the two hysteresis control outer loops.

The system block diagram is shown in Figure 5, and the control circuit adopts double closed loop of voltage and current. The voltage outer loop plays the role of voltage stabilization. After the output voltage detection signal is compared with the reference voltage sine wave, the voltage error signal i _g is obtained through the voltage error amplifier. The voltage error signal is used as the reference of the current loop, and is compared with the detection signal of the output current (the sum of the currents of the inductors L ₁ and L ₂ ) to generate the current error signal i _e . Taking i _g and i _e as control variables, i _g and the zero-crossing comparator get the sign signal of i _g , and i _e compares with the four hysteresis reference ±h ₁ and ±h ₂ signals to obtain four hysteresis error logic signals, Taking these four hysteresis error logic signals and the sign of i _g as the input of the logic circuit, according to the control logic of the NBHCM mode tri-state operation of TLDBI mentioned above (see Fig. 6), generate and drive the power switches S ₁ ~ S ₄ The signal controls the current of the inductors _L1 and _L2 to work in the half cycle of the output cycle (as shown in Figure 2 waveform), and at the same time controls the high frequency ripple of the inductor current within the specified ring width range, and realizes the three-state operation.

Here take i _o leading u _o as an example to illustrate the specific operation control, see Figure 6 and Figure 7:

When the state changes from i _g <0 to i _g >0, select the switching mode group (M ₁ -M ₃ ) to realize the 0 state, -1 state and +1 state. In this area, it is divided into feedback energy area A and output energy area B, which operate in two modes respectively.

Feedback energy area A: set the initial switching mode M ₁ state (0 state), i _e rises, when i _e >+h ₁ , it is converted to switching mode M ₂ state (-1 state), i _e decreases; When i _e <-h ₁ , the switching mode M ₂ is converted to the switching mode M ₁ state. So cycle. In this area, the 0 state and the -1 state are respectively realized by the switch mode _M1 and the switch mode M2.

Output energy area B: When _ie <-h ₂ , the feedback energy area A is converted to the output energy area B. In this area, the switching mode M ₂ and the switching mode M ₃ respectively realize the 0 state and the +1 state. When the switching mode M ₃ state (+1), i _e rises, when i _e >+h ₁ , it is converted to the switching mode M ₁ state (0 state), i _e falls; when i _e <-h ₁ , from switch mode M ₁ to switch mode M ₃ state. So cycle.

When the state changes from i _g >0 to i _g <0, select the switch mode group (M ₄ ˜M ₆ ) to realize the 0 state, +1 state and -1 state. In this area, it is divided into the feedback energy C area and the output energy area D, which operate in two modes respectively.

Feedback energy area C: set the initial switching mode M ₄ state (0 state), i _e drops, when i _e <-h ₁ , it is converted to switching mode M ₅ state (+1 state), i _e rises; When i _e >+h ₁ , the switching mode M ₅ is converted to the switching mode M ₄ state. So cycle. In this region, the switch mode _M4 and the switch mode _M5 realize the 0 state and the +1 state respectively.

Output energy D area: when _ie >+h ₂ , the feedback energy C area is converted to the output energy D area. In this area, the switch mode M ₄ and the switch mode M ₆ respectively realize the 0 state and the -1 state. When the switching mode M ₆ state (-1), i _e falls, when i _e <-h ₁ , it is converted to the switching mode M ₄ state (0 state), i _e rises; when i _e >+h ₁ , from switch mode M ₄ to switch mode M ₆ state. So cycle.

Claims (3)

1, a kind of three-level dual-buck half-bridge inverter main circuit topology, it is characterized in that, comprise power circuit, two three-level buck formula circuit, described power circuit is composed in series by first power supply (Ud1) and second source (Ud2), and series connection point connect " ", the composition of first three-level buck formula circuit is to be connected in first power switch pipe (S1) anode by first power supply (Ud1) positive pole, the negative electrode of first power switch pipe (S1) is connected with second power switch pipe (S2) anode, second power switch pipe (S2) negative electrode is connected in first filter inductance (L1) input, the output of first filter inductance (L1) is connected in filter capacitor (Cf) positive pole, filter capacitor (Cf) negative pole by connect " " line links to each other with first power supply (Ud1) negative pole, the positive pole of first fly-wheel diode (D1) links to each other with first power supply (Ud1) negative pole, the negative pole of first fly-wheel diode (D1) is connected in the contact of connecting of first power switch pipe (S1) and second power switch pipe (S2), the negative pole of second fly-wheel diode (D2) is connected in second power switch pipe (S2) negative electrode, and the positive pole of second fly-wheel diode (D2) is connected in the negative pole of second source (Ud2); The composition of second three-level buck formula circuit is the negative electrode that is connected in the 3rd power switch pipe (S3) by second source (Ud2) negative pole, the anode of the 3rd power switch pipe (S3) is connected with the 4th power switch pipe (S4) negative electrode, the 4th power switch pipe (S4) anode is connected in second filter inductance (L2) end, second filter inductance (L2) other end by filter capacitor (Cf) through connect " " line and second source (Ud2) are anodal links to each other, the positive pole of the 3rd fly-wheel diode (D3) is connected in the contact of connecting of the 3rd power switch pipe (S3) and the 4th power switch pipe (S4), the negative pole of the 3rd fly-wheel diode (D3) connect " ", the 4th fly-wheel diode (D4) positive pole is connected in the 4th power switch pipe (S4) anode, and negative pole is connected in first power supply (Ud1) positive pole.

2, a kind of no bias current half period operation method of three-level dual-buck half-bridge inverter, it is characterized in that, three-level dual-buck half-bridge inverter is first bridge arm voltage (UA) output positive voltage (+Ud) "+1 attitude " under no bias current half load cycle operating mode, (" 1 attitude " Ud) and first bridge arm voltage (UA), second bridge arm voltage (UB) all are output as 0 " 0 attitude " to second bridge arm voltage (UB) output negative voltage, be called for short "+1 attitude ", " 1 attitude ", three operating states of " 0 attitude ", utilize the first switch mode (M1) of the first switch mode group respectively, second switch mode (M2), (M4) of the 4th switch mode of the 3rd switch mode (M3) and second switch mode group, the 5th switch mode (M5), the 6th switch mode (M6) realizes, the first switch mode group realizes the positive half period electric current output of inverter: when needing the output positive voltage, when promptly exporting energy, select the first switch mode (M1) and the 3rd switch mode (M3); When needing the output negative voltage, when being feedback energy, select the first switch mode (M1) and second switch mode (M2), second switch mode group realizes the output of inverter negative half-cycle electric current: when needing the output positive voltage, when promptly exporting energy, select the 4th switch mode (M4) and the 5th switch mode (M5); When needing the output negative voltage, when being feedback energy, select the 4th switch mode (M4) and the 6th switch mode (M6), when selecting the first switch mode (M1), first power switch pipe (S1) turn-offs, (S2) is open-minded for second power switch pipe, third and fourth two power switch pipes (S3, S4) all turn-off, and the electric current of first filter inductance (L1) still powers to the load by first fly-wheel diode (D1) afterflow, first bridge arm voltage (UA) is output as 0, promptly realizes " 0 attitude "; When selecting second switch mode (M2), first, second, third and fourth four power switch pipes (S1, S2, S3, S4) all turn-off, the electric current of first filter inductance (L1) is by second fly-wheel diode (D2) afterflow, to the power supply feedback energy, first bridge arm voltage (UA) equals negative output voltage and (Ud), promptly realizes " 1 attitude "; When selecting the 3rd switch mode (M3), first and second two power switch pipes (S1, S2) are open-minded, three, the 4 two power switch pipe (S3, S4) turn-offs, the electric current of first filter inductance (L1) powers to the load by first power switch pipe (S1) and second power switch pipe (S2), first bridge arm voltage (UA) equal positive output voltage (+Ud), promptly realize "+1 attitude "; When selecting the 4th switch mode (M4), first, second, third these three power switch pipes (S1, S2, S3) turn-off, and (S4) is open-minded for the 4th power switch pipe, and second bridge arm voltage (UB) is output as 0, promptly realize " 0 attitude "; When selecting the 5th switch mode (M5), first, second, third and fourth four power switch pipes (S1, S2, S3, S4) all turn-off, the electric current of second filter inductance (L2) is by the 4th fly-wheel diode (D4) afterflow, to the power supply feedback energy, second bridge arm voltage (UB) equal positive output voltage (+Ud), promptly realize "+1 attitude "; When selecting the 6th switch mode (M6), first, second two power switch pipes (S1, S2) turn-off, three, the 4 two power switch pipe (S3, S4) is open-minded, the electric current of second filter inductance (L2) powers to the load by the 3rd, the 4 two power switch pipe (S3, S4), second bridge arm voltage (UB) equals negative output voltage and (Ud), promptly realizes " 1 attitude ".

3, a kind of control method of three-level dual-buck half-bridge inverter, it is characterized in that, three-level dual-buck half-bridge inverter at the method for controlling hysteresis loop current of the ternary operation of no bias current half load cycle operating mode is, introduce the given signal of electric current loop, be current reference signal (ig) is realized electric current as the converted controlled condition of the first switch mode group and second switch mode group interior ring control, at current reference signal (ig) greater than 0 zone, select three switch mode (M1 of the first switch mode group, M2, M3) realize that first bridge arm voltage (UA) is output as 0 " 0 attitude ", (" 1 attitude " Ud) and first bridge arm voltage (UA) are exported positive voltage, and (+Ud) "+1 attitude " is hereinafter to be referred as " 0 attitude " for first bridge arm voltage (UA) output negative voltage, " 1 attitude ", three operating states of "+1 attitude ".At output current for just, output voltage is the A district in negative feedback energy district: only select the first switch mode (M1) and second switch mode (M2) to realize that first bridge arm voltage (UA) is output as 0 " 0 attitude " and first bridge arm voltage (UA) output negative voltage (" 1 attitude " Ud), when selecting the first switch mode (M1), first power switch pipe (S1) turn-offs, (S2) is open-minded for second power switch pipe, the 3rd, the 4 two power switch pipe (S3, S4) all turn-off, the electric current of first filter inductance (L1) is by first fly-wheel diode (D1) afterflow, first bridge arm voltage (UA) is output as 0, promptly realizes " 0 attitude "; When selecting second switch mode (M2), first, second, third and fourth four switching power tubes (S1, S2, S3, S4) all turn-off, the electric current of first filter inductance (L1) passes through second fly-wheel diode (D2) to the power supply feedback energy, first bridge arm voltage (UA) equals negative output voltage (Ud), promptly realize " 1 attitude ", obtain negative output voltage; Be the B district of the output energy range of timing at output current and output voltage: only select the 3rd switch mode (M3) and the first switch mode (M1) to realize that (+Ud) "+1 attitude " and first bridge arm voltage (UA) is output as 0 " 0 attitude " to first bridge arm voltage (UA) output positive voltage, when selecting the 3rd switch mode (M3), first, the second two power switch pipe (S1, S2) open-minded, the 3rd, the 4 two power switch (S3, S4) turn-off, the electric current of first filter inductance (L1) is by first, the second two power switch (S1, S2) power to the load, first bridge arm voltage (UA) equal positive output voltage (+Ud), promptly realize "+1 attitude ", obtain positive voltage output; When selecting the first switch mode (M1), first power switch pipe (S1) turn-offs, (S2) is open-minded for second power switch pipe, the 3rd, the 4 two power switch pipe (S3, S4) turn-off, the electric current of first filter inductance (L1) is by first fly-wheel diode (D1) afterflow, first bridge arm voltage (UA) is output as 0, promptly realize " 0 attitude ", select three switch mode (M4 of second switch mode group less than 0 zone at current reference signal (ig), M5, M6) realize that second bridge arm voltage (UB) is output as 0 " 0 attitude ", (" 1 attitude " Ud) and second bridge arm voltage (UB) are exported positive voltage (+Ud) "+1 attitude " these three operation modes to second bridge arm voltage (UB) output negative voltage, at output current is negative, output voltage is the C district in positive energy feedback district: only select the 4th switch mode (M4) and the 5th switch mode (M5) to realize that second bridge arm voltage (UB) is output as 0 " 0 attitude " and second bridge arm voltage (UB) and exports positive voltage (+Ud) "+1 attitude ", when selecting the 4th switch mode (M4), first, second, the 3rd these three power switch pipe (S1, S2, S3) turn-off, (S4) is open-minded for the 4th power switch pipe, the electric current of second filter inductance (L2) is by the 3rd fly-wheel diode (D3) afterflow, second bridge arm voltage (UB) is output as 0, promptly realizes " 0 attitude "; When selecting the 5th switch mode (M5), first, second, third and fourth four power switch pipes (S1, S2, S3, S4) all turn-off, the electric current of second filter inductance (L2) is by the 4th fly-wheel diode (D4) afterflow, to the power supply feedback energy, second bridge arm voltage (UB) equal positive output voltage (+Ud), promptly realize "+1 attitude ", obtain positive voltage output; Be the D district of negative output energy range at output current and output voltage: only select the 6th switch mode (M6) and the 4th switch mode (M4) to realize that (" 1 attitude " Ud) and second bridge arm voltage (UB) are output as 0 " 0 attitude " to second bridge arm voltage (UB) output negative voltage, when selecting the 6th switch mode (M6), first, the second two power switch pipe (S1, S2) turn-off, the 3rd, the 4 two power switch pipe (S3, S4) open-minded, the electric current of second filter inductance (L2) is by the 3rd, the 4 two power switch pipe (S3, S4) power to the load, second bridge arm voltage (UB) equals negative output voltage (Ud), promptly realize " 1 attitude ", obtain negative voltage output; When selecting the 4th switch mode (M4), first, second, third these three power switch pipes (S1, S2, S3) turn-off, (S4) is open-minded for the 4th power switch pipe, the electric current of second filter inductance (L2) is by the 3rd fly-wheel diode (D3) afterflow, second bridge arm voltage (UB) is output as 0, realize promptly " 0 attitude " that the conversion between conversion between feedback energy A district in above-mentioned two switch mode groups and the output energy B district and feedback energy C district and the output energy D district is by two ring control outer shroud benchmark (± h that stagnate are set ₂) and current error signal (ie) realize, when current error signal (ie) less than the negative ring control outer shroud benchmark (h that stagnates ₂) time, realize that feedback energy A district is transformed into output energy B district or is transformed into feedback energy C district by output energy D district; When current error signal (ie) is controlled outer shroud benchmark (+h greater than the ring that just stagnates ₂) time, realize being transformed into feedback energy A district or being transformed into output energy D district by feedback energy C district by output energy B district; The first switch mode (M1) in feedback energy A district and the conversion between the second switch mode (M2), the first switch mode (M1) in output energy B district and the conversion between the 3rd switch mode (M3), the 4th switch mode (M4) in the 4th switch mode (M4) in feedback energy C district and the conversion between the 5th switch mode (M5) and output energy D district and the conversion between the 6th switch mode (M6) are by cyclic group standard (± h in two ring controls that stagnate is set ₁) and current error signal (ie) realize, in feedback energy A district: when current error signal (ie) less than the negative ring control that stagnates in cyclic group standard (h ₁) time, be transformed into second switch mode (M2) by the first switch mode (M1); Cyclic group standard (+h in current error signal (ie) is controlled greater than the ring that just stagnates ₁) time, be transformed into the first switch mode (M1) by second switch mode (M2), in output energy B district: cyclic group standard (h in current error signal (ie) is controlled less than the negative ring that stagnates ₁) time, be transformed into the 3rd switch mode (M3) by the first switch mode (M1); Cyclic group standard (+h in current error signal (ie) is controlled greater than the ring that just stagnates ₁) time, be transformed into the first switch mode (M1) by the 3rd switch mode (M3), in feedback energy C district: cyclic group standard (h in current error signal (ie) is controlled less than the negative ring that stagnates ₁) time, be transformed into the 4th switch mode (M4) by the 5th switch mode (M5); Cyclic group standard (+h in current error signal (ie) is controlled greater than the ring that just stagnates ₁) time, be transformed into the 5th switch mode (M5) by the 4th switch mode (M4), in output energy D district: cyclic group standard (+h in current error signal (ie) is controlled greater than the ring that just stagnates ₁) time, be transformed into the 6th switch mode (M6) by the 4th switch mode (M4); Cyclic group standard (h in current error signal (ie) is controlled less than the negative ring that stagnates ₁) time, be transformed into the 4th switch mode (M4) by the 6th switch mode (M6), realized current inner loop control simultaneously, control inductance pulsating quantity is cyclic group standard (± h in two stagnate ring control ₁) in; Adopt current reference signal (ig) as two switch mode group converted controlled conditions, output energy B district transfers feedback energy C district to and output energy D district transfers positive and negative the controlling of the mode group conversion in feedback energy A district by reference signal (ig) to, when current reference signal (ig) greater than zero the time, realize the mutual conversion in output energy B district and feedback energy C district; When current reference signal (ig) less than zero the time, realize feedback energy A district and the mutual conversion of exporting energy D district.

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