CN100426466C - Method for forming flash unit array with reduced word line spacing - Google Patents

Abstract

A method of forming a NAND-type flash memory device comprising: forming a control gate polycrystalline silicon layer on the substrate; forming a mask layer on the control gate polysilicon layer, the mask layer including mask patterns defining a plurality of spaced word lines of the flash memory device, the word lines being spaced apart from one another by a distance X that is less than a minimum feature size F that is imageable by a selected photolithography process for forming at least a portion of the mask layer patterns; and etching the control gate polysilicon layer through the mask layer. The mask layer forming step comprises: forming a first layer on the control gate polysilicon layer and patterning the first layer using a photolithography process to form a first set of spaced mask portions for defining a first set of spaced word lines, with a distance of F +2X between adjacent first set of spaced mask portions; forming spacers on the sidewall edges of the first set of spaced mask portions; forming a second layer between the spacers, the second layer defining a second set of spaced word lines; the spacers are removed to form a mask pattern.

Description

Method of forming flash cell array with reduced word line pitch

technical field

The present invention relates to a flash memory device and a method of manufacturing the same.

Background technique

NAND (NAND) type EEPROM (Electrically Erasable Programmable Read-Only Memory) or flash memory has been developed for solid-state mass storage applications in portable music players, mobile phones, digital cameras, etc., and it has been considered as a hard disk Drive (HDD) replacement. Therefore, these devices are desired to have greater capacity, lower cost and reduced unit size for miniaturization, increased processing speed.

NAND device structures are generally designed such that: (1) each memory cell utilizes a transistor with a floating gate and a control gate; and (2) a single contact window (contact). Therefore, as compared with conventional EEPROM, although the cell spacing is usually limited by the selected photolithography process, the area occupied by the memory cells is reduced and the integration density can be increased.

US Patent No. 5,050,125 (hereinafter referred to as the '125 patent) discloses a non-volatile semiconductor memory, wherein each bit line includes a string of flash memory cell arrays (as shown in the cross-sectional view of FIG. 4 of the '125 patent). The cell size or area is defined by the required overlap area of the floating gate and control gate. The cell size of each cell of the '125 patent cannot be shrunk below about 4F ² -5F ² , where "F" is the minimum dimension for photolithographic imaging, i.e. photolithography used in the fabrication process of the '125 patent The minimum feature size or line width to obtain. The smallest known feature size is about 90nm. Conclusion Assume that the minimum width of the floating gate is approximately 1F, and the minimum width of the space between adjacent floating gates in the floating gate array is also approximately 1F, while the minimum width of the control gate is approximately 1F, and adjacent The minimum spacing between the control gates is about 1F, meaning that each cell occupies at least a minimum of 2F in the X direction (horizontal direction facing the cross-sectional view of Figure 4 of the '125 patent), and at least 2F in the Y direction (relative to The other two-dimensional direction of the horizontal direction in FIG. 4 of the '125 patent) occupies at least a minimum of 2F to 2.5F.

US Patent No. 6,580,120 to Haspeslagh proposes a device with reduced wordline pitch, but utilizes a complex multi-set wordline formation process.

Therefore, it is desirable to increase the integration density of flash memory arrays using processes that can be easily integrated.

Contents of the invention

A method of forming a NAND flash memory device comprising: forming a control gate polysilicon layer on a substrate; forming a mask layer on the control gate polysilicon layer, the mask layer including a plurality of spaced words defining the flash memory device A mask pattern of lines, said word lines being spaced apart from each other by a distance X less than a minimum feature size F imageable by a selected photolithographic process for forming at least a portion of said mask layer pattern and etching the control gate polysilicon layer through the mask layer. Wherein, the mask layer forming step includes the following steps: forming a first layer on the control gate polysilicon layer, and using the photolithography process to pattern the first layer to form a first set of interval masks Part, the first group of spaced mask parts define the first group of spaced word lines, and the distance between adjacent mask parts of the first group of spaced intervals is F+2X; in the first group forming spacers on sidewall edges of the spaced mask portions; forming a second layer between the spacers, the second layer defining a second set of spaced word lines; and removing the spacers, thereby The mask pattern defining the number of spaced apart word lines is formed.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a circuit diagram of a portion of a flash memory having several NAND memory cells.

2 is a cross-sectional view of a cell string of an exemplary memory device showing word line spacing.

2 is a cross-sectional view of a cell string of an exemplary memory device showing word line spacing.

3A-3F illustrate an exemplary method of fabricating the structure of FIG. 2 .

4A-4D illustrate a step in fabricating a SONOS memory cell structure.

Description of main component marking

BL0, BL1: bit lines

WL0, WL1, WL2, ..., WLn: word lines

SSL, GSL: select line

M _nm : memory cell

SL0, SL1, GSL0, GSL1: select transistors

10: base

12: triple well area

14: Injection area

16: Gate dielectric layer

18: Memory unit

20a, 20b: selection transistors

22, 122: floating gate

24, 32, 34, 124: insulating layer

26, 126: Control grid

28, 128: silicide layer

30: plug

36: Conductive bit line

38: interlayer window

130, 130', 134: oxide mask

132: SiN layer

132': spacer wall

200: ONO layer

202, 206: insulating layer

204: storage layer

F, X: size

Detailed ways

Referring to FIG. 1 , an electrically erasable programmable read-only memory (EEPROM) is shown, including an array of memory cells formed on a chip substrate. As will be recognized by those skilled in the art, Figure 1 is a circuit diagram of a portion of a NAND flash memory array. Various elements such as row and column decoders, sensing circuits and other control circuits have not been shown to avoid obscuring the disclosure of the invention. However, these components are well known to those skilled in the art.

The memory array includes several parallel bit lines BL0, BL1, ..., BLm connected to memory cells _Mnm , where "n" represents the column number of the cell location in the memory array and "m" represents its row number. Parallel word lines WL0, WL1, WL2, . . . , WLn are insulated on the substrate to form control gates for the flash memory cells M _nm formed at each cell site. Selection transistors SL0 , SL1 , etc., and GSL0 , GSL1 , etc. are formed at respective ends of the bit line BL.

An exemplary memory array is divided into a number of "blocks" of memory. Each block has a number of "pages". A page has many "cells" of memory. For example, a 1Gb memory has 1024 blocks, and one block has 64 pages. Each page has 2K bytes (ie 16K bits). A word line contains one or more pages. Each block provides one cell string or two cell strings in the bit line direction. One cell string has 16 bits, 32 bits or 64 bits. One cell stores one bit, or two bits, such as in the case of the SONOS memory cells discussed below.

In one embodiment, programming, erasing and reading operation conditions are as follows:

erase programming read Selected WL 0V 20V 0V Unselected WL 0V 10V 4.5V SSL floating VCC 4.5V GSL floating 0V 4.5V BL (programming to 0) floating 0V N/A BL (to 1 programming) floating VCC N/A Ontology (bulk) 20V 0V N/A

In this program/erase method, Fowler-Nordheim (FN) tunneling is used for programming and erasing of NMOS NAND flash memory cells. During programming, a higher positive voltage is applied to the word line of selected cells. A voltage is applied to the unselected word lines to turn on the cells. A ground voltage or 0V is applied to the bit line to write data "0", and VCC is applied to write data "1". 0V is delivered to the channel of the selected cell, FN tunneling is performed to inject electrons from the channel to the floating gate. When the data is "1", the word line voltage connects the channels and there is negligible FN tunneling current, so the cell is not programmed. For erasing, the P-type well of the cell is biased with a high voltage and all word lines in the selected block are grounded. Electrons tunnel from the floating gate FN to the P-well substrate.

Fig. 2 is a side cross-sectional view of a cell string. The cell string includes select transistors 20a, 20b, wherein a number of NMOS floating gate flash cell transistors 18 are formed between the select transistors 20a, 20b. Although the select transistors 20a, 20b are shown as double gate transistors, single gate transistors could also be used as shown in FIG. 1 .

之间的SiO₂。源极/漏极注入区域较佳地为N+注入区域14，其形成于单元18之间，且形成于单元18与选择晶体管20a、20b之间。在一实施例中，N+注入区域14包含浓度约为1×10¹⁸到5×10¹⁹atoms/cm³的砷或磷的掺质。In one embodiment, the substrate 10 includes a p-type doped silicon substrate, and the p-type doped silicon substrate has a triple well region 12 formed in a cell array region therein. The triple well includes an n-type well surrounding a p-type well. For example, alternative embodiments may utilize an n-type doped substrate and alternative well arrangements. Although described herein in connection with NMOS flash memory cells, the memory cells may also include PMOS cells formed on a p-type substrate. The gate dielectric layer 16 is thermally grown on the substrate 10, and preferably includes being formed to a thickness of about 70-110

between SiO ₂ . The source/drain implant regions, preferably N+ implant regions 14, are formed between cells 18 and between cells 18 and select transistors 20a, 20b. In one embodiment, the N+ implanted region 14 contains arsenic or phosphorus dopant at a concentration of about 1×10 ¹⁸ to 5×10 ¹⁹ atoms/cm ³ .

之间的多晶硅层，且更佳地约500

的多晶硅层。介电层24形成于浮动栅极22上并包含热氧化层，譬如形成为厚度约110～140

的SiO₂，或具有约110～140

之间的有效氧化物厚度的ONO(氧化物/氮化物/氧化物)层。可使用LPCVD(低压化学气相沉积)工艺沉积所述ONO层，其具有从SiH₂CL₂/O₂气体沉积约20厚度的顶部氧化层，具有从SiH₂CL₂/O₂气体沉积约40厚度的底部氧化层，且具有从SiH₂CL₂/N₂气体沉积约80

厚度的SiN层。控制栅极26形成自若干平行单元串共用的字线，且控制栅极26形成于介电层24上，且较佳地包含具有约700～1000

之间厚度的多晶硅层28。硅化物层28较佳地包含钨(W)硅化物层，可视情况形成于控制栅极/字线26上。Each cell 18 includes a conductive floating gate 22 formed on the gate dielectric layer 16, preferably comprising a thickness of about 300-1000

between polysilicon layers, and preferably about 500

polysilicon layer. The dielectric layer 24 is formed on the floating gate 22 and includes a thermal oxide layer, for example, formed to a thickness of about 110-140

SiO ₂ , or with about 110-140

The effective oxide thickness in between is the ONO (Oxide/Nitride/Oxide) layer. The ONO layer can be _deposited using LPCVD (low pressure chemical vapor _deposition ) process, which has about ₂₀ thickness of _the top _oxide layer, with about ₄₀ thickness _{of the} bottom oxide layer, and has about ₈₀

thickness of the SiN layer. The control gate 26 is formed from a word line shared by several parallel cell strings, and the control gate 26 is formed on the dielectric layer 24, and preferably includes a thickness of about 700˜1000

The thickness of the polysilicon layer 28 between. The silicide layer 28 preferably comprises a tungsten (W) silicide layer, optionally formed on the control gate/word line 26 .

A planarizing insulating layer 32 is formed over the cell strings, which may include one or more individual dielectric layers. A connection hole is formed through a dielectric layer 32 and filled with a polysilicon plug 30 to be electrically connected to the selection transistor 20 . A conductive bit line 36 , for example comprising tungsten (W), is formed on the second insulating layer 34 and connected to the polysilicon plug 30 through a conductive via 38 .

It will be apparent to those skilled in the art that when the control gate 26 and silicide layer 28 (when present) form a word line across several strings of cells as shown in FIG. 1 , the floating gate of each cell 22 and dielectric layer 24 are surrounded by an insulating layer that separates cells in individual strings from each other and from cells of adjacent strings.

As shown in FIG. 2, each transistor cell 18 has a channel length F defined by the smallest dimension that can be imaged by the photolithography process used to pattern the memory array. Each select transistor 20 a and 20 b preferably has a length 2F (to avoid shoot-through problems, minimize source-to-drain leakage current, etc.), and is spaced a distance F from the respective plug 30 . Each plug has a pitch of 2F. Importantly, each floating gate cell 18 is spaced from an adjacent floating gate cell 18 by a distance "X" less than "F" and from an adjacent select transistor 20 (for an end cell 18) by a distance "X" distance. The total unit string length is equal to 8F+mF+(m+1)X, where "m" is the total number of units in the unit string, usually 16, 32 or 64. In one embodiment, X is equal to 0.03 μm and F is equal to 0.09 μm and there are 16 units, so the total unit string length is only 24F+(17/3)F=29.7F. As in the prior art, if X is equal to F, then the total string length will be 41F. Also, assuming again that X is equal to 1/3F, the cell size is about (F+X)2F (or about ( ^2.66F2 )) instead of ^4-5F2 .

An exemplary method of forming the closely spaced word line structure of FIG. 2 is described with reference to FIGS. 3A-3F . 3A-3F illustrate front-end-of-line (FEOL) process steps for creating a memory structure. The process steps used to form the interconnect circuitry required to address individual memory cells, i.e., the formation of back-end-of-line circuits such as contacts, vias, metal lines, and corresponding insulating layers, are not discussed here. line, BEOL) process.

之间。接着，在多晶硅层122上形成ONO介电层124。接着，将控制栅极多晶硅层126沉积为厚度在约700～1000

之间。最后，沉积或形成钨硅化物层128于控制栅极多晶硅层126上，使其厚度约为300

Referring to FIG. 3A , a material stack for forming individual memory cell transistors is first formed on the gate dielectric layer 16 . Specifically, the floating gate polysilicon layer 122 is deposited to a thickness of about 300-1000

between. Next, an ONO dielectric layer 124 is formed on the polysilicon layer 122 . Next, the control gate polysilicon layer 126 is deposited to a thickness of about 700-1000

between. Finally, a tungsten silicide layer 128 is deposited or formed on the control gate polysilicon layer 126 to a thickness of about 300

之间，且更佳地约为1000氧化物掩膜130由使用光刻工艺所成像的光刻胶掩膜来图案化和蚀刻的氧化层形成，其中“F”为可成像的最小尺寸。每一掩膜130具有宽度F。接着，将SiN层132沉积于所述结构上，即沉积于氧化物掩膜130和硅化物层128上。譬如通过低压化学气相沉积(LPCVD)工艺将SiN层132沉积为厚度小于F，且在一实施例中约为300。在实施例中，氧化物掩膜130区彼此间隔一段距离F+2X，其中X为图2中所示字线之间的距离。所述距离确实由光刻工艺界定，且其可将特征尺寸界定为小至F。Referring to FIG. 3B, a first oxide layer is deposited or formed over the suicide memory cell stack (ie, layers 122, 124, 126, 128), patterned and etched to form spaces spaced to define a first set of spaces. A first set of oxide masks 130 for word lines and memory cells. In one embodiment, the thickness of the oxide mask 130 is about 900-1500

between, and more preferably about 1000 The oxide mask 130 is formed from an oxide layer patterned and etched using a photoresist mask imaged by a photolithography process, where "F" is the smallest dimension that can be imaged. Each mask 130 has a width F. Next, a SiN layer 132 is deposited on the structure, ie on the oxide mask 130 and the silicide layer 128 . For example, the SiN layer 132 is deposited by a low pressure chemical vapor deposition (LPCVD) process to a thickness less than F, and in one embodiment about 300 . In an embodiment, the oxide mask 130 regions are spaced apart from each other by a distance F+2X, where X is the distance between word lines shown in FIG. 2 . The distance is indeed defined by the photolithography process, and it can define feature sizes as small as F.

Referring to FIG. 3C , portions of the SiN layer 132 are removed leaving SiN sidewall spacers 132 ′ on the sidewalls of the oxide mask 130 . Endpoint detection can be used to monitor the etch process. In an exemplary embodiment, an anisotropic dry etching process using Ar/CF ₄ reactive gas may be used to etch the SiN layer 132 . The etching process is stopped when the oxide layer 130 is detected. Since the oxide is thicker than the SiN formed therebetween, once the oxide is detected, only a portion of the SiN layer 132 adjacent to the oxide portion remains. SiN spacers 132' have a thickness equal to "X", which is the space between word lines, and about the same as the deposited thickness of layer 132 .

Referring to FIG. 3D, a second oxide layer (not shown) is then deposited on the structure of FIG. 3C to fill the open spaces between the spacers 132', and it is etched back to retain the second set of spacer oxide masks 134. . Oxide mask 130 continues, but is designated 130' because it may be slightly etched during exposure of spacers 132' through the second oxide layer. Each oxide portion 130', 134 has a width equal to F and is separated from an adjacent oxide portion by a spacer 132' having a width equal to X, where X is less than F. Layers 130' and 134 together form an oxide mask for forming spaced word lines and memory cells. Although only 11 oxide mask sections are shown, it should be understood that 16, 32, or 64 sections could be provided for forming the number of word lines in a cell string, and additional oxide sections could be provided for forming select transistors ( not shown in the figure).

In an alternative embodiment, masks 130, 134 are formed of SiN, and layer 132 (and thus spacers 132') are formed of oxide.

Referring to FIG. 3E, the SiN spacer 132' is removed, and the oxide mask layer of FIG. 3D is used to etch through the layers 122, 124, 126 and 128 to form the spacer memory cell 18 of FIG. 2, which has a width F and are separated by a distance X from each other. A dry etching process using an Ar/CF ₄ reaction solution may be used to remove the SiN spacer 132'. A dry etch process using a Cl ₂ /HBr solution may be used to etch the control gate polysilicon layer 126 , and the same solution may be used to etch the silicide layer 128 . A dry etching process using a CHF ₃ /CHF ₄ /He solution may be used to etch the ONO dielectric layer 124 . Finally, a dry etch process using a Cl ₂ /HBr solution may be used to etch the floating gate polysilicon layer 122 .

As shown in FIG. 3F , mask portions 130 ′ and 134 are removed by an etching process, and implanted regions 14 are formed in substrate 10 adjacent to and between individual memory cells 18 .

An alternative program/erase method can also be used for the memory cell array of Figure 1, which utilizes hot hole injection by BTBT (Band-to-Band Tunneling) to remove stored electrons during programming. Tunneling occurs at the intersection of the source/drain (S/D) junction and the tunnel oxide. The n+S/D-to-substrate junction is reverse biased to such an extent that soft breakdown or Zener breakdown occurs. The pn junction has current flow when electrons tunnel from the valence band to the conduction band at the S/D and crossover points. Holes are generated in the valence band, and the floating gate attracts the holes by applying a negative voltage on the control gate. Negative voltage on the control gate also enhances BTBT current. If the accessed cell is not being programmed, the bit line is biased at 0V and the S/D junction is not reverse biased. There is no BTBT tunneling current under this condition. Erase is performed by selecting all cells in the block to have a higher threshold. During erase, electrons tunnel from the channel to the floating gate through FN tunneling. The programming, erasing and reading conditions are summarized in the table below.

erase programming read Selected WL 20V -5V 0V Unselected WL 20V 10V 4.5V SSL VCC 10V 4.5V GSL 0V floating 4.5V BL (programming to 0) 0V 7V N/A BL (to 1 programming) 0V 0V N/A Ontology 0V 0V N/A

Hot hole injection creates holes trapped in the tunnel oxide and can degrade program-erase endurance characteristics. Hole-type traps are located near the edge of the drain junction, which affects channel hot electron injection for programming. Existing hole-type traps will reduce the electric field near the drain and make hot electrons less efficient. However, since the erasing is done by FN tunneling over the entire tunnel oxide region, the impact of this mechanism is low in the programming method proposed above. Although this mechanism can cause disturbances in NOR flash, it does not cause disturbances in NAND flash. Unselected word lines have a high voltage to pass the bit line voltage. Cells on unselected word lines do not have BTBT disturb. Unselected blocks also have select transistors to protect the cells. The bit line voltage cannot be delivered to the cell. To ensure that the S/D junction is reverse biased, the S/D needs to be forward biased. The bias voltage comes from the bit line. Assume, for example, that WL2 is selected and the cell is programmed. WL0 and WL1 are unselected word lines between selected word lines and bit lines. Pull WL0, WL1 and SSL to 10V. Set WL2 to -5V. The 7V bias on the bit line will pass to the S/D region between WL1 and WL2. The S/D regions will have BTBT tunneling current. Negatively biased WL2 attracts holes to the floating gate of this cell. Since WL2 is negatively biased and biased below Vth for the erased state, the cell is turned off. Therefore, the 7V bias will not pass to WL3 and other word lines.

Figures 4A-4D illustrate the process described above in connection with Figures 3A-3F as applicable to the formation of SONOS (silicon/ONO/silicon) memory cells such as those described in US Patent No. 6,580,120 to Haspeslagh, cited in The method is incorporated in this article in its entirety. In FIGS. 4A to 4D , reference numerals similar to those in FIGS. 3A to 3F refer to similar structures.

之间。层200包含第一绝缘层202、储存层204和第二绝缘层206。可使用LPCVD(低压化学气相沉积)工艺沉积所述ONO层，其具有从SiH₂CL₂/O₂气体沉积约20

厚度的顶部氧化层206，具有从SiH₂CL₂/O₂气体沉积约40

厚度的底部氧化层202，且具有从SiH₂CL₂/N₂气体沉积约80

厚度的SiN储存层204。As shown in FIG. 4A , an ONO layer 200 is formed on a substrate 10 . ONO layer 200 preferably has an effective oxide thickness of about 110-140

between. Layer 200 includes a first insulating layer 202 , a storage layer 204 and a second insulating layer 206 . The ONO layer can be _deposited using LPCVD (low pressure chemical vapor _deposition ) process, which has about ₂₀

thickness _{of the} top oxide layer ₂₀₆ , with approximately 40

thickness _of the bottom oxide _layer 202, and has about ₈₀

thick SiN storage layer 204 .

The rest of the process is basically the same as described above in connection with FIGS. 3A-3F . A control gate polysilicon layer 126 is formed on layer 200 . A silicide layer 128 is optionally formed, followed by a first set of spaced apart oxide mask 130 and SiN layer 132 .

Referring to FIG. 4B, the SiN layer 132 is etched to form SiN spacers 132'. In FIG. 4C , a second oxide layer is deposited and etched to expose the SiN spacers 132 ′, leaving a second set of spaced apart oxide masks 134 . As shown in FIG. 4D , the SiN spacers 132 ′ are removed, and then the mask set is used to etch through the suicide layer 128 and the top polysilicon layer 126 .

In an embodiment, FIG. 4D shows the final cell structure, although mask portions 130' and 134 are shown removed. In an alternative embodiment, the etch process continues from the ONO layer 200 to the substrate 10 . In this alternative embodiment, implanted regions are formed (as shown above in Figure 3F) and FN tunneling is used for programming/erasing. The program/erase/read conditions for implanted embodiments are shown in the table below for NMOS cells.

erase programming read Selected WL 0V 12～15V 0V Unselected WL 0V 6～9V 4.5V SSL floating 6～9V 4.5V GSL floating 0V 4.5V BL (programming to 0) floating 0V N/A BL (to 1 programming) floating 6～9V N/A Ontology 12～15V 0V N/A

If no implanted region exists, then source side injection is used for programming and FN tunneling is used for erasing. The program/erase method is described in US Patent No. 6,580,120, which is incorporated herein by reference in its entirety. An exemplary read condition is also described in the '120 patent.

In summary, the present invention proposes a method for forming word lines with reduced spacing and forming cells thereof, which has a better integrated process. The reduced cell spacing improves integration density, thereby reducing device size and/or capacity.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (17)

1. A method for forming a NAND flash memory device, characterized in that it comprises the following steps: forming a control gate polysilicon layer on the substrate; A mask layer is formed on the control gate polysilicon layer, wherein the mask layer includes a mask pattern defining a plurality of spaced word lines of the NAND flash memory device, the word lines are spaced apart from each other by a certain distance X and said distance X is less than a minimum feature size F imaged by a selected photolithographic process used to form at least a portion of said mask pattern; and etching the control gate polysilicon layer through the mask layer; Wherein, the mask layer forming step comprises the following steps: A first layer is formed on the control gate polysilicon layer, and the first layer is patterned using the photolithography process to form a first set of spaced mask portions defining A first group of spaced word lines, and a distance of F+2X between adjacent mask parts of the first group of spaces; forming spacers on sidewall edges of the first set of spaced apart mask portions; forming a second layer between the spacers, the second layer defining a second set of spaced apart word lines; and The spacers are removed, thereby forming the mask pattern defining the plurality of spaced word lines. 2. The method for forming a NAND flash memory device according to claim 1, wherein the spacer is silicon nitride and the first and second layers are oxides, or the first and second layers is silicon nitride and the spacer is oxide. 3. The method for forming a NAND flash memory device according to claim 2, wherein the spacer forming step comprises the following steps: depositing a spacer layer on the first layer and between the first set of spaced apart mask portions; and The spacer layer is etched from above the first layer and between the first set of spaced apart mask portions to form the spacers. 4. The method for forming a NAND flash memory device according to claim 1, wherein said second layer forming step comprises the following steps: depositing the second layer on the substrate, including the first layer and the spacers; and The second layer is etched to expose the spacers. 5. The method for forming a NAND flash memory device according to claim 4, wherein the first layer has 1000

thickness, and the spacer has a 300 thickness of. 6. The method for forming a NAND flash memory device according to claim 1, further comprising a step of forming implanted regions in the substrate between the spaced word lines after the etching step. 7. The method for forming a NAND flash memory device according to claim 1, wherein the control gate polysilicon layer is formed on the oxide/nitride/oxide layer. 8. The method for forming a NAND flash memory device according to claim 7, wherein the oxide/nitride/oxide layer has a thickness between 110-140

The effective oxide thickness between. 9. The method for forming a NAND flash memory device according to claim 1, further comprising a step of forming a silicide layer on the control gate polysilicon layer. 10. The method for forming a NAND flash memory device according to claim 1, further comprising the steps of: forming a floating gate polysilicon layer over the active area in the substrate; and A dielectric layer is formed on the floating gate polysilicon layer, wherein the etching step includes etching the floating gate polysilicon layer and the dielectric layer. 11. The method for forming a NAND flash memory device according to claim 1, further comprising the steps of: forming a first insulating layer on the substrate; forming a storage layer on the first insulating layer; A second insulating layer is formed on the storage layer, wherein the control gate polysilicon layer is formed on the second insulating layer. 12. The method for forming a NAND flash memory device according to claim 1, wherein the mask layer is oxide. 13. A method of forming a NAND flash memory device, characterized in that it comprises the following steps: forming a dielectric layer on the substrate; forming a polysilicon control gate layer on the dielectric layer; depositing a first mask layer on the polysilicon control gate layer; etching the first mask layer to form a first set of spaced mask portions defining a first set of spaced word lines, each mask portion having a width and the width adjacent mask portions are separated by a distance that is greater than the minimum feature size and less than three times the minimum feature size, depending on the minimum feature size imaged by the selected lithographic process; forming spacers on sidewalls of the first set of spaced apart mask portions; A second set of spaced mask portions are formed between the spacers and define a second set of spaced word lines; removing the spacers to form a mask pattern in which the first set of spaced mask portions are alternately spaced apart from the second set of spaced mask portions by a separation distance smaller than the minimum feature size; and The polysilicon control gate layer is etched through the mask pattern. 14. The method for forming a NAND flash memory device according to claim 13, wherein the forming step of the mask part between the spacer and the second group comprises the following steps: forming a sacrificial layer on the first set of spaced mask portions; etching the sacrificial layer to form the spacers on sidewalls of the first set of spaced mask portions; forming a layer of masking material over the first set of spaced apart mask portions and spacers; The layer of masking material is etched to expose the first set of spaced apart masking portions, wherein portions of the layer of masking material remain to form the second set of spaced apart masking portions. 15. The method for forming a NAND flash memory device according to claim 13, wherein the mask part of the first group of intervals is oxide or silicon nitride, and the mask part of the second group of intervals is oxide compounds or silicon nitride. 16. The method for forming a NAND flash memory device according to claim 13, wherein the dielectric layer is an oxide/nitride/oxide layer. 17. The method for forming a NAND flash memory device according to claim 16, wherein the dielectric layer is formed on the floating gate polysilicon layer, and the etching step also includes passing through the first and second A set of spaced mask portions etches the dielectric layer and the floating gate polysilicon layer.

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