CN100425015C - coherent detection and decoding method and device - Google Patents

Abstract

The invention discloses a detecting and decoding method, which is applied to the second stage of cell search of a code division multiple access system and detects a secondary synchronous code of an incoming signal from a base station, and the detecting and decoding method mainly comprises the following steps: coherently calculating the correlation values of the secondary synchronization codes, wherein the correlation values are obtained by inner code detection and outer code detection designed for all the secondary synchronization codes; selecting the maximum correlation value on each time slot as the secondary synchronization code detected by the time slot, and forming a code word; and decoding the codeword with a coherent weighted non-interrupted Reed-Solomon code after receiving all or part of the codeword to obtain the code group and frame synchronization of the incoming signal. The invention further discloses a detection and decoding device for realizing the detection and decoding method of the invention.

Description

Coherent detection and decoding method and device

technical field

The invention relates to a detection and decoding method and device, which are used in the decoding process of a communication system. More particularly ^, it relates to a detection and decoding method and device for cell search ( cell search). The method and device use coherent detection and coherent weighted continuous Reed-Solomon code (comma-free Reed Solomon code, CFRS) decoding to effectively improve performance.

Background technique

CDMA cellular systems using a direct sequence spread spectrum code division multiple access technique greatly increase channel capacity. This system has attracted considerable attention in recent research on mobile communication systems. Generally speaking, due to the nature of frequency reuse, the bandwidth efficiency of CDMA systems is superior to that of other multitasking access systems (such as frequency division multiple access and time division multiple access) . In addition, cell planning is quite simple in CDMA systems. Therefore, the code division multitasking access cell system will be the mainstream in the future. In particular, the ^3rd Generation Partnership Project (3GPP) Wideband Code Division Multiple Access/Frequency Division Duplex (W-CDMA/FDD) system has been adopted in a third generation system for IMT-2000 one of the standards.

In a CDMA cell-based system, the method used by a user equipment (UE) to search for the best cell is called "cell search". Fast cell search is very important, in order to reduce the user equipment start-up delay time (switched-on delay) (initial search, initial search), increase standby (standby time) (idle state search, idle mode search) and in handover (handover) ( Action state search, active mode search) to maintain a good communication link quality.

Please refer to FIG. 1 , which is helpful to understand the frame structure of a 3rd Generation Partnership Project (3GPP) broadband CDMA/FDM system. First of all, in the Broadband CDMA/FDMA system of the 3rd Generation Partnership Project (3GPP), cell search is generally completed by means of three stages, which include two special A designed synchronization channel (synchronization channel, SCH) and a common pilot channel (common pilot channel, CPICH). In the first phase 110, a primary synchronization channel (PSCH) 111 is used for slot synchronization. The primary synchronization channel 111 includes a primary synchronization code (PSC) defined as ac _p , where “a” (=±1) depends on the presence or absence of diversity transmission of the base station. In the second stage 120, the secondary synchronization channel (SSCH) 121 is used for frame/codegroup identification. The secondary synchronization channel 121 includes secondary synchronization codes (secondary synchronization codes, SSCs) defined as ac _s , where the coefficient a is equal to the coefficient of the primary synchronization channel. In the third stage 130, the common pilot channel 131 is used for downlink scrambling code determination. As shown, 15 time slots are included in a 10 millisecond (ms) frame (radioframe), and because a speed of 3.84 million chips per second (Mchips/sec) is used in the system. Therefore, each frame contains 38400 chips (chips), that is, each time slot contains 2560 chips. In addition, the P-SCH and the S-SCH have a length of 256 chips and are only transmitted at the beginning of the slot boundary.

In recent years, fast cell search methods for CDMA cell-based systems have been disclosed. See U.S. Patent No. 6,185,244 to Nystrom et al., entitled "Cell searching in a CDMA communications system." Seen in U.S. Patent No. 6,289,007 issued to Kim et al., entitled "Method for Acquiring A Cell Site Station in Asynchronous CDMA Cellular Communication Systems" ). And see U.S. Patent No. 6,038,250 issued to Shou et al., titled "Initial Synchronization Method And Receiver For DS Relay Station Asynchronous Cell System" (Initial Synchronization Method And Receiver for DS -CDMA InterBase Station Asynchronous Cellular System). However, since the frequency offset comes from the unstable frequency of the crystal oscillator of the user equipment, for the user equipment, the carrier frequency of the incoming signal may have a frequency offset, thus causing a frequency offset.

In the past, the secondary synchronization detection device used in the second stage of cell search can be roughly divided into two stages: (1) secondary synchronization code matched filter (secondary synchronization code matched filter), used to detect the secondary synchronization code and (2) Decoder, which performs a decoding process according to the code word detected by the secondary synchronization code matched filter. The secondary synchronization code matched filter adopts a non-coherent structure to resist performance degradation caused by frequency offset and multipath fading channel. This technique can be found in Y.P.E.Wang and T.Ottosson, "Initial frequency acquisition in W-CDMA," IEEE Proc.VTC'99, Vol.2, pp.1013-1017, Sept.1999. In addition, the decoder part can be roughly divided into soft decision (Soft Decision) and hard decision (Hard Decision) methods. However, a Soft Decision decoder requires a large number of calculations, thus increasing the complexity of the device. Therefore, a Hard Decision Hamming correlator is generally used. The Hammy correlator design makes the complexity relatively low, but its performance is also low.

Contents of the invention

The main object of the present invention provides a kind of detection and decoding method, is used for the cell search of code division multiple access system, is more particularly used in the second stage of the cell search of broadband code division multiple access system, adopts coherent type detection method and coherent The weighted uninterrupted Reed-Solomon code decoding method can reduce the effect of frequency offset in the system and the influence of multi-path fading channels on the degradation of cell search characteristics, thereby accomplishing the purpose of quickly completing cell search.

A secondary object of the present invention is to provide a detection and decoding device for cell search in a code division multiple access system, more particularly for the second stage of cell search in a broadband code division multiple access system, using coherent detectors and The decoder of coherent weighted uninterrupted Reed-Solomon code can reduce the effect of frequency offset in the system and the influence of multipath fading channel on the degradation of cell search characteristics.

For reaching above-mentioned main object, the present invention provides a kind of detection and decoding method, is applied to the second stage of the cell search of code division multiple access system, and this detection and decoding method mainly comprises the following steps: coherently calculate this secondary A correlation value of the synchronization code, wherein the correlation values of the secondary synchronization codes (correlation values of the secondary synchronization codes) come from the coherent type secondary synchronization code detector; on each time slot, the maximum correlation value is selected as the The secondary synchronization code detected by the time slot and form a code word; and after receiving the whole or part of the code word, a coherent weighted non-stop Reed-Solomon code decodes the code word to obtain the The code group and frame synchronization of the incoming signal.

For reaching above-mentioned secondary purpose, the present invention provides a kind of detection and decoding device, is used for the cell search of code division multiple access system, is more particularly used in the second stage of the cell search of broadband code division multiple access system, and this detection The AND decoding device includes: a coherent secondary synchronization detector for selecting a code word of a primary synchronization code of the incoming signal; and a coherent weighted non-stop Reed-Solomon code decoder for performing the The decoding of the incoming signal to obtain the code group and frame synchronization of the incoming signal.

The present invention has the following advantages:

(1) The secondary synchronization detection method of the present invention adopts a coherent detection method, which can effectively reduce the influence of frequency offset and multi-path fading channel effect on the degradation of cell search characteristics, and its effect is better than that of the non-coherent coherent type.

(2) The secondary synchronization detection method of the present invention adopts a coherent weighted continuous Reed-Solomon decoding method, which can achieve a better match between system performance and complexity.

(3) In practical application, the secondary synchronous detection device of the present invention can be implemented in the form of hardware, especially in the form of a chip, and this design will be particularly beneficial to the development of a system-on-chip (SoC).

Description of drawings

FIG. 1 shows a frame structure diagram of a broadband CDMA/FDM system used in the 3rd Generation Partnership Project (3GPP).

FIG. 2 shows a flowchart of a detection and decoding method according to the present invention.

FIG. 3 a is an embodiment of block 10 of FIG. 2 .

FIG. 3b is an embodiment of block 20 of FIG. 2 .

FIG. 3c is an embodiment of block 30 of FIG. 2 .

FIG. 4 shows a structural diagram of a detection and decoding device according to the present invention.

FIG. 5 a is an embodiment of the coherent SSC detector in FIG. 4 .

FIG. 5b is an embodiment of the coherently weighted non-stop Reed-Solomon code decoder in FIG. 4 .

Label description:

111 primary synchronization channel

131 common pilot channel

510 Coherent Secondary Sync Detector 511 Inner Code Matched Filter

512 outer code matched filter 513 cache unit

514 code word selection unit

520 coherent weighted non-stop Reed-Solomon code detector

521a, 521b delay components 522a, 522b multiple computing units

523 accumulation unit 524 selection unit

Detailed ways

Generally speaking, cell search needs to go through three synchronization stages in sequence, which are (1) the first stage: slot synchronization (slot synchronization) (2) the second stage: frame synchronization/code group determination (frame synchronization/code group identification) (3) The third stage: scrambling code identification (scrambling code identification). Please refer to FIG. 2 , which shows a flowchart of a detection and decoding method according to the present invention, which can be used to effectively improve the performance of cell search. The method can be used in the second stage of the cell search in the CDMA system, that is, the detection and decoding of the secondary synchronization code to obtain the frame synchronization/code group decision, but it is not limited to this application. In step 10, the correlation values of the SSCs are coherently calculated, wherein the correlation values are obtained by detecting inner codes and outer codes designed for all SSCs. In step 20, the largest correlation value is selected in each time slot as the secondary synchronization code detected in the time slot, and a code word is formed. In step 30, after receiving the whole or part of the code word, the code word is decoded with a coherent weighted continuous Reed-Solomon code to obtain the code group and frame synchronization of the incoming signal.

FIG. 3 a is an embodiment of step 10 of FIG. 2 . Wherein step 10 also includes the following steps: in step 11, the 256 chips of the secondary synchronization code are divided into W sections, each section has 256/W code chips, wherein W is a suitable positive integer, Each small segment is called an inner code. In step 12, the inner codes corresponding to the W segments and the 16 SSCs are detected, that is, the inner codes are detected. For example, if it is divided into 4 segments, and each segment has 64 chips, then the inner code detection has 4 output values. In step 13, the outer code detection is performed on the W segment, and the W segments are matched with 16 secondary synchronization codes, wherein the W segment of the outer code detection has a corresponding output of the inner code detection. In step 14, the output value of each outer code detection is multiplied by the conjugate complex number of the output value of a primary synchronous code detection (in the first stage) corresponding to its time to obtain a multiplied value; The primary synchronization code is orthogonal to the primary synchronization code. In step 15, the real part of the multiplied value in each segment is taken and accumulated to obtain a correlation value, that is, each secondary synchronization code is divided into W segments and accumulated. In step 16, the correlation value obtained in step 15 is taken as a frame cycle, and the correlation value accumulated for all secondary synchronization codes in each time slot is used as the basis for judging the code word.

FIG. 3b is an embodiment of step 20 of FIG. 2 . When the required secondary synchronization code of the second stage is completely received, the following steps are also included in step 20: in step 21, the correlation value of all secondary synchronization codes obtained in step 16 is selected on each time slot The maximum value is stored, and a total of P correlation values are obtained (P is an integer ranging from 3 to 15). In step 22, a complete or partial set of codewords is obtained according to the collected secondary synchronization codes detected, that is, P correlation values.

FIG. 3c is an embodiment of step 30 of FIG. 2 . Wherein step 30 also comprises the following steps: in step 31, this code word has P symbols, corresponding to the secondary synchronous code represented by this symbol and its correlation value size (this correlation value has received all the secondary synchronization codes that want to receive) After the synchronization code, the correlation value stored in step 22), the P symbols are compared with each symbol of the uninterrupted Reed-Solomon code; where the comparison is correct, the corresponding symbol of the code word Multiplied by a positive number to form a weighted value, otherwise multiplied by a negative number to form another weighted value. So on and so forth. It should be noted that the design of the positive and negative numbers can be changed and is determined by the designer. According to the coherent decoding method disclosed in the present invention, the weighted value is the result obtained in step 31 . In step 32, the weighted values obtained after comparing the P symbols with 960 possible codewords are accumulated as the comparison result until 960 comparisons are completed. In step 33, the maximum value among the 960 comparison results is selected as the code group and frame synchronization of the incoming signal.

FIG. 4 shows a structural diagram of a detection and decoding device according to the present invention. A detection and decoding device, which is applied to the secondary synchronization code detection of the cell search of the code division multiple access system, and is more particularly used for the second stage of the cell search of the broadband code division multiple access system, and detects the second stage from the base station A secondary synchronization code of an incoming signal, the detection and decoding device 500 includes: a coherent type secondary synchronization code detector 510, used for codeword selection of a secondary synchronization code of the incoming signal, and a coherent weighted type The discontinuous Reed-Solomon code decoder 520 is used to decode the incoming signal to obtain the code group and frame synchronization of the incoming signal.

FIG. 5 a is an embodiment of the coherent secondary sync detector 510 in FIG. 4 . The coherent secondary sync detector 510 further includes: an inner code matched filter 511 ; an outer code matched filter 512 ; a buffer unit 513 and a code word selection unit 514 . As shown in the figure, the inner code matched filter 511 is used for inner code detection of the secondary synchronization code. The 256 chips of the SSC are divided into W segments, each segment has 256/W chips, where W is an appropriate positive integer, and each small segment is called an inner code. The inner code matched filter 511 performs matching for the W segments and the 16 SSCs respectively. For example, if it is divided into 4 segments, and each segment has 64 chips, then the inner code matched filter has 4 output values. The outer code matched filter 512 is used for the outer code detection of the SSC, wherein the outer code matched filter 512 is also matched with the 16 SSCs for the W segments respectively. The corresponding output value of the inner code matched filter 511 is stored in the W segment of the outer code matched filter 512, and the output value of the outer code matched filter 512 is matched with a primary synchronous code corresponding to its time. The complex conjugates of the output values of the filters (in the first stage) are multiplied to obtain a multiplied value; wherein the secondary synchronization code is orthogonal to the primary synchronization code. The outer code matched filter 512 takes the real part of the multiplied value in each section and accumulates it to obtain a correlation value output by the outer code matched filter 512, that is, each secondary synchronization code is divided into W areas segment accumulation. With the above steps, the correlation value of the real number can be obtained at the output end of the outer code matched filter 512 . . The buffer unit 513 accumulates and stores the correlation value output by the outer code matched filter 512 in a frame cycle on each time slot and stores it in the buffer unit 513 until all secondary synchronization codes to be received are received. , select the maximum value of the correlation values of all secondary synchronization codes obtained in each time slot, and store them, and obtain P new correlation values (P is an integer ranging from 3 to 15), wherein the P The new correlation value is a real value. After receiving all secondary synchronization codes to be received, the code word selection unit 514 obtains a complete set (when P=15) or part (when 2<P) of P (an integer) new correlation values <15) codeword.

FIG. 5 b is an embodiment of the coherently weighted non-stop Reed-Solomon code decoder 520 in FIG. 4 . The coherent weighted continuous Reed-Solomon code detector 520 further includes: a plurality of delay components 521a, 521b . . . ; a plurality of calculation units 522a, 522b . The coherent weighted non-stop Reed-Solomon code detector 520 operates on a codeword, which is generated by the coherent secondary sync detector 510, against 960 possible combinations of non-stop Reed-Solomon codes. acquired.

For example, the codeword has P symbols, which are selected by the codeword selection unit 514 and correspond to the secondary synchronization code represented by the symbol and its correlation value, wherein the selected secondary synchronization code is used as the 960 The basis for the comparison of possible codewords, and the correlation value is used as the basis for generating the weight. The P symbols of the codeword enter a plurality of delay components 521a, 521b, respectively, the first symbol enters the first delay component 521a, the second symbol enters the second delay component 521b, and so on. The P symbols of the codeword are compared with each symbol from the non-stop Reed-Solomon code respectively. After the comparison, if the first symbol is correctly compared, the symbol is represented by a positive value in the calculation unit 522a; if the second symbol is compared incorrectly, the symbol is represented by a positive value in the calculation unit 522b. Negative values represent. So on and so forth. It should be noted that the positive and negative values are determined by the designer. Finally, the correlation value stored in the delay element is multiplied by the corresponding positive value or negative value in the calculation unit 522 a , 522 b , etc. to become an input signal of the accumulation unit 523 . The accumulating unit 523 accumulates all the input signals, and each accumulation can obtain an accumulated value as a comparison result. Before the decoding is completed, the accumulating unit 523 generates a total of 960 comparison results, which are sequentially input to the selection unit 524 .

After these 960 comparisons, the selection unit 524 is connected to the accumulation unit 523 to select the maximum value among the 960 comparison results, and the uninterrupted Reed-Solomon code corresponding to this value is what we have determined Code group and corresponding frame synchronization. The selection method of this maximum value is as follows, in the first comparison, the first output of the accumulation unit 524 is compared with the preset numerical value (this numerical value is determined by the designer) in the selection unit 524, and the larger numerical value is compared. The code word corresponding to it is stored in the selection unit 524 , and thereafter, each new input signal is compared with the signal stored in the selection unit 524 , and the larger value after the comparison is stored. By analogy, the code group and frame synchronization can be judged by the data stored in the selection unit 524 until the 960 comparisons are completed.

In practical application, the detection and decoding device of the present invention can be implemented in the form of software and hardware because the functions of each block are clear, especially implemented in the form of a chip to be embedded in the cell search circuit.

Therefore, according to the detection and decoding method for the CDMA system of the present invention, the effects of frequency offset and multi-path fading channels can be effectively reduced in the CDMA system, and cell search can be quickly achieved.

According to the detection and decoding device used in the code division multiple access system of the present invention, the system performance can be effectively improved under the frequency offset and multi-path fading channel effects. The method and apparatus according to the present invention can be used in mobile devices and wireless personal digital assistant (PDA) systems.

Although the present invention has been disclosed with the foregoing preferred embodiments, it is not intended to limit the present invention. Any skilled person may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be defined by the claims.

Claims (8)

1. one kind is detected and interpretation method, is applied to the second stage of the cell search of code division multiple access system, and this second stage detects the secondary synchronization sign indicating number from an entering signal of base station, and it is characterized in that: this detection and interpretation method comprise the following step:

(a) coherently calculate the correlation of this secondary synchronization sign indicating number, wherein this correlation by the ISN at all secondary synchronization sign indicating numbers designs detect with outer sign indicating number detect it;

(b) on each time slot, select maximum correlation value as the detected secondary synchronization sign indicating number of this time slot, and form a code word;

(c) finish the code word that receives this whole or part by a phase dry type secondary synchronization detector after, with a relevant weighting type free of discontinuities Reed Solomon code this code word is deciphered, with code group and the frame synchronization that obtains this entering signal.

2. detection as claimed in claim 1 and interpretation method is characterized in that: wherein step (a) also comprises the following step:

(a-1) 256 chips with this secondary synchronization sign indicating number are divided into W section, and every section has 256/W chip, and wherein W is a suitable positive integer, and wherein each away minor segment is referred to as ISN;

(a-2) detect its pairing ISN at 16 secondary synchronization sign indicating numbers respectively;

(a-3) this W section is carried out outer sign indicating number and detect, mate with 16 secondary synchronization sign indicating numbers, have the output of corresponding ISN detection in W section of its China and foreign countries' sign indicating number detection at the outer sign indicating number testing result of W section;

(a-4) output valve that each outer sign indicating number is detected and its time conjugate complex number of going up the output valve of corresponding one elementary synchronous code detection in the phase I multiply each other the value that multiplies each other; Wherein this secondary synchronization sign indicating number and this elementary synchronous code quadrature;

(a-5) this value of multiplying each other in each section is got add up behind its real part a correlation, meaning promptly, each secondary synchronization sign indicating number is divided into W section and adds up;

(a-6) this correlation with step (a-5) is the cycle with the frame, adds up the foundation that the correlation of gained is judged as this code word slot synchronization on each time slot respectively at all secondary synchronization sign indicating numbers.

3. detection as claimed in claim 2 and interpretation method is characterized in that: wherein step (b) also comprises the following step:

(b-1) be chosen in the maximum of this correlation of all secondary synchronization sign indicating numbers of gained of step (a-6) on each time slot, and store, obtain P new correlation altogether, wherein P is the integer between 3 to 15;

(b-2) collect detected secondary synchronization sign indicating number thus, promptly P correlation obtains one group of complete or code word partly.

4. detection as claimed in claim 1 and interpretation method is characterized in that: wherein step (c) also comprises the following step:

(c-1) this code word has P symbol, each symbol of this P symbol and this free of discontinuities Reed Solomon code is compared, wherein compare correct person, the pairing correlation of the symbol of this code word is multiplied by a positive number and forms a weighted value, forms another weighted value otherwise then be multiplied by a negative;

(c-2) add up this P symbol respectively with 960 kinds may code words the weighted value of comparison back gained as the result of comparison, finish up to 960 comparisons;

(c-3) select maximum in 960 comparison results, with Rule of judgment as the code group and the frame synchronization of this entering signal.

5. one kind is detected and code translator, is applied to the second stage of the cell search of code division multiple access system, and described second stage detects the secondary synchronization sign indicating number from an entering signal of base station, and it is characterized in that: this detection and code translator comprise:

One phase dry type secondary synchronization detector carries out outer sign indicating number and detects being divided into W section in this secondary synchronization sign indicating number, mates at outer yard testing result and 16 secondary synchronization sign indicating numbers of W section, is used to select the code word of this entering signal;

One relevant weighting type free of discontinuities Read-Solomon code decoder, connect this phase dry type secondary synchronization detector after, be used to carry out the decoding of this entering signal, with code group and the frame synchronization that obtains this entering signal.

6. detection as claimed in claim 5 and code translator, it is characterized in that: 256 chips of this secondary synchronization sign indicating number are divided into W section, every section has 256/W chip, wherein W is a suitable integer, each away minor segment is referred to as ISN, detects pairing ISN at 16 secondary synchronization sign indicating numbers, is referred to as ISN and detects, this W section is carried out outer sign indicating number detect, mate at outer yard testing result and 16 secondary synchronization sign indicating numbers of W section.

7. detection as claimed in claim 6 and code translator is characterized in that: wherein this phase dry type secondary synchronization detector also comprises:

One ISN matched filter, the ISN that is used for this secondary synchronization sign indicating number detects;

One outer yard matched filter, the outer sign indicating number that is used for this secondary synchronization sign indicating number detects, and obtaining multiply each other a value and a correlation, this value of multiplying each other multiplies each other from the conjugate complex number of the output valve of corresponding one elementary synchronous code matched filter in the phase I on the output valve of this outer sign indicating number matched filter and its time and obtains; This correlation outside this in sign indicating number matched filter, is got this value of multiplying each other in each section to add up behind its real part and is obtained, and that is to say that each secondary synchronization sign indicating number is divided into W section and adds up; Wherein this secondary synchronization sign indicating number and this elementary synchronous code quadrature;

One buffer unit, the correlation of sign indicating number matched filter output is the cycle with the frame outside being used for being somebody's turn to do, on each time slot, add up and store, behind the secondary synchronization sign indicating number of receiving all desires receptions, on each time slot, select the maximum of this correlation of all secondary synchronization sign indicating numbers, and store and obtain the new correlation of P altogether, P is the integer between 3 to 15;

One code word selected cell is used for when P=15 obtaining one group of complete code word at P new correlation, o'clock obtains the part code word in P new correlation in 2＜P＜15.

8. detection as claimed in claim 5 and code translator is characterized in that: wherein should also comprise by relevant weighting type free of discontinuities Read-Solomon code decoder:

A plurality of Delay Elements are used for P symbol of this code word and each symbol of this free of discontinuities Reed Solomon code are compared;

A plurality of computing units are connected in this a plurality of Delay Elements, be used for producing on the occasion of with negative value, wherein the symbol of this code word is if comparison is correct, then produce one on the occasion of, otherwise then be a negative value;

One unit that adds up, be connected in a plurality of computing units, be used to the input signal that adds up, adding up can obtain an accumulated value as comparison result at every turn, wherein this input signal by be stored in correlation in the Delay Element be multiplied by respectively this correspondence of this computing unit on the occasion of or negative value;

One selected cell is connected in this unit that adds up, and selects the maximum in the comparison result, and the pairing free of discontinuities Reed Solomon code of this maximum is as the code group of judging this entering signal and the basis for estimation of pairing frame synchronization.

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