CN100421172C - Magnetic Tunnel Junction Memory Cell Structure - Google Patents

Abstract

A storage device, including a magnetic tunnel junction memory unit, has a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to an electrical conductor for writing to the magnetic tunnel junction structure. In another example, the read switch is a transistor electrically connected to the magnetic tunnel junction structure through a deep via contact. In another example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of electrical conductors respectively associated with the cells for writing information into the associated magnetic tunnel junction structures. Each read switch is connected to electrical conductors associated with other magnetic tunnel junction cells than the cell in which the read switch is present.

Description

Magnetic Tunnel Junction Memory Cell Structure

This application claims priority under 35 U.S.C 119(e)(1) of pending U.S. Provisional Application No. 60/422,225, filed October 30, 2002, and is incorporated herein by reference.

technical field

The invention relates to the field of data storage, and more particularly relates to a memory unit structure of a magnetic tunnel junction device.

Background technique

Magneto-resistive random-access memory (MRAM) is a high-speed, low-voltage, high-density, non-volatile memory in which information bits are stored in a magnetic tunnel junction (MTJ) structure by applying a magnetic field, and by measuring its magnetic Obtain this information bit from MTJ. The advantages of MRAM over other technologies include: a combination of fast read and write, non-volatility, near-infinite cycle capability, full bit changeability, and simple cell structure.

The MTJ is sandwiched between two ferromagnetic (FM) layers separated by a thin insulating layer. A particularly useful MTJ structure is one in which one of the ferromagnetic layers is pinned by exchange biasing the antiferromagnetic layer. For MRAM applications, the MTJ structure is designed to have stable magnetic states corresponding to the parallel and antiparallel orientations of the FM layers in the MTJ device. More specifically, a stack of MTJ material is typically composed of two magnetic layers separated by a thin dielectric barrier. A layer of antiferromagnetic material with strong exchange coupling, such as FeMn or IrMn, is placed in contact with the underlying magnetic layer, locking it in one direction. This layer is separated from the next magnetic layer by a thin layer of Ru, creating a synthetic Antiferromagnet. The strong exchange between the magnetic layers in this synthetic antiferromagnet structure fixes the magnetic polarization of the pinned layer in one direction and prevents the pinned layer from switching during write operations. Assume the fact that the MTJ device acts as a A readout circuit is used to obtain the state of the MTJ device by estimating the MTJ reluctance from a variable resistor of two discrete reluctance values depending on the aforementioned relative orientation of the free magnet to the locked magnet.

The integrated memory cell has a scalable construction process for fabricating the MTJ, and circuitry for writing to and reading from the MTJ. As with most integration processes, lower cost can be achieved by reducing the number of components, simplifying the construction process, and/or reducing the memory cell surface area.

Contents of the invention

The storage device includes a magnetic tunnel junction memory unit, which has a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to the electrical conductor for writing to the magnetic tunnel junction structure. In another example, the read switch is a transistor electrically connected to the magnetic tunnel junction structure through a deep via contact.

In another example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of electrical conductors respectively associated with the cells for writing information into the associated magnetic tunnel junction structures. Each read switch is connected to electrical conductors associated with other magnetic tunnel junction cells than the cell in which the read switch is present.

Description of drawings

For a more complete understanding of the present invention, reference is made to the following detailed description taken in conjunction with the accompanying drawings, in which:

Figure 1 shows a conventional MTJ MRAM cell;

Figure 1A shows a schematic diagram of a part of the MTJ MRAM cell shown in Figure 1;

FIG. 2 shows a magnetic storage structure according to an exemplary embodiment of the present invention;

Figure 2A shows a magnetic storage structure according to another embodiment of the present invention;

FIG. 3 shows a schematic diagram of the magnetic storage structure shown in FIG. 2 and FIG. 2A .

Detailed ways

The numerous innovative teachings of the present application will be described with reference to presently preferred exemplary embodiments. However, it should be understood that such embodiments provide only a few examples of the many many preferred uses and innovative teachings. In general, statements made in the specification of the present application do not necessarily define any of the various claimed inventions. Furthermore, some statements may apply to some inventive features but not to others. Throughout the drawings, it should be noted that the same reference numerals or letters will be used to designate similar or equivalent elements having the same function. Detailed descriptions of known functions and constructions that would make the subject matter of the present invention unclear have been omitted for conciseness.

FIG. 1 shows a cross-section of a conventional example of an MTJ MRAM cell 100 . The diagram runs parallel to and/or cuts through various elements, as described below. Elements of cell 100 include MTJ 114; conductive layer 102 that operates as a bit "write" line and a "read" line for bits stored in MTJ 114; conductive layer 104 that operates as a word "write" line; FET 106, having source 108, drain 110 and gate 112, operates as a switch for reading stored bits. Typically, write lines 102 and 104 are perpendicular to each other, as seen from above cell 100, and lie in separate parallel planes.

MTJ 114 is formed at the intersection of write lines 102 and 104 as described elsewhere. One side of MTJ 114 is in electrical continuity with line 102, while the other side is in electrical continuity with source 108 of FET 106 through electrical path 116, as described further below. Line 104 and MTJ 114 are electrically interrupted.

The drain 110 of FET 106 is connected to ground 118 . Normally, FET 106 is normally non-conductive so that no current can flow from line 102 through MTJ 114 , path 116 and source 108 to “ground”. When an appropriate current is selectively momentarily applied to wires 102 and 104 , it creates an orthogonal magnetic field in MTJ 114 . These fields selectively write or set MTJ 114 in its low reluctance state (R _PARALLEL ) or its high reluctance state (R _ANTIPARALLEL ). The state of the MTJ 114 can then be read by applying a current from a current source to the line 102 and a signal to the gate 112 of the FET, which acts on conduction between the source 108 and the drain 110 . The magnitude of the current flowing through - either low or high - MTJ 114, path 116 and pass FET 106 to "ground" 118 is read to determine whether MTJ 114 is in a high or low resistance state. The high resistance state causes lower current flow through elements 114 , 116 and 106 than the low resistance state.

An MRAM may include a large number of parallel bitlines (BL) 102, and orthogonal wordlines (WL) 104 that are mutually parallel to an MTJ 114 located at each wordline-bitline intersection.

Cell 100 is fabricated by typical integrated circuit techniques using lithographic, doping, and other processes to form regions and layers of various conductors, semiconductors, and insulators. For example, ground 118 in FIG. 1 includes a columnar conductive metal contact 120 in electrical continuity with the diffusion region 110 (i.e., the drain) of the FET at one end and with a common conductive electrode extending into and out of the plane of the figure at the other end. The ground wire 122 is in electrical continuity and is in electrical continuity with similar contacts 120 of other units 100 (not shown). Similarly, portion of path 116 includes a columnar electrical contact 124 connected at one end to source 108 of FET 106 and at the other end to metal element 126 serving as part of path 116 .

As shown, contacts 120 and 124 are coplanar; furthermore, metal element 126 and metal ground 122 are coplanar. In fact, the elements 120, 124 are formed at the same time, and the metal elements 122, 126 are formed at the same time later from the deposited metal layer (M1). Specifically, after forming FET 106, in and on silicon substrate 128, the surrounding areas of FET 106 and the substrate are covered by electrically insulating layer 130 by conventional doping and deposition techniques. The layer 130 serves to protect the FET 106 during fabrication of the cell and later in use. Ultimately, layer 130 has a depth equal to the height of contacts 124 , 120 . Typically, this is accomplished by depositing layer 130 to a depth slightly greater than desired, and then removing the excess by planarization techniques such as chemical-mechanical polishing.

After fabrication of layer 130, it is selectively etched by known photolithographic techniques and other similar techniques to create vias or holes 132, 134 extending through the layer and exposing source and drain electrodes 108 at their bottom. and 110. Metal is then deposited or filled into the vias 132, 134 such that the contacts 120, 124 so formed are in electrical continuity with the contact 110 and the source 108, respectively.

Next, a metal layer M1 is formed, covering the layer 130 and the ends of the contacts 120, 124, with the conductive layer M1 being in electrical continuity therewith. Finally, the depth of layer M1 adopts the desired thickness of components 126 and ground 122 due to the application of the planarization step. Next, photolithography is used to remove excess metal from layer M1 , leaving element 126 and ground 122 .

Path 116 includes contact 142 in electrical continuity with element 126 . Contacts 142 are formed by first depositing insulating layer 144 over layer M1, ground 122, and the planarized top surface of element 126, and then forming vias 146 therethrough by selective etching or other removal techniques. Vias 146 are then filled with the metal of contacts 142 and coplanarity of the top surfaces of layer 144 and contacts 142 is achieved in any convenient manner.

Next, a second metal layer (M2) is coated on the top surface of layer 144 and contacts 142, followed by a lithographic selective etch or other removal technique to remove selected portions of layer M2 to fabricate Word write line 104 and coplanar conductive member 150 are in electrical continuity with contact 142 . Next, an insulating layer 152 is formed on the planarized top surfaces of the wire 104 and the member 150 , and in the space between the wire 104 and the member 150 . Next, contacts 154 are formed in electrical continuity with the top surface of member 150 in vias 156 extending through layer 152 .

On top of the planarized top surface of the insulating layer 152, a metal layer 160 is deposited, followed by selective removal of the layer 160 to leave a metal member 162 electrically connected at one end to the top of the contact 154 with a connection to the member 104 The top surface of the spaced and electrically isolated "free" end. MTJ 114 is fabricated on the top surface of the "free" end of member 162 using similar techniques and is electrically connected to the "free" end of member 162. In addition, known techniques are implemented to provide an additional metal layer (M3), from which an MTJ bit line (BL) 102 is formed, on top of and in electrical continuity with MTJ 114.

Finally, known techniques are implemented to provide another metal layer (M4), from which metal lines 300 are formed, generally perpendicular to and electrically isolated from metal BL 102. The resistance of the aggregated wordline 112 is reduced using a metal line 300 having a relatively low resistance. Aggregating alone would provide the wordline 112 with a detrimentally long RC delay. Typically, metal line 300 has a sheet resistance of approximately 0.1 ohm/sq, shunting to polymeric wordline 112 having a sheet resistance of approximately 5 ohm/sq. As shown in FIG. 1A, metal line 122 is bypassed to aggregated word line 112 every 128 bit lines, which is a typical scheme of conventional MRAM configurations. For example, this bypass can be provided using a technique known from DRAM technology known as stitching. The bonding achieves an ohmic combination of the metal line 300 and the aggregated word line 112, which reduces the overall RC delay and thus increases access time.

Note that metal layer M1 includes elements 122 and 126 , M2 includes elements 104 and 150 , M3 includes element 102 , and M4 includes element 300 . As can be seen, the structure of conventional MTJ MRAM includes multiple fine layers and processes. A reduction in the number of layers and associated deposition operations, etching and other removal operations, and/or other photolithographic operations will reduce manufacturing costs, and/or provide more storage per unit of capacity. An aspect of the present invention reduces the number of layers, more specifically metal layers, thereby advantageously enabling reduced manufacturing costs and/or reduced cell capacity.

FIG. 2 shows a cross-section of an MTJ memory device 200 according to an exemplary embodiment of the present invention. Memory device 200 includes bit lines 102 and word lines 104 for operating MTJ 114 as described above. In addition, the memory device 200 may be fabricated by conventional integrated circuit techniques as described above. However, using the connection and activation scheme of the present invention, layers M1 and M4 (from FIG. 1 ) are eliminated from the current storage device 200 . Line 104 of the current connection and activation scheme is made multifunctional in order to maintain the preferred low ohmic read word line and low ohmic ground provided in conventional MRAM cell 100 through the metal layers (ie M4 and M1 respectively). That is, in addition to the wires 104 used to implement the magnetic field in the MTJ 114, the wires 104 are used to reduce the high ohmic nature of the aggregated WL 112 and provide a low ohmic ground.

To provide a low-ohmic read wordline according to the current connection and activation scheme, each cell's metal wordline 104 is bypassed to its aggregate WL 112. Figures 2 and 3 show this bypass as item 33. FIG. 3 shows a schematic diagram of the MTJ memory device 200 shown in FIG. 2 . For example, bypassing may be provided by bonding techniques, similar to the bonding of metal line 300 to polymeric WL 112 described with respect to FIG. 1A . An advanced signal connection of line 104 (hereinafter referred to and denoted as Adr(n) 104 in FIG. 3 ) combined with a corresponding activation scheme (as described below) is used to cancel M4 ( FIG. 1 ).

To provide a low ohmic ground, Adr(n) 104 of each cell is bypassed to the adjacent cell (shown as item 35 in Figure 3 and shown by the dashed line in Figure 2) also in the bonding process The diffusion ground 110. Thus, Adr(n) 104 in combination with the activation scheme described below also performs the function of metal ground 122 of M1 (in FIG. 1 ), and thus, can be eliminated. Accordingly, contacts 150 can be applied directly to the top surface of contacts 124 , further eliminating contacts 142 and further reducing the overall height of device 200 .

A typical read/write activation scheme according to the magnetic memory structure shown in FIGS. 2 and 3 is described below. First, to write to a particular MTJ cell 114 , an appropriate current is selectively momentarily applied to the write lines BL(n) 102 and Adr(n) 104 associated with the MTJ cell 114 . For example, to write to cell "A" in FIG. 3, a write current (eg, about 5 mA) is applied to Adr(1) and BL(0). Here, the voltage of Adr(1) is about 0.25V, equal to 5mA×50ohm. Furthermore, due to the tie 33 of aggregate WL(1) to Adr(1), the outputs of switches "D" and "E" must be kept at a low voltage (eg 0.25V) to prevent being turned on during writing. Since the diffused region of each switch 106 is tied to the adjacent write line Adr(n) 104, by applying the necessary 0.25 volt signal to all other Adr(n), switches "D" and "E" output remains low.

To read cell "A", current is applied to BL(O) and the switch is turned on by applying an active signal to the gate via Adr(1) and a ground reference to the switch output via the other Adr(n) "D" for conduction through switch "D", which is sensed to determine the state of the MTJ of cell "A". More specifically, Adr(1) is pulled high (eg, about 1.8V) and all other Adr(n) are driven low (eg, ground=0V) to provide a ground connection. Conventional circuitry may be included to sense the magnitude of current flow to determine whether the MTJ 114 is in a high or low resistance state. The high resistance state induces a lower current flow than the low resistance state.

The combination of the current connection and activation scheme provides the functionality of the metal layers M1 and M4 and the write line of the conventional MTJ cell configuration shown in Figure 1 in a single multifunctional metal line.

Referring now to FIG. 2A, another embodiment of the present invention is shown. In this embodiment, contacts 154 , 150 , and 124 (shown in FIG. 2 ) are combined into a single deep contact 250 . Typically, conventional integrated circuit designs require metal-to-metal distances between metal features such as 104 and 150 to be in the range of approximately 0.24 μm (shown as "X" in FIG. 2 ). Using deep via contacts 250, the distance X is significantly reduced (up to 1/3 reduction), and as a result, the overall width of the multi-cell MTJ structure is greatly reduced. Traditionally, via contacts can be made narrower than metal contacts. As shown in FIGS. 2 and 2A , conventional via contacts 124 , 154 , and 250 are narrower than conventional metal features, such as feature 150 (approximately 0.16 μm narrower). As shown in FIG. 2A , the use of deep via contacts allows a reduction from the X dimension of approximately 0.24 μm in FIG. 2 to the corresponding Y dimension of approximately 0.16 μm in FIG. 2A .

Deep via contact 250 is applied to the electrical contact between source 108 and member 162 and can be formed using well known conventional techniques.

While preferred embodiments of the present invention apparatus and method have been shown in the drawings and have been described in the foregoing detailed description, it is to be understood that the invention is not limited to the disclosed embodiments, and is intended to be modified without departing from the disclosed embodiments. Numerous reconfigurations, modifications and substitutions are possible within the spirit of the invention as illustrated and defined by the appended claims.

Claims (10)

1. memory device comprises:

A plurality of magnetic tunnel junction cells, each described magnetic tunnel junction cell comprises magnetic tunnel junction structure (114) and field effect transistor (106), described field effect transistor (106) has the grid (112) that defined the control input, has the source electrode (108) that has defined first node and have the drain electrode (110) that has defined Section Point, and wherein said source electrode (108) links to each other with the magnetic tunnel junction structure (114) of corresponding magnetic tunnel junction cell;

A plurality of electric conductors (104) are associated with described magnetic tunnel junction cell respectively, and each described electric conductor (104) links to each other with related magnetic tunnel junction structure (114), is used for information is write related magnetic tunnel junction structure (114);

It is characterized in that:

Described grid (112) is continuous with the related electric conductor (104) comprising the corresponding magnetic tunnel junction cell of field effect transistor (106) by first bypass (33); And

Described drain electrode (110) by second bypass (35) with except with link to each other comprising one of described electric conductor (104) the related electric conductor (104) of the magnetic tunnel junction cell of described field effect transistor (106).

2. equipment according to claim 1 is characterized in that described first bypass (33) and described second bypass (35) are the stitch bypasses.

3. equipment according to claim 1 is characterized in that described electric conductor (104) is word line (Adr (0), Adr (1), Adr (2)).

4. equipment according to claim 1 is characterized in that described grid (112) is a polysilicon gate.

5. equipment according to claim 1, it is characterized in that comprising the described magnetic tunnel junction cell of many groups, described a plurality of electric conductor (104) is related with described group respectively, each described electric conductor (104) links to each other with the described magnetic tunnel junction structure (114) of associated group, be used for information is write the described magnetic tunnel junction structure (114) of associated group, each each described grid (112) of described group with link to each other with described group of related electric conductor; And each described drain electrode (110) with except with link to each other comprising one of described electric conductor (104) the related electric conductor (104) of the group of described drain electrode (110).

6. equipment according to claim 5, it is characterized in that the described grid (112) in each described group links together, and each of first group described drain electrode (110) in described many groups links to each other all with second group of related electric conductor (104) in described the group more.

7. equipment according to claim 6 is characterized in that each of the 3rd group described drain electrode (110) in described many groups all with described first group of related electric conductor (104) links to each other.

8. equipment according to claim 5 is characterized in that each described group interior described drain electrode (110) links together.

9. equipment according to claim 8 is characterized in that each described group interior described drain electrode (110) ground connection.

10. according to any described equipment of aforementioned claim, it is characterized in that described magnetic tunnel junction cell comprises:

Substrate (128) is gone up formation described field effect transistor (106) at described substrate (128);

Electrical insulation material layer is used to cover described field effect transistor (106);

Conductive member (162), be used to cover described electrical insulation material layer, wherein said magnetic tunnel junction structure (114) is electrically connected with described conductive member (162), and described magnetic tunnel junction structure (114) is formed on described conductive member (162) and the described electrical insulation material layer facing surfaces; And

Single deep via contact (250) is extended by described electrical insulation material layer, and described conductive member (162) is electrically connected with the source electrode (108) of described field effect transistor.

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