CN100418216C - Semiconductor Package and Semiconductor Module - Google Patents

Abstract

Provided are a semiconductor package capable of miniaturization by connecting semiconductor elements without using wire bonding, and a semiconductor module including the semiconductor package. It has: an IGBT element (20), which has an emitter electrode (22), a gate electrode (23), and an emitter electrode on the surface (21a), and has a collector electrode (26) on the back surface (21b); the first electrode plate ( 30), set opposite to the surface (21a) of the IGBT element (20), having a protrusion connected to the emitter (22) by soldering; the second electrode plate (40), and the back surface of the IGBT element (20) (21b) oppositely disposed, having an opposite surface (41b) connected to the collector (26) by brazing; an insulating substrate (50), disposed between the first electrode plate (30) and the IGBT element (20) , with a connection pad connected to the gate electrode (23) and the radiation sensing electrode by soldering.

Description

Semiconductor Package and Semiconductor Module

technical field

The present invention relates to a semiconductor package and a semiconductor module, and particularly relates to a semiconductor package having a semiconductor element for power, a power control device such as an inverter, a converter, etc., and a semiconductor package that is modularized in multiples module.

Background technique

As semiconductor elements for power, IGBT elements (switching elements), IEGTs, MOS-FETs, and the like are often used. All of these power semiconductor elements have front-side power terminals and control terminals on the front surface, and rear-side power terminals on the back surface. In addition, when the power semiconductor element is an IGBT element, the front-side power terminal is an emitter, the back-side power terminal is a collector, and the control terminal is a gate electrode.

When this type of semiconductor element for power is mounted on a substrate and packaged, the power terminal on the back side of the semiconductor element is connected to the electrode on the package side by soldering, and the power terminal and control terminal on the front side of the semiconductor element are passed through using aluminum wires. Wire bonding is used to connect electrodes on the package side (for example, refer to Japanese Patent Laid-Open Document 1 and Patent Document 2).

However, the wire bonding method has the following technical problems: the bonding time is long because the wires are bonded one by one; Fracture or short circuit between adjacent, etc.

Therefore, a method of bonding aluminum thin plates instead of wires to the surface side power terminals of semiconductor elements, and a method of soldering and bonding flat plates or lead wires to lead out as electrodes tend to be adopted. In particular, a method of selecting a material that can be soldered to the front-side power terminal of a semiconductor element, and connecting a plate or a lead to the front-side power terminal by soldering is a technology that has recently attracted attention. Among them, wires bonded by wire bonding are used for the lead-out wiring from the control terminals.

As shown in FIG. 19 , such a semiconductor package 1 includes a plate-shaped IGBT element (semiconductor element) 2 , and a first electrode plate 3 and a second electrode plate 4 sandwiching the IGBT element 2 in a stacked state.

On the surface side of the IGBT element 2, an emitter electrode (power terminal) 2a, a gate electrode (control terminal) 2b, and an emitter electrode (emity sensing electrode) (control terminal) 2c are provided. In addition, collector electrodes (power terminals) 2 d are provided on the back side of the IGBT element 2 . The emitter electrode 2a is connected to the first electrode plate 3 by soldering, and the collector electrode 2d is also connected to the second electrode plate 4 by soldering.

An insulating substrate 5 is disposed near the IGBT element 2 . The insulating substrate 5 is joined to the second electrode plate 4 by soldering using connection pads (not shown) provided on the back surface thereof. As the soldering, a solder sheet cut into a predetermined size, a solder paste printed by a printing method, a solder formed by a plating method, or a solder film formed by a vapor deposition method, etc. are used. The second electrode plate 4 also serves as collector-side wiring and a heat sink, and is fixed to a conductive member (not shown) such as a metal-coated ceramic substrate or a bus bar. In addition, the emitter-side wiring extending from the first electrode 3 is formed by the aluminum tape 8 .

The gate electrode 2b is electrically connected to the connection pad 5b through a bonding wire 6b made of aluminum, and the radiation sensing electrode 2c is electrically connected to the connection pad 5a through a bonding wire 6a made of aluminum. Furthermore, the control wiring 7a is soldered to the connection pad 5a, and the control wiring 7b is soldered to the connection pad 5b.

[Patent Document 1] Japanese Patent Laid-Open No. 2003-110064

[Patent Document 2] Japanese Patent Laid-Open No. 2002-164485

In semiconductor package 1 having the above structure, for wire bonding, gate electrode 2b and emitter electrode 2c of IGBT element 2, connection pad 5a and connection pad 5b on insulating substrate 5 need to be arranged on the same plane. In addition, it is necessary to secure a bonding space, secure a separation distance for preventing short-circuiting between adjacent bonding wires 6a, 6b, secure a separation distance for preventing short-circuiting between bonding wires 6a, 6b and control wirings 7a, 7b, and the like. Therefore, the planar size of the second electrode plate 4 increases, and the size of the semiconductor package 1 increases. Furthermore, leaving the wire bonding process in the manufacturing process of the semiconductor package 1 is disadvantageous in terms of equipment investment and engineering management.

Contents of the invention

The present invention is intended to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor package that can be miniaturized by connecting semiconductor elements without using wire bonding, and a semiconductor module including the semiconductor package.

The first characteristic of the embodiment of the present invention is that, in the semiconductor package, there is: a plate-shaped semiconductor element having a first power terminal and a control terminal on the main surface, and a second power terminal on the back surface opposite to the main surface. Terminals; the first electrode plate is arranged opposite to the main surface of the semiconductor element, and has a first power electrode connected to the first power terminal by soldering; the second electrode plate is arranged opposite to the back surface of the semiconductor element, and has The second power electrode connected to the second power terminal by soldering; the insulating substrate is arranged between the semiconductor element and the first electrode plate, and has a control electrode connected to the control terminal by soldering; A protruding portion protruding outward from each outer peripheral edge of the element, the first electrode plate, and the second electrode plate, and an external connection terminal connected to the control terminal is provided on the protruding portion, and the first power electrode faces the semiconductor element side. In the protruding protruding portion, the insulating substrate further includes an opening or a cutout through which the protruding portion passes.

A second feature of an embodiment of the present invention is that the semiconductor module includes: the semiconductor package of the above-mentioned first feature; and a first conductive member and a second conductive member that are conductive and are provided to sandwich the semiconductor package.

Invention effect

According to the present invention, it is possible to provide a semiconductor package that can be miniaturized by connecting a semiconductor element without using wire bonding, and a semiconductor module including the semiconductor package.

Description of drawings

FIG. 1 is a perspective view showing a semiconductor package according to a first embodiment of the present invention.

FIG. 2 is an exploded perspective view showing the semiconductor package shown in FIG. 1 .

3 is an exploded perspective view showing an insulating substrate and an IGBT element included in the semiconductor package shown in FIG. 1 .

4 is an exploded perspective view showing an insulating substrate and a first electrode plate included in the semiconductor package shown in FIG. 1 .

5 is a perspective view showing an insulating substrate and a first electrode plate included in the semiconductor package shown in FIG. 1 .

6 is a sectional view along line A-A showing the semiconductor package shown in FIG. 1 .

7 is a sectional view along line A-A showing a semiconductor package according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a first step in the manufacturing process of the semiconductor package shown in FIG. 7 .

Fig. 9 is a sectional view of the second step.

10 is an A-A sectional view showing a semiconductor package according to a third embodiment of the present invention.

11 is an A-A sectional view showing a semiconductor package according to a fourth embodiment of the present invention.

12 is an A-A sectional view showing a semiconductor package according to a fifth embodiment of the present invention.

13 is an A-A sectional view showing a semiconductor package according to a sixth embodiment of the present invention.

14 is a side view showing a semiconductor module according to a seventh embodiment of the present invention.

FIG. 15 is a plan view showing the semiconductor module shown in FIG. 14 .

16 is a first step side view illustrating the manufacturing steps of the semiconductor module according to the eighth embodiment of the present invention.

Fig. 17 is a side view of the second step.

18 is a side view showing a semiconductor module according to a ninth embodiment of the present invention.

FIG. 19 is a perspective view showing an example of a conventional semiconductor package of the present invention.

Detailed ways

(first embodiment)

A first embodiment of the present invention will be described with reference to FIGS. 1 to 6 .

As shown in FIGS. 1 and 2 , the semiconductor package 10 is constituted by laminating an IGBT element (semiconductor element) 20 as a power semiconductor element; The electrode plate 30 ; the second electrode plate 40 arranged on the back surface 21 b side facing the front surface of the IGBT element 20 ; and the insulating substrate 50 arranged between the first electrode plate 30 and the IGBT element 20 . The outer peripheral edge of the IGBT element 20 is provided on the inner side of the respective outer peripheral edges of the first electrode plate 30 , the second electrode plate 40 , and the insulating substrate 50 .

As shown in FIGS. 2 and 3 , the IGBT element 20 is one in which an IGBT is mounted on a so-called semiconductor chip 21 which is a plate-like chip. On the surface 21 a of the semiconductor chip 21 , an emitter electrode (first power terminal) 22 , a gate electrode (control terminal) 23 , and an emitter electrode (control terminal) 24 are provided. Around the gate electrode 23 and the radiation sensing electrode 24, a solder resist film 25 for preventing a short circuit due to solder flow is formed by printing. In addition, on the back surface 21b of the semiconductor chip 21, a collector (second power terminal) 26 is provided. In addition, the opening shape of the solder resist film 25 is determined according to the amount of solder used for soldering and the type of soldering (solder ball shape or solder flake shape). When solder balls are used for solder bonding, the shape of the opening is set to be circular, for example.

As shown in FIGS. 2 and 4 , the first electrode plate 30 has a plate-shaped substrate body 31 made of a conductive material such as copper. Copper is used because of its price, electrical conductivity, and thermal conductivity, but it is not limited thereto (other conductive materials will be described later). On the facing surface 31a of the substrate main body 31 on the IGBT element 20 side, there is formed a protrusion (first power electrode) 32 (first power electrode) 32 ( Refer to Figure 4).

As shown in FIG. 2 , the second electrode plate 40 has a plate-shaped substrate main body 41 made of a conductive material such as copper. The opposing surface (second power electrode) 41 a of the substrate main body 41 on the side of the IGBT element 20 is in contact with the collector electrode 26 of the IGBT element 20 , and the second electrode plate 40 is electrically connected to the collector electrode 26 . In addition, the material of the board|substrate main body 41 may be the same material as the board|substrate main body 31, and may be a different material.

As shown in FIGS. 2 , 3 and 4 , the insulating substrate 50 has a plate-shaped substrate main body 51 made of glass epoxy resin, polyimide resin, or the like. The substrate main body 51 is provided with an opening (through opening) 52 having the same planar shape as the protrusion 32 and a slightly larger similar shape through which the protrusion 32 of the first electrode plate 30 passes. The protrusion 32 of the first electrode plate 30 is fitted into the opening 52 . In addition, lead-out portions (protrusions) 51a protruding outward from respective outer peripheral edges of the IGBT element 20 , the first electrode plate 30 , and the second electrode plate 40 are formed on the substrate body 51 (see FIGS. 3 and 4 ). Furthermore, connection pads 51 b are provided on the surface of the substrate main body 51 on the second electrode plate 40 side (IGBT element 20 side) (see FIG. 4 ). Furthermore, on the surface of the substrate main body 51 on the side of the first electrode plate 30, a fixing pad 51c for fixing the first electrode plate 30 is provided (see FIGS. 2 and 3). This fixed pad 51 c is positioned outside the outer peripheral edge of the IGBT element 20 .

On the substrate main body 51 , as shown in FIGS. 3 and 4 , connection pads (control electrodes) 53 and 54 are provided opposite to the gate electrode 23 and the emitter electrode 24 of the IGBT element 20 , respectively. Further, wirings 55 and 56 respectively connected to the connection pads 53 and 54 are provided on the substrate main body 51, and external connection terminals 57 and 58 respectively connected to the wirings 55 and 56 are positioned on the lead-out portion 51a.

In addition, except for the connection portions of the connection pads 53 and 54 and the external connection terminals 57 and 58 , they are covered with a solder resist (not shown) for preventing solder flow. The material and type of the protective film are not particularly limited. The opening shape of the solder resist film is determined according to the amount of solder used for soldering and the type of soldering (solder ball shape or sheet shape). When solder balls are used for solder bonding, the shape of the opening is set to be circular, for example.

Next, the electrical connection structure and bonding structure among these IGBT elements 20 , the first electrode plate 30 , the second electrode plate 40 , and the insulating substrate 50 will be described.

As shown in FIGS. 3 and 4, the emitter electrode 22 of the IGBT element 20 and the protrusion 32 of the first electrode plate 30 are joined by soldering, and as shown in FIG. There is a solder layer 70 . Accordingly, the emitter electrode 22 and the protrusion 32 of the first electrode plate 30 are electrically connected.

In addition, as shown in FIG. 3 , the gate electrode 23 of the IGBT element 20 and the connection pad 54 on the insulating substrate 50 are bonded by soldering with solder balls 60 , forming a gap between the IGBT element 20 and the insulating substrate 50 . There is a solder layer. Thereby, the gate electrode 23 and the connection pad 54 are electrically connected. Similarly, as shown in FIG. 3, the radiation sensing electrode 24 of the IGBT element 20 is bonded to the connection pad 53 on the insulating substrate 50 by soldering the solder ball 60. As shown in FIG. 6, the IGBT element 20 A solder layer 71 is formed between the insulating substrate 50 . Thereby, the emitter electrode 24 and the connection pad 53 are electrically connected.

Furthermore, as shown in FIG. 2, the collector electrode 26 of the IGBT element 20 and the opposing surface 41a of the second electrode plate 40 are joined by soldering, and as shown in FIG. A solder layer 72 is formed between them. Thus, the collector electrode 26 and the second electrode plate 40 are electrically connected.

As shown in FIG. 5 , the second electrode plate 40 and the connection pad 51 b of the insulating substrate 50 are bonded by soldering with solder-coated balls (pads) 61 . The solder coating ball 61 has a function of maintaining a certain space between the second electrode plate 40 and the insulating substrate 50 . The solder-coated balls 61 are disposed on the connection pads 51b, and the surfaces thereof are melted to perform solder bonding of the second electrode plate 40 and the insulating substrate 50. In addition, the solder-coated ball 61 is formed by coating the surface of a core material made of metal or a non-metallic material such as plastic with a metal material, and coating the surface of the thus-produced component with solder. .

As shown in FIG. 2 , the first electrode plate 30 and the fixing pad 51 c of the insulating substrate 50 are bonded by soldering, and the first electrode plate 30 is fixed on the insulating substrate 50 . In addition, the first electrode plate 30 and the second electrode plate 40 are electrically insulated by the insulating substrate 50 . In addition, the fixing pad 51c is made of a material with good wettability with soldering, and is made of the same material as the connection pad 51b in the same manufacturing process so as not to increase the manufacturing process of the insulating substrate 50 .

In this way, according to the semiconductor package 10 of the first embodiment, by disposing the gate electrode 23 and the emitter electrode 24 of the IGBT element 20 and the respective connection pads 53 and 54 of the insulating substrate 50 at positions facing each other, it is possible to solder Bonding connects them without the need for wire bonding. Accordingly, there is no need to secure a bonding space for wire bonding, and it is also unnecessary to secure a separation distance for preventing a short circuit due to the bonding wire, so that the size of the semiconductor package 10 can be reduced. Therefore, the connection to the IGBT element 20 can be performed without using wire bonding, whereby the size of the semiconductor package 10 can be reduced. In addition, since a wiring machine facility for wire bonding is not required, investment in manufacturing equipment and space for production equipment can be reduced.

Furthermore, the insulating substrate 50 has a lead-out portion 51a protruding outward from the respective outer peripheral edges of the IGBT element 20, the first electrode plate 30, and the second electrode plate 40, and the lead-out portion 51a is provided with connections to the connection pads 53, 54. Since the external connection terminals 57 and 58 do not require wire bonding, control wiring can be drawn out of the package.

In addition, the first electrode plate 30 has a protrusion 32 protruding toward the IGBT element 20 side as the first power electrode, and the insulating substrate 50 has an opening 52 through which the protrusion 32 passes, so that the first electrode plate 30 and the first electrode plate 30 can be easily connected. The emitter electrode 22 of the IGBT element 20 is connected.

In addition, the insulating substrate 50 has a fixed land 51c on the surface facing the first electrode plate 30, and the first electrode plate 30 and the fixed land 51c are joined by soldering, so the insulating substrate 50 and the insulating substrate 50 can be bonded with high strength. The first electrode plate 30 is fixed.

In addition, each outer peripheral edge of the second electrode plate 40 and the insulating substrate 50 is set outside the outer peripheral edge of the IGBT element 20, and has, for example, solder coating balls 61 positioned between the second electrode plate 40 and the insulating substrate 50. The distance between the second electrode plate 40 and the insulating substrate 50 is used as a spacer to maintain a constant distance between the second electrode plate 40 and the insulating substrate 50, thereby maintaining the distance between the second electrode plate 40 and the insulating substrate 50. Therefore, damage to the IGBT element 20 due to external impact or the like can be prevented. As a result, component reliability of the semiconductor package 10 can be improved.

Furthermore, the spacer has a metal material on at least the surface, such as a solder-coated ball 61, and is bonded to at least one of the second electrode plate 40 and the insulating substrate 50 by soldering, so the device for soldering can Pad-bonding to at least one of the second electrode plate 40 and the insulating substrate 50 does not require a new device for pad-bonding, thereby reducing investment in manufacturing equipment and space for production equipment.

In addition, as the spacer, if it is difficult to manufacture the solder-coated ball 61, a commercially available ceramic-sealed or resin-sealed electric passive element can be used. For example, chip components such as resistors, capacitors, or inductors can be used as pads. Since the size of the chip components is standardized and it is easy to collect components of the same height, the second electrode plate 40 and the insulating substrate 50 can be bonded with a high degree of parallelism. In addition, a chip component incorporating such an electric passive element has solder-plated electrode portions at both ends. Since the electrode portion can be used to perform soldering to the substrate, assembly is easy. At this time, the chip component incorporating the electrically passive element used as the spacer does not need to be used as a part of the circuit of the semiconductor device of the present embodiment.

In addition, the present invention is not limited to the above-mentioned embodiments. For example, in the above-mentioned embodiment, the material of the first electrode plate 30 and the second electrode plate 40 is copper, but it is not limited to this, as long as it is a conductive material, from the viewpoint of formability, specific gravity, and thermal expansion coefficient, etc. Starting from, aluminum, molybdenum, copper-molybdenum alloy, and copper-tungsten alloy can also be used. Furthermore, the material of the first electrode plate 30 and the second electrode plate 40 may be a clad material (clad) of various materials, and the surfaces may be plated with other materials in order to improve the wettability of the solder joint.

In addition, the protrusions 32 of the first electrode plate 30 are formed by press embossing, but it is not limited thereto. to form.

In addition, various solder materials such as common Sn—Pb eutectic solder, lead-free solder, and Pb-rich high-temperature solder may be used as the solder material used for soldering. In addition, as the solder supplied between the collector electrode 26 and the second electrode plate 40 and between the emitter electrode 22 and the first electrode plate 30, a solder sheet cut into a predetermined size or a solder paste printed by a printing method can be used. , Solder formed into a film by plating or vapor deposition, etc. Furthermore, as the solder supplied between the gate electrode 23 and the radiation sensing electrode 24 and the respective connection pads 53, 54, solder balls, solder paste printed by printing, solder paste supplied by dispensing, etc. may be used. But the use of solder balls is the easiest and preferred.

In addition, as the insulating substrate 50 , when fixing to the first electrode plate 30 by soldering, two boards are used, and when fixing to the first electrode plate 30 only by bonding or mechanical fixing, a single board can be used. Furthermore, as the insulating substrate 50, a flexible substrate or a flexible substrate can be used, and in particular, when heat resistance is required, a BT resin imide (BT resin.imide) substrate or the like can be used.

In addition, the opening 52 through which the protrusion 32 passes is provided on the insulating substrate 50 , but the present invention is not limited to this, and for example, a cutout through which the protrusion 32 passes may be provided.

(second embodiment)

A second embodiment of the present invention will be described with reference to FIGS. 7 to 9 .

The second embodiment of the present invention is basically the same as the first embodiment, and in the second embodiment, the parts different from the first embodiment will be described. In addition, in the second embodiment, the same parts as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted (the same applies to other embodiments).

The difference between the second embodiment and the first embodiment is that, as shown in FIG. The solder bonding of the electrode plate 30 , the solder bonding of the IGBT element 20 and the insulating substrate 50 , and the solder bonding of the IGBT element 20 and the second electrode plate 40 are diffusion bonding.

Here, diffusion bonding is a bonding method in which materials are heated to a temperature equal to or lower than the melting point, brought into close contact under pressure, and bonded in a solid state by interdiffusion of mutual atoms. In addition, since the opposing surface 31a of the first electrode plate 30 on the side of the IGBT element 20 is flat, the first electrode plate 30 does not have the structure of the protrusion 32 shown in FIG. 4 described above.

The emitter electrode 22 on the IGBT element 20 and the opposing surface 31a of the first electrode plate 30 are joined by diffusion bonding by brazing (refer to FIG. 2 ). A solder layer 70 is formed between the boards 40 . Thus, the emitter electrode 22 is electrically connected to the first electrode plate 30 .

In addition, the gate electrode 23 on the IGBT element 20 and the connection pad 54 on the insulating substrate 50 are joined by diffusion bonding by soldering (see FIG. 3 ), and a solder joint is formed between the IGBT element 20 and the insulating substrate 50. layer. Thereby, the gate electrode 23 and the connection pad 54 are electrically connected. Similarly, the radiation-sensitive electrode 24 on the IGBT element 20 and the connection pad 53 on the insulating substrate 50 are joined by diffusion bonding (refer to FIG. 3 ) by soldering. As shown in FIG. A solder layer 71 is formed between the substrates 50 . Thereby, the emitter electrode 24 is electrically connected to the connection pad 53 .

Furthermore, the collector electrode 26 of the IGBT element 20 and the opposing surface 41a of the second electrode plate 40 are joined by diffusion bonding by brazing (see FIG. 2 ). A solder layer 72 is formed between the electrode plates 40 . Thus, the collector electrode 26 is electrically connected to the second electrode plate 40 .

Next, an assembly process of the semiconductor package 10 will be described.

First, as shown in FIG. 8 , the solder sheet 72 a is placed on the second electrode plate 40 , and the IGBT element 20 is placed on the solder sheet 72 a. In addition, the solder flakes 72a are formed of Sn-based solder, and are placed on the opposing surface 41a of the second electrode plate 40 and the collector electrode 26 (refer to FIG. Instead, Ni/Au plating is implemented. Set the laminated second electrode plate 40 and IGBT element 20 in a decompression extrusion machine, and perform decompression extrusion under predetermined conditions (such as extrusion pressure of 4MPa, temperature of 210°C, decompression less than or equal to 10Torr) . This condition is set according to the solder composition of the solder flake 72a to be used, and the like. In addition, in the second embodiment, for example, the extrusion pressure is set in the range of 0.5 MPa to 10 MPa, the temperature in the range of 150° C. to 300° C., and the pressure reduction is set in the range of 50 Torr or less. Pressing under reduced pressure diffuses Au on the opposing surface 41 a of the second electrode plate 40 and on the collector electrode 26 of the IGBT element 20 , and Ni and Sn diffuse and react. Thereby, the opposing surface 41a of the second electrode plate 40 is bonded to the collector electrode 26 of the IGBT element 20 (see FIG. 2 ).

Next, as shown in FIG. 9, the insulating substrate 50 is placed on the first electrode plate 30, the solder sheet 70a is inserted into the opening 52 of the insulating substrate 50, and the gate electrode 23 of the IGBT element 20 (see FIG. 3) A small piece of solder flake 71a of the same size is placed on the connection pad 53 (see FIG. 3 ) of the insulating substrate 50, and a small piece of the same size as the radiation-sensitive electrode 24 of the IGBT element 20 (see FIG. 3 ) Shaped solder flakes 71a are placed on the connection pads 53 (see FIG. 3 ) of the insulating substrate 50 . In addition, the solder flake 70 a is thicker than the thickness of the insulating substrate 50 , and the solder flake 71 a is a thin flake having the same thickness as the difference between the thickness of the solder flake 70 a and the insulating substrate 50 . In addition, the solder flakes 70a, 71a are formed by Sn-based solder, and are placed on the opposing surface 31a of the first electrode plate 30, and further on the emitter electrode 22, the gate electrode 23, and the emitter electrode 21a of the surface 21a of the IGBT element 20. On each electrode of 24, Ni/Au plating is implemented in order to improve wettability with solder.

Then, the bonded IGBT element 20 and second electrode plate 40 are placed on the insulating substrate 50 via the solder sheet 70 a and the solder sheet 71 a so that the IGBT element 20 and the insulating substrate 50 face each other. At this time, positioning is performed so that the solder sheet 70a faces the emitter electrode 22 of the IGBT element 20 and the solder sheet 71a faces the gate electrode 23 and the emitter electrode 24 of the IGBT element 20 (see FIG. 3 ). The laminated IGBT element 20 , first electrode plate 30 , second electrode plate 40 , and insulating substrate 50 were set in a pressure-reducing extrusion machine, and pressure-reducing extrusion was performed under the same conditions as above. Pressing under reduced pressure diffuses Au on the opposing surface 31 a of the first electrode plate 30 and on each electrode of the IGBT element 20 , and Ni and Sn diffuse and react. Thus, the opposing surface 31a of the first electrode plate 30 is bonded to the emitter electrode 22 of the IGBT element 20, and the connection pads 53, 54 of the insulating substrate 50 are respectively bonded to the gate electrode 23 and the emitter electrode 24 of the IGBT element 20 ( Refer to Figure 3). In this way, the semiconductor package 10 as shown in FIG. 7 is completed.

In this way, according to the semiconductor package 10 of the second embodiment, by making the solder bonding between the electrodes to be diffusion bonding, melting of the solder can be prevented, and the thickness of the solder layers 70, 71, 72 can be controlled, so that the semiconductor package 10 can be maintained. The parallelism between the first electrode plate 30 and the second electrode plate 40 can also make the thickness of the semiconductor package 10 constant. As a result, when a plurality of semiconductor packages 10 are combined and modularized, it is possible to prevent unevenness in parallelism between the first electrode plate 30 and the second electrode plate 40 included in each semiconductor package 10 and the unevenness of each semiconductor package 10. 10, such as uneven thickness, etc., to manufacture semiconductor modules.

(third embodiment)

A third embodiment of the present invention will be described with reference to FIG. 10 .

The third embodiment of the present invention is basically the same as the second embodiment, and the difference between the third embodiment and the second embodiment will be described.

The difference between the third embodiment and the second embodiment is that, as shown in FIG. 20.

The resin portion 80 is provided around the IGBT element 20 by filling resin into the space between the first electrode plate 30 and the second electrode plate 40 . Thereby, the first electrode plate 30 and the second electrode plate 40 are fixedly bonded, and the periphery of the IGBT element 20 is covered with the resin portion 80 .

In this way, according to the semiconductor package 10 of the third embodiment, by providing the resin portion 80 in the space between the first electrode plate 30 and the second electrode plate 40, the mechanical strength of the semiconductor package 10 is improved, so it is possible to prevent the Damage to the IGBT element 20 caused by impact or the like. As a result, component reliability of the semiconductor package 10 can be improved.

(fourth embodiment)

A fourth embodiment of the present invention will be described with reference to FIG. 11 .

The fourth embodiment of the present invention is basically the same as the first embodiment, and the difference between the fourth embodiment and the first embodiment will be described.

The difference between the fourth embodiment and the first embodiment is that, as shown in FIG. 40 includes a stress relaxation layer 86 having stress relaxation properties and conductivity.

The stress relaxation layer 85 is provided on the substrate body 31 as the protrusion 32 on the substrate body 31 of the first electrode plate 30, and is sandwiched between the protrusion bodies 32a, 32b as an intermediate layer. The protrusion main body 32a is joined to the substrate main body 31 by soldering. Thereby, the solder layer 73 is formed between the protrusion main body 32 a and the substrate main body 31 . In addition, the stress relaxation layer 86 is provided as an intermediate layer in the substrate main body 41 of the second electrode plate 40 .

The stress relaxation layers 85 and 86 are formed of an electrically conductive material such as copper. In addition, the stress relaxation layers 85 and 86 have a cross-sectional mesh shape by providing wires in a mesh shape, but the present invention is not limited thereto. The stress relaxation layers 85 and 86 gently (softly) relax stress.

In this way, according to the semiconductor package 10 of the fourth embodiment, since the stress can be relaxed by providing the stress relaxation layers 85 and 86 , damage to the IGBT element 20 due to the stress can be prevented. As a result, component reliability of the semiconductor package 10 can be improved.

In addition, in the manufacturing process of the semiconductor package 10 , as shown in FIGS. 8 and 9 , even when an external force or the like is applied, damage to the IGBT element 20 due to the external force can be prevented. As a result, reduction in manufacturing yield when manufacturing the semiconductor package 10 can be suppressed.

Furthermore, when a plurality of semiconductor packages 10 are combined to form a module, it is also possible to prevent damage to the semiconductor package 10 caused by an external force applied to the semiconductor package 10 in the manufacturing process of the semiconductor module, especially to prevent the IGBT element 20 from being damaged. damage. As a result, it is possible to suppress a decrease in manufacturing yield when manufacturing a semiconductor module.

In addition, since the stress relaxation layers 85 and 86 are formed in a cross-sectional mesh shape, stress can be gently relaxed with a simple structure.

(fifth embodiment)

A fifth embodiment of the present invention will be described with reference to FIG. 12 .

5th Embodiment of this invention is basically the same as 1st Embodiment, and the part which differs from 1st Embodiment in 5th Embodiment is demonstrated.

The fifth embodiment differs from the first embodiment in that, as shown in FIG. 12 , the first electrode plate 30 has a stress relieving layer 85 having stress relieving properties and conductivity, and the second electrode plate 40 has a stress relieving layer 85 having stress relieving properties and electrical conductivity. Conductive stress relief layer 86 .

The stress relaxation layer 85 is provided as an intermediate layer in the substrate main body 31 of the first electrode plate 30 and functions as the protrusion 32 on the substrate main body 31 . In addition, the stress relaxation layer 86 is provided as an intermediate layer in the substrate main body 41 of the second electrode plate 40 .

The stress relaxation layers 85 and 86 are formed of an electrically conductive material such as copper. In addition, the stress relaxation layers 85 and 86 have a cross-sectional mesh shape by providing wires in a mesh shape, but the present invention is not limited thereto. The stress relaxation layers 85 and 86 gently (softly) relax stress.

In this way, according to the semiconductor package 10 of the fifth embodiment, since the stress can be relaxed by providing the stress relaxation layers 85 and 86 , damage to the IGBT element 20 due to the stress can be prevented. As a result, component reliability of the semiconductor package 10 can be improved.

In addition, in the manufacturing process of the semiconductor package 10 , as shown in FIGS. 8 and 9 , even when an external force or the like is applied, damage to the IGBT element 20 due to the external force can be prevented. As a result, reduction in manufacturing yield when manufacturing the semiconductor package 10 can be suppressed.

Furthermore, when a plurality of semiconductor packages 10 are combined to form a module, damage to the semiconductor package 10 caused by an external force applied to the semiconductor package 10 in the manufacturing process of the semiconductor module can be prevented, especially damage to the IGBT element 20 can be prevented. damage. As a result, it is possible to suppress a decrease in manufacturing yield when manufacturing a semiconductor module.

(sixth embodiment)

A sixth embodiment of the present invention will be described with reference to FIG. 13 .

The sixth embodiment of the present invention is basically the same as the first embodiment, and the differences between the sixth embodiment and the first embodiment will be described.

The sixth embodiment differs from the first embodiment in that, as shown in FIG. A stress relaxation layer 88 having stress relaxation properties and conductivity is provided between the second electrode plate 40 .

The stress relaxation layer 87 is provided on the substrate body 31 as the protrusion 32 on the substrate body 31 of the first electrode plate 30, and is sandwiched between the protrusion bodies 32a, 32b as an intermediate layer. The protrusion main body 32a is joined to the substrate main body 31 by soldering. Thereby, the solder layer 73 is formed between the protrusion main body 32 a and the substrate main body 31 .

In addition, a stress relieving layer 88 is provided as an intermediate layer in the stress relieving electrode 41b. The stress relaxation electrode 41b is joined between the IGBT element 20 and the second electrode plate 40 by soldering. Thus, the solder layer 72 is formed between the IGBT element 20 and the stress relieving electrode 41b, and the solder layer 74 is formed between the second electrode plate 40 and the stress relieving electrode 41b.

The stress relaxation layers 87 and 88 are formed of an electrically conductive material such as copper. In addition, the stress relaxation layers 87 and 88 are formed as thin copper wire tapes by weaving thin copper wires like cloth, but the present invention is not limited thereto. The stress relaxation layers 87 and 88 gently (softly) relax stress, in particular stress caused by thermal expansion of the IGBT element 20 , the first electrode plate 30 , and the second electrode plate 40 .

In this way, according to the semiconductor package 10 according to the sixth embodiment, since the stress can be relaxed by providing the stress relaxation layers 87 and 88 , damage to the IGBT element 20 due to the stress can be prevented. As a result, component reliability of the semiconductor package 10 can be improved.

In addition, in the manufacturing process of the semiconductor package 10 , as shown in FIGS. 8 and 9 , even when an external force or the like is applied, damage to the IGBT element 20 due to the external force can be prevented. As a result, reduction in manufacturing yield when manufacturing the semiconductor package 10 can be suppressed.

Furthermore, when a plurality of semiconductor packages 10 are combined to form a module, damage to the semiconductor package 10 caused by an external force applied to the semiconductor package 10 in the manufacturing process of the semiconductor module can be prevented, especially damage to the IGBT element 20 can be prevented. damage. As a result, it is possible to suppress a decrease in manufacturing yield when manufacturing a semiconductor module.

(seventh embodiment)

A seventh embodiment of the present invention will be described with reference to FIGS. 14 and 15 . In addition, in the seventh embodiment, an example of the semiconductor module 11 including the semiconductor package 10 in any one of the above-mentioned first to sixth embodiments will be described.

As shown in FIG. 14 and FIG. 15 , the semiconductor module 11 of the seventh embodiment includes: the semiconductor package 10 of any one of the first to sixth embodiments; a plurality of FRD elements (high-speed rectifier elements) 12; The conductive member 91 and the second conductive member 92 have conductivity and are arranged to sandwich each semiconductor package 10 and each FRD element 12; the heat dissipation plate 94, the first conductive member 91 and the second conductive member 92 pass through an insulating sheet or an insulating plate and other insulators 93 are provided.

The semiconductor package 10 and the conductive members 91 , 92 are joined by soldering, and the semiconductor package 10 and the conductive members 91 , 92 are electrically connected. In addition, the FRD element 12 and the conductive members 91 and 92 are joined by soldering, and the FRD element 12 and the conductive members 91 and 92 are electrically connected. Thus, the solder layer 75 is formed between the semiconductor package 10 and the conductive members 91 and 92 , and the solder layer 75 is also formed between the FRD element 12 and the conductive members 91 and 92 . Here, brazing joining is fusion joining.

The conductive members 91 and 92 have electrical conductivity and function as common electrode members for each semiconductor package 10 and each FRD element 12 , and also have thermal conductivity and function as a heat dissipation member. Here, the first conductive member 91 is connected to the first electrode pad 30 (see FIG. 1 ) of the semiconductor package 10 and functions as an emitter region. In addition, the second conductive member 92 is connected to the second electrode pad 40 (see FIG. 1 ) of the semiconductor package 10 and functions as a collector region.

Thus, according to the semiconductor module 11 of the seventh embodiment, the same effect as that obtained by the semiconductor package 10 of any one of the first to sixth embodiments can be obtained.

(eighth embodiment)

An eighth embodiment of the present invention will be described with reference to FIGS. 16 and 17 .

The eighth embodiment of the present invention is basically the same as the seventh embodiment, and in the eighth embodiment, differences from the seventh embodiment will be described.

The eighth embodiment differs from the seventh embodiment in that in the semiconductor module 11 , the solder bonding for forming the solder layer 75 is diffusion bonding.

Here, an assembly process of the semiconductor module 11 will be described.

First, as shown in FIG. 16, a plurality of semiconductor packages 10 and a plurality of FRD elements 12 are placed on the second conductive member 92 through the solder sheet 75a, and then the first conductive member 91 is placed on each semiconductor package through the solder sheet 75a. package 10 and each FRD component 12 . The laminated first conductive member 91, semiconductor package 10, FRD element 12, and second conductive member 92 are placed in a decompression extruder, and are placed under predetermined conditions (for example, the extrusion pressure is 4 MPa and the temperature is 210° C. , pressure reduction is less than or equal to 10Torr) under reduced pressure extrusion. This condition is set according to the solder composition and the like of the solder sheet 75a to be used. In addition, in the sixth embodiment, for example, the extrusion pressure is set in the range of 0.5 MPa to 10 MPa, the temperature in the range of 150° C. to 300° C., and the pressurization is set in the range of 50 Torr or less. Each semiconductor package 10 and each FRD element 12 are bonded to the conductive members 91 and 92 by diffusion bonding by reduced pressure pressing.

Next, as shown in FIG. 17 , the respective conductive members 91 and 92 sandwiching the semiconductor package 10 and the FRD element 12 are placed on a heat sink 94 via an insulator 93 . The heat dissipation plates 94 in the laminated state are set in a heating extruder, and heated and extruded under predetermined conditions. The respective conductive members 91 , 92 are bonded to the heat sink 94 by melting the insulator 93 by heating and pressing. Thus, the semiconductor module 11 as shown in FIGS. 14 and 15 is completed.

Thus, according to the semiconductor module 11 of the eighth embodiment, the same effect as that obtained by the semiconductor package 10 of any one of the first to sixth embodiments can be obtained. Furthermore, by joining the semiconductor package 10 and the conductive members 91, 92 by soldering diffusion bonding, melting of the solder can be prevented, and it is possible to prevent the solder Damage to the semiconductor package 10 caused by solidification and shrinkage, especially damage to the IGBT element 20 can be prevented. As a result, it is possible to suppress a reduction in manufacturing yield when manufacturing the semiconductor module 11 .

(ninth embodiment)

A ninth embodiment of the present invention will be described with reference to FIG. 18 .

The ninth embodiment of the present invention is basically the same as the seventh or eighth embodiment, and in the ninth embodiment, the parts different from the seventh or eighth embodiment will be described.

The difference between the ninth embodiment and the seventh or eighth embodiment is that, as shown in FIG. The resin part 81.

The resin portion 81 is provided around each semiconductor package 10 and each FRD element 12 (see FIG. 15 ) by filling the space between the first conductive member 91 and the second conductive member 92 with resin. Thereby, the first conductive member 91 and the second conductive member 92 are fixedly bonded, and the surroundings of each semiconductor package 10 and each FRD element 12 are covered with the resin portion 81 . In addition, the resin is filled between the first conductive member 91 and the second conductive member 92 after the semiconductor package 10 is bonded to the conductive members 91 and 92 (see FIG. 16 ) and before heat pressing (see FIG. 17 ). in the space between.

In this way, according to the semiconductor module 11 of the ninth embodiment, by providing the resin portion 81 in the space between the first conductive member 91 and the second conductive member 92, the mechanical strength of the semiconductor module 11 is improved, so it is possible to prevent the damage to the semiconductor package 10 due to impacts or the like, and in particular damage to the IGBT element 20 can be prevented. As a result, component reliability of the semiconductor module 11 can be improved.

In particular, the resin portion 81 is provided between the first conductive member 91 and the second conductive member 92 before the bonded semiconductor package 10 and the conductive members 91 and 92 are placed on the heat sink 94 and heated and pressed. Therefore, it is possible to prevent damage to the semiconductor package 10 , particularly to the IGBT element 20 , due to heating and pressing. . As a result, it is possible to suppress a reduction in manufacturing yield when manufacturing the semiconductor module 11 .

Finally, the present invention is not limited to the above-described embodiments, and it goes without saying that various changes can be made without departing from the gist thereof. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements shown in the above-mentioned embodiments. For example, some constituent elements may be excluded from all the constituent elements described in the above-mentioned embodiments. Furthermore, constituent elements of different embodiments may be appropriately combined.

Claims (14)

1. semiconductor packages is characterized in that having:

Tabular semiconductor element has the 1st power terminal and control terminal on interarea, with the opposed back side of above-mentioned interarea on have the 2nd power terminal;

The 1st battery lead plate with the above-mentioned interarea opposite disposed of above-mentioned semiconductor element, has the 1st electric power electrode that is connected with above-mentioned the 1st power terminal by soldered joint;

The 2nd battery lead plate with the above-mentioned back side opposite disposed of above-mentioned semiconductor element, has the 2nd electric power electrode that is connected with above-mentioned the 2nd power terminal by soldered joint; And

Insulated substrate, be located between above-mentioned semiconductor element and above-mentioned the 1st battery lead plate, have control electrode that is connected with above-mentioned control terminal by soldered joint and the protuberance of giving prominence to laterally from each outer peripheral edges of above-mentioned semiconductor element, above-mentioned the 1st battery lead plate and the 2nd battery lead plate, on this protuberance, possesses the external connection terminals that is connected with above-mentioned control terminal

Above-mentioned the 1st electric power electrode is the jut to above-mentioned semiconductor element side projection,

Above-mentioned insulated substrate also possesses peristome or the notch that above-mentioned jut passes.

2. semiconductor packages as claimed in claim 1 is characterized in that,

Above-mentioned insulated substrate with the opposed surface of above-mentioned the 1st battery lead plate on have anchor pad, above-mentioned the 1st battery lead plate engages by soldered joint with the said fixing pad.

3. semiconductor packages as claimed in claim 1 is characterized in that, each outer peripheral edges of above-mentioned the 2nd battery lead plate and above-mentioned insulated substrate are located at than the outer peripheral edges of above-mentioned semiconductor element in the outer part; Have liner between above-mentioned the 2nd battery lead plate and above-mentioned insulated substrate, this liner location is arranged on than each outer peripheral edges of above-mentioned semiconductor element in the outer part, and the spacing distance between above-mentioned the 2nd battery lead plate and the above-mentioned insulated substrate is remained necessarily.

4. semiconductor packages as claimed in claim 3 is characterized in that above-mentioned liner has metal material from the teeth outwards, engages with in above-mentioned the 2nd battery lead plate and the above-mentioned insulated substrate at least one by soldered joint.

5. semiconductor packages as claimed in claim 3 is characterized in that, above-mentioned liner is equipped with the chip part of electric electric passive component in being.

6. semiconductor packages as claimed in claim 1 is characterized in that, above-mentioned soldered joint is a diffusion bond.

7. semiconductor packages as claimed in claim 1 is characterized in that, also has the resin portion of surrounding above-mentioned semiconductor element and being provided with between above-mentioned the 1st battery lead plate and above-mentioned the 2nd battery lead plate.

8. semiconductor packages as claimed in claim 1 is characterized in that, also possesses the stress relaxation layer with stress relaxation properties and conductivity.

9. semiconductor packages as claimed in claim 1 is characterized in that, above-mentioned the 1st battery lead plate possesses the stress relaxation layer with stress relaxation properties and conductivity.

10. semiconductor packages as claimed in claim 1 is characterized in that, above-mentioned the 2nd battery lead plate possesses the stress relaxation layer with stress relaxation properties and conductivity.

11., it is characterized in that above-mentioned stress relaxation layer forms the section mesh-shape as each described semiconductor packages in the claim 8 to 10.

12. a semiconductor module is characterized in that having:

Each described semiconductor packages in the claim 1 to 11; And

The 1st conductive component and the 2nd conductive component have conductivity, respectively the above-mentioned semiconductor packages of clamping and being provided with.

13. as claim 12 semiconductor module, it is characterized in that,

Above-mentioned semiconductor packages is connected by soldered joint with above-mentioned the 1st conductive component;

Above-mentioned semiconductor packages is connected by soldered joint with above-mentioned the 2nd conductive component;

Above-mentioned soldered joint is a diffusion bond.

14., it is characterized in that between above-mentioned the 1st conductive component and above-mentioned the 2nd conductive component, also having the resin portion of surrounding above-mentioned semiconductor packages and being provided with as claim 12 semiconductor module.

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