CN100417950C - Method for constructing two-stage scan test structure with low test power consumption - Google Patents

Abstract

The present invention relates to a method for constructing a two-stage scan test structure with low test power dissipation, which belongs to the technical field of integrated circuit test. The present invention is characterized in that firstly, a circuit network monofile is used for obtaining a table used for distinguishing the existence of common combination successors between every two time sequence units; the time sequence units are divided into groups according to the table, and the size of the group is regulated in order that the groups are uniform; all the time sequence units are reformed into scan time sequence units through a method of adding multiway selectors before the time sequence units; one scan time sequence unit is selected from each group to form a scan chain connected to a clock signal clk 1, the rest scan time sequence units are divided into sub groups, each sub group is respectively driven by one scan time sequence unit arranged in the scan chain, and the sub groups are connected to a clock signal clk 2. When the method is used, the test power dissipation can be reduced to a large degree under the conditions of basic constant fault coverage and test vector and no increase of difficult test fault numbers.

Description

Method for constructing two-stage scan test structure with low test power consumption

technical field

The invention belongs to the technical field of integrated circuit testability design

Background technique

First, introduce background knowledge and related definitions:

Combination gate: The value of the output signal line of the gate has nothing to do with the clock signal. Such a gate is called a combination gate. The types of combination gates include NOT gate, AND gate, OR gate, NAND gate, NOR gate, XOR gate, XOR gate NOR gates etc.

Sequential gate: The value of the output signal line of the gate is related to the clock signal. Such a gate is called a sequential gate, also known as a sequential unit. The input of the timing gate has a logic input and a clock input, and the output is a logic output. Usually, when the rising edge or falling edge of the clock input signal arrives, the value of the logic input signal is read in, thereby generating the value of the corresponding logic output signal.

Combination successor: In the circuit structure, the output signal line of a combination gate is the combination successor of the input signal line of the combination gate. Composite successor relations can be iterated over. For example, in Figure 1, d is the combined successor of a, e is the combined successor of d, and e is also the combined successor of a.

Direct Combined Successor: Adjacent combined successors are called direct combined successors. For example, in Figure 1, d is the direct combined successor of a, but e is not the direct combined successor of a.

Common combined successor: For example, in Figure 1, e is the combined successor of a, and e is also the combined successor of c, then a and c have a common combined successor e.

Testing: A method of testing chip quality after chip packaging. Since the internal circuit of the chip cannot be directly accessed after the chip is packaged, the method adopted for testing the chip is to insert test vectors at the input end of the chip and collect test responses at the output end of the chip. Compare the actual test response with the test response of the fault-free circuit to determine whether the chip circuit is faulty or not.

Test generation problem: For a possible fault in the circuit, find a test vector that can detect the fault, this problem is called the test generation problem.

Scan test: Scan test is a method to design the circuit for testability in order to reduce the complexity of sequential circuit test generation problems. In this method, the sequential circuit is divided into two parts, the sequential unit and the combinatorial logic, as shown in Figure 2, and then a multiplexer is added to transform the sequential unit into a scanning sequential unit, and multiple scanning sequential units are connected end to end to form a scan chain, consisting of a The scan input scan-in is driven and finally connected to a scan output scan-out, as shown in Figure 3. When the signal test is 0, the multiplexer gates the combination logic, which is in the normal working state; when the signal test is 1, the multiplexer gates the scan chain, and the circuit enters the scan test state.

Scanning sequential unit: the sequential unit modified by scanning and testing, such as the structure composed of the multiplexer and the sequential unit in Figure 3 .

Scan chain (scan chain): A scan test structure composed of multiple scan timing units connected end to end (Figure 4). The length of the scan chain is the number of scan sequential units included in the scan chain.

Test power consumption: The test power consumption generated when testing the circuit is mainly caused by the inversion of the logic value of the signal line inside the circuit (logic 1->logic 0, logic 0->logic 1). In the scan test structure, the test power consumption is mainly generated during the insertion of the test vector and the removal of the test response, and the inversion of the logic value of the sequential unit of the circuit and its subsequent combination unit occurs.

In the past, the methods to reduce the power consumption of scan test mainly include: (1) sorting the test vectors; (2) sorting the sequential units; (3) adding control logic behind the sequential units so that during the test vector insertion process, The inversion of the value only occurs in the sequential unit, and will not be propagated to the subsequent combinational logic; (4) encode and decode the test vector; (5) introduce an additional logic structure, so that the logic inversion only occurs in part of the timing when the test vector is placed in the unit.

Method (1)(2)(5) only reduces the test power consumption, but does not reduce the test time. The additional logic introduced by method (3)(5) brings a certain area overhead and reduces the circuit performance. Method (4) ) is mainly aimed at the problem of data volume, which can reduce power consumption while data is compressed.

Contents of the invention

The invention adopts a two-level scanning test structure, and divides the scanning sequence units into different clock domains. The scanning sequential unit of the first stage constitutes a traditional scan chain structure, and its clock input signal is clk ₁ . The scanning sequential units of the second stage are divided into multiple groups, the clock input signal of which is clk ₂ , and the logic input of each scanning sequential unit group is connected to the logic output of one scanning sequential unit in the first stage.

Let the scanning sequential unit group G _i in the second stage include scanning sequential units g ₁ 'g ₂ '...g _n ', and the logic input of each scanning sequential unit in G _i is connected to the scanning sequential unit f in the first level _i ' logic output, then the sequential unit g ₁ g ₂ ...g _{n f i} corresponding to the sequential unit g ₁ 'g ₂ '...g _{n '} f _{i '} should meet the following conditions: any two Sequential cells do not have the same combined successor in the circuit structure.

When placing a test vector, first place the corresponding test vector into the scan chain through the scan input terminal, and set the length of the scan chain as l, then it takes l clk to place a test vector into the first-level scan chain ₁ clock cycle, since the scan timing units of the first level and the second level are controlled by different clock input signals, the scan timing units of the second level do not flip during this process. Next, put the logic output values of each scanning sequential unit in the first level into the corresponding scanning sequential unit group of the second level, which requires a clock cycle of clk ₂ , and the scanning sequential units of the first level do not flip during this process .

According to the information of the circuit structure, after the sequential units are grouped, most of the sequential units can be divided into the second level. In the process of putting the test vector into the scan chain, only the scan sequential unit in the first-level scan chain is flipped, and the number of flips is greatly reduced; while the test vector is placed in the scan sequential unit of the second stage, only one The clock cycle and the number of flips are also greatly reduced, thereby reducing the power consumption of the scan test.

The present invention is characterized in that: it contains following steps successively:

Step 1: conv[N][N] is defined as a successor relationship table to record whether there is a common combined successor in the circuit structure between two sequential units. successor_of_iOut[] is defined as the combined successor list of sequential unit i to record all combined successors of the sequential unit in the circuit. successor_of_jOut[] is defined as the combined successor list of sequential unit j to record all combined successors of the sequential unit in the circuit. Initialize, input the circuit net list file to the computer, and use the N*N form conv[N][N] to record the relationship between sequential units in the circuit structure, where N is the total number of sequential units; if for i≠j, i∈ [1, N], sequential unit i and sequential unit j of j∈[1, N], sequential unit i and sequential unit j have a common combined successor in the circuit structure, then conv[i][j]=conv[j ][i]=1, otherwise conv[i][j]=conv[j][i]=0;

Step 1.1: Create conv[N][N] table;

Step 1.1.1: For all sequential units in the circuit, set the corresponding identification of the output signal line of sequential unit i in the circuit as iOut, and store the combination of sequential unit i into the array successor_of_iOut[] successively, the method is as follows: first Store the direct combination successor i ₁ i ₂ ...i _{n of} sequential unit i into the array, and then store the direct combination successor of i ₁ i ₂ ...i _n in the array in turn until the unit stored in the array is already a sequence unit or raw output;

Step 1.1.2: For any two sequential units i and j, if there are identical units in successor_of_iOut[] and successor_of_jOut[], then conv[i][j]=conv[j][i]=1; otherwise conv [i][j]=conv[j][i]=0;

Step 2: Group sequential units according to the N*N table conv[N][N];

Step 2.1: Let the set of sequential units be F, and each group be G ₁ G ₂ ...G _n ;

Step 2.2: If F is not empty, execute step 2.3, otherwise execute step 2.4;

Step 2.3: Establish a new group Gm, m ∈ [1, n], randomly take a sequential unit g in F and put it into G _m , traverse the remaining sequential units in F, if a certain sequential unit f satisfies $\∀g\∈G_m,$ conv[f][g]=0, then put f into G _m , update F and G _m , and continue to traverse the remaining sequential units in F; after the traversal, go to step 2.2;

Step 2.4: end of grouping;

Step 3: In order to make the grouping uniform, adjust the grouping results obtained in step 2;

Step 3.1: Select the largest group G _max and the smallest group G _min from G ₁ G ₂ ...G _n , G _max is the group with the largest number of sequential units, and G _min is the group with the smallest number of sequential units;

Step 3.2: Select satisfying conditions from G _max $\∀g\∈G_{\min },$ Conv[f][g]=0 sequential unit f, put f into G _min , update G _max and G _min ;

Step 3.3: Repeat step 3.1 and step 3.2 until the difference between G _max and G _min is 1 or the condition cannot be found in G _max $\∀g\∈G_{\min },$ Conv[f][g]=0 sequential unit f;

Step 4: Construct a two-stage scan test structure with low test power consumption according to the adjusted grouping results G ₁ G ₂ ...G _n ;

Step 4.1: add a multiplexer MUX before each sequential unit, and transform it into a scanning sequential unit;

Step 4.2: Select a scanning sequential unit g ₁ 'g ₂ '...g _n ' from G ₁ G ₂ ...G _n to form a scan chain, and scan sequential units g ₁ 'g ₂ '...g _n ' The clock input is connected to the clock signal _clk1 ;

Step 4.3: the clock inputs of the remaining scanning sequential units in G ₁ G ₂ ...G _n are connected to the clock signal clk ₂ ;

Step 4.4: Connect the logic input of the remaining scan sequential cells in _G1 to the logic output of scan sequential cell _g1 ' and the logic input of the remaining scan sequential cells in _G2 to the logic of scan sequential cell _g2 ' output, and so on, connecting the logic inputs of the remaining scan sequential cells in G _n to the logical outputs of the scan sequential cells g _n ';

Step 4.5: As shown in Figure 5, the clock signals clk ₁ and clk ₂ are generated by one clock signal clk plus two control signals C ₁ and C ₂ through two AND gates; connect the clock signal clk to the two inputs respectively The input terminals of AND gates AND ₁ and AND ₂ , the control signals C ₁ and C ₂ are respectively connected to the other input terminals of AND ₁ and AND ₂ , clk ₁ and clk ₂ are the outputs of AND ₁ and AND ₂ respectively; when C ₁ =1 and C ₂ =0, clk ₁ is valid and clk ₂ is invalid; when C ₁ =0 and C ₂ =1, clk ₁ is invalid and clk ₂ is valid. (Figure 5)

Proof of use:

The experimental platform is SUN BLADE2000 workstation, the test code generator used in the experiment is ATALANTA, and the fault simulator is HOPE. Table 1 shows the experimental results of applying the present invention to a part of ISCAS89 and ITC99 circuits. In the table, Full Scan is the experimental result of single-chain complete scanning, Two Stage Scan is the experimental result of the present invention, and FC (Fault Coverage) indicates failure Coverage rate, #HF (Hard Fault) represents the number of difficult-to-measure faults, #VEC (Vector) represents the number of test vectors, TP (Test Power) and PTP (Peak Test Power) represent the test average power consumption and test peak power of the present invention respectively The power consumption is compared to the test average power consumption and the test peak power consumption of the single-chain full scan test structure.

As can be seen from Table 1, the two-stage scanning test structure of the present invention can ensure that the original fault coverage and the number of test vectors are basically unchanged and the number of difficult-to-test faults does not increase, so that the average power consumption of the test and the number of test vectors are not increased. Peak power consumption has been greatly reduced.

Table 1: The present invention is applied to the experimental result of ISCAS89 and ITC99 circuit

Description of drawings

Figure 1: Schematic diagram of the combined successor.

Figure 2: Schematic diagram of the timing circuit.

Figure 3: Schematic diagram of scanning and testing sequential circuits.

Figure 4: Schematic diagram of the scan chain.

Figure 5: Schematic diagram of clock signals clk1 and clk2.

Figure 6: Circuit schematic.

Figure 7: Form conv[12][12].

Figure 8: Schematic diagram of the two-stage scanning test structure.

Figure 9: Program flow diagram for constructing a two-stage scan test structure with low test power consumption.

Detailed ways

The specific implementation manners of the above methods will be described below through specific examples.

Example 1: the circuit shown in Figure 6, wherein the total number of sequential units is 3, the output signal line of sequential unit 1 is identified as 1Out=5 in the circuit, and the output signal line of sequential unit 2 is identified as 2Out= in the circuit 6. The output signal line of the sequential unit 3 is marked as 3Out=7 in the circuit, and the arrays successor_of_5[], successor_of_6[] and successor_of_7[] are used to store the combined successors of the sequential units 1, 2 and 3 respectively.

The process of creating the form conv[3][3] is as follows:

1) For sequential unit 1 in the circuit, 1Out=5, 5 has only one direct combined successor 15, and 15 is stored in the array successor_of_5[].

The signal line 15 has three branches, the first branch is the input of the sequential unit 2, so there is no need to search further; the direct combination of the second branch is followed by 17, and 17 is stored in the array; the direct combination of the third branch is followed by is 16, store 16 in the array.

17 is the input of sequential unit 1, so there is no need to search further; 16 has already reached the original output, so there is no need to search further. Finish.

In this way, the contents stored in the array successor_of_5[] are: 15, 17, 16; similarly, the contents stored in the array successor_of_6[] are: 10, 13, 12, 14, 15, 17, 16; in the array successor_of_7[] The stored content is: 9, 11, 12, 14, 15, 17, 16.

2) Sequential units 1 and 2 have a common combined successor 15, so conv[1][2]=conv[2][1]=1;

Sequential units 1 and 3 have a common combined successor 15, so conv[1][3]=conv[3][1]=1;

Sequential cells 2 and 3 have a common combined successor 12, so conv[2][3]=conv[3][2]=1.

Example 2: The total number of sequential units in a circuit is 12, and the set is F. Figure 7 shows the table conv[12][12] representing the relationship between these sequential units in the circuit structure.

The grouping of sequential units according to the table conv[12][12] is as follows:

Create a new group G ₁ , put sequential unit 1 into G ₁ , G ₁ ={1}; traverse the remaining sequential units in F, and find that sequential unit 2 satisfies the condition conv[2][1]=0, that is, satisfies condition $\∀g\∈G_1,$ conv[2][g]=0, so put sequential unit 2 into G ₁ , G ₁ ={1, 2}; traverse the remaining sequential units in F, and find that sequential unit 4 satisfies the condition conv[4][1 ]=0 and conv[4][2]=0, which means the condition is satisfied $\∀g\∈G_1,$ conv[4][g]=0, so put sequential unit 4 into G ₁ , G ₁ ={1, 2, 4}; traverse the remaining sequential units in F, and find that sequential unit 7 satisfies the condition conv[7] [1]=0 and conv[7][2]=0 and conv[7][4]=0, which means the condition is satisfied $\∀g\∈G_1,$ conv[7][g]=0, so put sequential unit 7 into G ₁ , G ₁ ={1, 2, 4, 7}; traverse the remaining sequential units in F, and find that sequential unit 10 satisfies the condition conv[ 10][1]=0 and conv[10][2]=0 and conv[10][4]=0 and conv[10][7]=0, which means the condition is satisfied $\∀g\∈G_1,$ conv[10][g]=0, therefore put sequential unit 10 into G ₁ , G ₁ ={1, 2, 4, 7, 10}. By analogy, G ₂ ={3, 11, 12}, G ₃ ={5, 6, 8, 9} are obtained. The grouping is over.

The adjustment of the above grouping results according to the table conv[12][12] is as follows:

Select the largest group G _max =G1, the smallest group G _min =G2, select the sequential unit 2 from G _max to satisfy the conditions conv[2][3]=0 and conv[2][11]=0 and conv[2 ][12]=0, which means the condition is satisfied $\∀g\∈G_{\min },$ conv[2][g]=0, so put sequential unit 2 into G ₂ , then G ₁ ={1, 4, 7, 10}, G ₂ ={2, 3, 11, 12}, G ₃ = {5, 6, 8, 9}. At this point, the condition for uniform grouping has been met, and the adjustment ends.

The case of constructing a two-level scan structure with low test power consumption according to the adjusted grouping results is as follows:

Add a multiplexer MUX before each sequential unit to transform it into a scanning sequential unit; select a scanning sequential unit 1', 2' from each group G ₁ , G ₂ , and G ₃ according to the adjusted grouping results , 5' constitute a scanning chain, and the clock input of scanning sequential units 1', 2', 5' is connected to clock signal clk ₁ ; the clock input of each group of remaining sequential units is connected to clock signal clk ₂ ; the remaining sequential units in G ₁ The logic input of G2 is connected to the logic output of scan sequential cell 1', the logic input of the remaining sequential cells in _G2 is connected to the logic output of scan sequential cell 2', and the logic input of the remaining sequential cells in _G3 is connected to the scan sequential cell 5' The logic output; clock signals clk ₁ and clk ₂ are generated by the same clock signal clk plus two control signals through two AND gates, as shown in Figure 5; end.

Claims (1)

1. structure has the method for the two-stage sweep test structure of low testing power consumption, and it is characterized in that: it contains following steps successively:

The 1st step: initialization, to computing machine input circuit netlist file, adopt N*N form conv[N] [N] write down the mutual relationship of timing unit on circuit structure, wherein N is the sum of timing unit, conv[N] [N] be defined as follow-up relation table, and whether write down timing unit has common combination follow-up between any two on circuit structure; If for i ≠ j, i ∈ [1, N], timing unit i and the timing unit j of j ∈ [1, N], timing unit i and timing unit j have common combination follow-up on circuit structure, then conv[i] [j]=conv[j] [i]=1, otherwise conv[i] [j]=conv[j] [i]=0;

The 1.1st step: set up conv[N] [N] form;

The 1.1.1 step: for all timing units in the circuit, if the output signal line of timing unit i corresponding identification in circuit is iOut, successor_of_iOut[then] be defined as the combination successor list of timing unit i, it is follow-up to write down all combinations in circuit of this timing unit; If the output signal line of timing unit j corresponding identification in circuit is jOut, then successor_of_jOut[] be defined as the combination successor list of timing unit j, it is follow-up to write down all combinations in circuit of this timing unit; With the follow-up array successor_of_iOut[that deposits in successively of the combination of timing unit i] in, method is as follows: at first with the follow-up i of direct combination of timing unit i ₁i ₂I _nDeposit in the array, then successively with i ₁i ₂I _nFollow-up also the depositing in the array of direct combination, till the unit that deposits array in has been a timing unit or original output;

1.1.2 step: for any two timing unit i and j, if successor_of_iOut[] and successor_of_jOut[] in same unit is arranged, conv[i then] [j]=conv[j] [i]=1; Otherwise conv[i] [j]=conv[j] [i]=0;

The 2nd step: according to N*N form conv[N] [N] divide into groups to timing unit;

The 2.1st step: the set of establishing timing unit is F, and each group is respectively G ₁G ₂G _n

The 2.2nd step:, otherwise carried out for the 2.4th step if the F non-NULL then carried out for the 2.3rd step;

The 2.3rd step: set up new group G _m, m ∈ [1, n] appoints a timing unit g who gets among the F to put into G _m, remaining timing unit among the traversal F is if certain sequential unit f satisfies $\∀g\∈G_m,$ Conv[f] [g]=0, then f is put into G _m, upgrade F and G _m, continue remaining timing unit among the traversal F; Traversal finishes the back and changeed for the 2.2nd step;

The 2.4th step: grouping finishes;

The 3rd step:, the 2nd step gained group result is adjusted for making grouping evenly;

The 3.1st step: from G ₁G ₂G _nIn select maximum group G _MaxWith smallest group G _Min, G _MaxBe the maximum group of contained timing unit quantity, G _MinIt is the group of contained timing unit minimum number;

The 3.2nd step: from G _MaxIn select and satisfy condition $\∀g\∈G_{\min },$ Conv[f] the timing unit f of [g]=0, put into G with f _Min, upgrade G _MaxAnd G _Min

The 3.3rd step: carry out the 3.1st step and the 3.2nd step repeatedly, up to G _MaxWith G _MinSize to differ be 1 or G _MaxIn can not find and satisfied condition $\∀g\∈G_{\min },$ Conv[f] till the timing unit f of [g]=0;

The 4th step: according to adjusting later group result G ₁G ₂G _nConstruct the two-stage sweep test structure of low testing power consumption;

The 4.1st step: before each timing unit, add MUX MUX respectively, transform the scanning sequence unit as;

The 4.2nd step: from G ₁G ₂G _nIn respectively select a scanning sequence unit g ₁' g ₂' ... g _n', constitute a scan chain, scanning sequence unit g ₁' g ₂' ... g _n' clock input be connected to clock signal clk ₁

The 4.3rd step: G ₁G ₂G _nIn the clock input of remaining scanning sequence unit be connected to clock signal clk ₂

The 4.4th step: with G ₁In the logic input of remaining scanning sequence unit be connected to scanning sequence unit g ₁' logic output, with G ₂In the logic input of remaining scanning sequence unit be connected to scanning sequence unit g ₂' logic output, by that analogy, with G _nIn the logic input of remaining scanning sequence unit be connected to scanning sequence unit g _n' logic output;

The 4.5th step: add two control signal C by a clock signal clk ₁And C ₂By two and a door AND ₁And AND ₂Clocking clk ₁And clk ₂, wherein clock signal clk is connected respectively to two inputs and door AND ₁And AND ₂Input end, control signal C ₁And C ₂Be connected respectively to AND ₁And AND ₂Another input end, clock signal clk ₁And clk ₂Be respectively AND ₁And AND ₂Output; Work as C ₁=1 and C ₂=0 o'clock, clk ₁Effectively and clk ₂Invalid; Work as C ₁=0 and C ₂=1 o'clock, clk ₁Invalid and clk ₂Effectively.

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