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CN100416810C - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN100416810C
CN100416810C CNB2006100573009A CN200610057300A CN100416810C CN 100416810 C CN100416810 C CN 100416810C CN B2006100573009 A CNB2006100573009 A CN B2006100573009A CN 200610057300 A CN200610057300 A CN 200610057300A CN 100416810 C CN100416810 C CN 100416810C
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mentioned
contacts
protrusions
semiconductor element
circuit structure
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CN101034691A (en
Inventor
王俊恒
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Chipmos Technologies Inc
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Chipmos Technologies Bermuda Ltd
Chipmos Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device includes a circuit structure, a passivation layer, an under bump metallurgy pad and a bump. The circuit structure has a plurality of contacts. The protective layer is located on the circuit structure and has a plurality of openings and a plurality of protrusions, wherein the openings expose the contacts, and the protrusions are located on the contacts. The metal pads are disposed on the contacts and the protrusions. The bumps are arranged on the under bump metallurgy pads.

Description

半导体元件及其制造方法 Semiconductor element and its manufacturing method

技术领域 technical field

本发明涉及一种半导体元件及其制造工艺，且特别涉及一种能够增加与其它电子元件之间电连接之可靠性的半导体元件及其制造工艺。The present invention relates to a semiconductor element and its manufacturing process, and in particular to a semiconductor element capable of increasing the reliability of electrical connection with other electronic elements and its manufacturing process.

背景技术 Background technique

倒装芯片接合技术(flip chip interconnect technology)乃是一种将芯片(die)连接至线路板的封装技术，其主要是在芯片之多个接点上形成多个凸块(bump)。接着将芯片翻转(flip)，并利用这些凸块来将芯片的这些接点连接至线路板上的接合垫(terminal)，以使得芯片可通过这些凸块而电连接至线路板上。Flip chip interconnect technology (flip chip interconnect technology) is a packaging technology that connects a chip (die) to a circuit board, which mainly forms a plurality of bumps (bumps) on multiple contacts of the chip. Then the chip is flipped, and the bumps are used to connect the contacts of the chip to the bonding pads (terminals) on the circuit board, so that the chip can be electrically connected to the circuit board through the bumps.

图1A至图1C为公知之在芯片的接点上形成凸块的制造工艺示意图。请参照图1A，首先提供芯片110，其中芯片110具有有源表面112。芯片110还具有多个接点114，设置于有源表面112上。接着于有源表面112上形成一层保护层120。1A to 1C are schematic diagrams of a known manufacturing process for forming bumps on the contacts of a chip. Referring to FIG. 1A , firstly, a chip 110 is provided, wherein the chip 110 has an active surface 112 . The chip 110 also has a plurality of contacts 114 disposed on the active surface 112 . Then a protection layer 120 is formed on the active surface 112 .

请参照图1B，然后通过光刻/蚀刻工艺，在保护层120上形成多个开口122，其中这些开口122暴露出这些接点114。值得注意的是，由于开口122略小于接点114，因此位于开口122附近之保护层120具有隆起部分P。接着于保护层120与接点114上形成一层球底金属材料150。然后于球底金属材料150上形成光刻胶层130。之后通过光刻/蚀刻工艺在光刻胶层130上形成多个开口132，其中这些开口132暴露出球底金属材料150之相应于这些接点114的区域。接着，通过电镀将金形成于这些开口132内，以在芯片110上形成多个金凸块140，其中这些金凸块140通过球底金属材料150与这些接点114电连接。Referring to FIG. 1B , a plurality of openings 122 are formed on the passivation layer 120 through a photolithography/etching process, wherein the openings 122 expose the contacts 114 . It should be noted that since the opening 122 is slightly smaller than the contact 114 , the passivation layer 120 near the opening 122 has a raised portion P. Next, a layer of UBM material 150 is formed on the passivation layer 120 and the contact 114 . Then a photoresist layer 130 is formed on the UBM material 150 . Afterwards, a plurality of openings 132 are formed on the photoresist layer 130 through a photolithography/etching process, wherein the openings 132 expose regions of the UBM material 150 corresponding to the contacts 114 . Then, gold is formed in the openings 132 by electroplating to form a plurality of gold bumps 140 on the chip 110 , wherein the gold bumps 140 are electrically connected to the contacts 114 through the UBM material 150 .

请参照图1C，接着先移除光刻胶层130。之后以这些金凸块140为掩膜，移除不为金凸块140所覆盖的球底金属材料150，以形成具有多个金凸块140的芯片结构100。值得注意的是，由于金凸块140所覆盖的区域包含保护层120之环形的隆起部分P，因此金凸块140亦会具有环形的隆起部分Q，其中隆起部分Q是对应于隆起部分P。Referring to FIG. 1C , the photoresist layer 130 is removed first. Afterwards, using the gold bumps 140 as a mask, the UBM material 150 not covered by the gold bumps 140 is removed to form the chip structure 100 having a plurality of gold bumps 140 . It should be noted that since the area covered by the gold bump 140 includes the ring-shaped raised portion P of the passivation layer 120 , the gold bump 140 also has a ring-shaped raised portion Q, wherein the raised portion Q corresponds to the raised portion P.

请参照图2，其为具有公知技术所制造之凸块的芯片电连接于线路板之示意图。公知技术可以通过单向导电接着膜250以及已经制造完成的金凸块140，而将线路板200电连接于芯片110，其中单向导电接着膜250具有多个内层为导体而外层为绝缘体的颗粒252，而线路板200具有多个接合垫210。Please refer to FIG. 2 , which is a schematic diagram of a chip with bumps manufactured by known techniques electrically connected to a circuit board. The known technology can electrically connect the circuit board 200 to the chip 110 through the unidirectional conductive adhesive film 250 and the gold bump 140 that has been manufactured, wherein the unidirectional conductive adhesive film 250 has multiple inner layers as conductors and outer layers as insulators particles 252 , and the wiring board 200 has a plurality of bonding pads 210 .

详细地说，当线路板200通过单向导电接着膜250以及金凸块140而与芯片110电连接时，部分的颗粒252会同时受到金凸块140之隆起部分Q以及接合垫210的压迫。此时颗粒252外层之绝缘体受到隆起部分Q以及接合垫210压迫的部位便会破裂，并且暴露出内层的导体。如此一来，颗粒252内层之导体便能够通过外层之绝缘体的破裂处而与隆起部分Q以及接合垫210电接触，进而达到芯片110与线路板200之间的电连接。In detail, when the circuit board 200 is electrically connected to the chip 110 through the one-way conductive adhesive film 250 and the gold bump 140 , part of the particles 252 will be pressed by the protruding portion Q of the gold bump 140 and the bonding pad 210 at the same time. At this time, the insulator of the outer layer of the particle 252 is broken at the portion pressed by the raised portion Q and the bonding pad 210 , and the conductor of the inner layer is exposed. In this way, the conductor of the inner layer of the particle 252 can electrically contact the protruding portion Q and the bonding pad 210 through the breach of the outer layer of the insulator, thereby achieving the electrical connection between the chip 110 and the circuit board 200 .

值得注意的是，由于金凸块140之隆起部分Q的表面积相当的小，所以当公知技术通过单向导电接着膜250来将金凸块140电连接于接合垫210时，金凸块140与接合垫210之间的电连接关系会具有较低的可靠性。It should be noted that since the surface area of the raised part Q of the gold bump 140 is relatively small, when the gold bump 140 is electrically connected to the bonding pad 210 through the unidirectional conductive adhesive film 250 in the known technology, the gold bump 140 and the bonding pad 210 will be separated. The electrical connection relationship between the bonding pads 210 has low reliability.

发明内容 Contents of the invention

本发明的目的就是提供一种半导体元件及其制造工艺，以增加设置于半导体元件上之金凸块顶部的有效电连接区域。The object of the present invention is to provide a semiconductor device and its manufacturing process, so as to increase the effective electrical connection area on the top of the gold bump disposed on the semiconductor device.

本发明提出一种半导体元件，其包括电路结构、保护层、球底金属垫以及凸块。电路结构具有多个接点。保护层位于电路结构上，并且具有多个开口以及多个凸起物，其中这些开口暴露出这些接点，并且这些凸起物位于这些接点上。上述球底金属垫设置于上述这些接点与上述这些凸起物上，并且上述凸块设置于上述这些球底金属垫上。The invention provides a semiconductor device, which includes a circuit structure, a protection layer, a metal pad under a ball, and a bump. The circuit structure has multiple contacts. The protection layer is located on the circuit structure and has a plurality of openings and a plurality of protrusions, wherein the openings expose the contacts, and the protrusions are located on the contacts. The above-mentioned bottom metal pads are arranged on the above-mentioned contacts and the above-mentioned protrusions, and the above-mentioned bumps are arranged on the above-mentioned bottom metal pads.

依照本发明的较佳实施例所述之半导体元件，其中这些凸块的材料为金。In the semiconductor device according to a preferred embodiment of the present invention, the material of the bumps is gold.

依照本发明的较佳实施例所述之半导体元件，其中每一个接点上设置有一个凸起物。According to the semiconductor device described in the preferred embodiment of the present invention, each contact is provided with a protrusion.

依照本发明的较佳实施例所述之半导体元件，其中这些凸起物之外形为环状、条状或块状。According to the semiconductor device described in the preferred embodiment of the present invention, the shape of the protrusions is ring, strip or block.

依照本发明的较佳实施例所述之半导体元件，其中每一个接点上设置有多个凸起物。According to the semiconductor device described in the preferred embodiment of the present invention, a plurality of bumps are arranged on each contact.

依照本发明的较佳实施例所述之半导体元件，其中这些凸起物之外形为环状、条状、块状或是前述的组合。According to the semiconductor device described in the preferred embodiment of the present invention, the shape of the protrusions is ring, strip, block or a combination thereof.

本发明提出一种半导体元件的制造方法，其步骤包括先提供电路结构，其中这个电路结构具有多个接点。然后将一层保护材料覆盖于电路结构上。接着对这层保护材料进行图案化，以形成保护层，其中保护层具有多个开口以及多个凸起物。这些开口暴露出这些接点，并且这些凸起物位于这些接点上。然后于这些接点与这些凸起物上形成多个凸块，其中这些凸块的位置对应于这些接点The invention provides a method for manufacturing a semiconductor element, the steps of which include providing a circuit structure first, wherein the circuit structure has a plurality of contacts. Then a layer of protective material is covered on the circuit structure. Then pattern the protection material to form a protection layer, wherein the protection layer has a plurality of openings and a plurality of protrusions. The openings expose the contacts, and the bumps are located on the contacts. Then a plurality of bumps are formed on the contacts and the protrusions, wherein the positions of the bumps correspond to the contacts

依照本发明的较佳实施例所述之半导体元件的制造方法，还包括在对该层保护材料进行图案化之后与在形成上述这些凸块之前，于这些接点与这些凸起物上形成一层球底金属材料，且这些凸块形成于球底金属材料上。接着移除球底金属材料之不为这些凸块所覆盖的部分。The method for manufacturing a semiconductor element according to a preferred embodiment of the present invention further includes forming a layer on the contacts and the protrusions after patterning the layer of protective material and before forming the above-mentioned bumps. The metal material of the bottom of the ball, and these bumps are formed on the metal material of the bottom of the ball. The portion of the UBM not covered by the bumps is then removed.

由于本发明之电路结构的接点上具有多个凸起物，因此覆盖于这些接点上的凸块亦会具有多个对应于这些凸起物并且厚度实质上相同的隆起部分。所以，本发明所制造之半导体元件之凸块与线路板之接合垫之间的电连接关系会具有较高的可靠性。Since the contacts of the circuit structure of the present invention have a plurality of protrusions, the bumps covering these contacts also have a plurality of raised portions corresponding to these protrusions and having substantially the same thickness. Therefore, the electrical connection relationship between the bump of the semiconductor element and the bonding pad of the circuit board manufactured by the present invention has higher reliability.

为让本发明之上述和其它目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合附图，作详细说明如下。In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

附图说明 Description of drawings

图1A至图1C为公知之于芯片的接点上形成凸块的制造工艺示意图。1A to 1C are schematic diagrams of a known manufacturing process for forming bumps on the contacts of a chip.

图2为图1C之芯片结构电连接至基板的示意图。FIG. 2 is a schematic diagram of the chip structure in FIG. 1C being electrically connected to a substrate.

图3A至图3C为本发明一实施例之半导体元件的制造工艺示意图。3A to 3C are schematic diagrams of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

图4为图3C之半导体元件电连接至基板的示意图。FIG. 4 is a schematic diagram of the semiconductor device in FIG. 3C being electrically connected to a substrate.

主要元件标记说明Description of main component marking

100：芯片结构100: chip structure

110：芯片110: chip

112：有源表面112: active surface

114：接点114: contact

120：保护层120: protective layer

122：开口122: opening

130：光刻胶层130: photoresist layer

132：开口132: opening

140：金凸块140: Gold bump

P：隆起部分P: raised part

Q：隆起部分Q: bump

250：单向导电接着膜250: One-way conductive adhesive film

252：颗粒252: particles

200：线路板200: circuit board

210：接合垫210: Bonding Pad

300：半导体元件300: Semiconductor components

310：电路结构310: Circuit Structure

312：有源表面312: Active surface

314：接点314: contact

320a：保护材料320a: Protective material

320b：保护层320b: protective layer

322：开口322: opening

324：凸起物324: Protrusions

330：光刻胶层330: photoresist layer

332：开口332: opening

340：凸块340: Bump

360a：球底金属材料360a: ball bottom metal material

360b：球底金属垫360b: ball bottom metal pad

S：隆起部分S: raised part

X：隆起部分X: raised part

具体实施方式 Detailed ways

图3A至图3C为本发明一实施例之半导体元件的制造工艺示意图。请参照图3A，首先提供电路结构310，其中电路结构310具有有源表面312。此外，电路结构310还具有多个接点314，其位于有源表面312上。接着将一层保护材料320a形成于有源表面312以及这些接点314上，其中形成保护材料320a的方法例如为网版印刷、涂布或是直接将干膜形态的保护材料320a贴附于有源表面312上。3A to 3C are schematic diagrams of a manufacturing process of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 3A , firstly, a circuit structure 310 is provided, wherein the circuit structure 310 has an active surface 312 . In addition, the circuit structure 310 also has a plurality of contacts 314 located on the active surface 312 . Then a layer of protective material 320a is formed on the active surface 312 and these contacts 314, wherein the method of forming the protective material 320a is, for example, screen printing, coating or directly attaching the protective material 320a in dry film form to the active surface. surface 312 .

请参照图3B，接着例如通过光刻/蚀刻的方式将保护材料320a图案化以形成保护层320b。保护层320b具有多个开口322以及多个凸起物324，其中这些开口322暴露出这些接点314，并且这些凸起物324位于这些接点314上。每一个接点314上之凸起物324的形状例如是环状、条状与块状中的一种或其组合。Referring to FIG. 3B , the protective material 320 a is then patterned, for example, by photolithography/etching to form a protective layer 320 b. The protection layer 320 b has a plurality of openings 322 and a plurality of protrusions 324 , wherein the openings 322 expose the contacts 314 , and the protrusions 324 are located on the contacts 314 . The shape of the protrusion 324 on each contact 314 is, for example, one of ring shape, strip shape and block shape or a combination thereof.

值得注意的是，虽然在本实施例中单一个接点314上设置有多个凸起物324，但是本实施例并非用以限定单一个接点314上之凸起物324的数量。在本发明之其它实施例中，还可以通过适当的图案化过程在单一个接点314上仅设置一个凸起物324。此外，当单一个接点314上仅设置一个凸起物324时，其外型可以是环状、条状或块状。It should be noted that although a single contact 314 is provided with a plurality of protrusions 324 in this embodiment, this embodiment is not intended to limit the number of protrusions 324 on a single contact 314 . In other embodiments of the present invention, only one protrusion 324 may be provided on a single contact 314 through a suitable patterning process. In addition, when only one protrusion 324 is provided on a single contact 314, its shape can be ring, strip or block.

然后于保护层320b与这些接点314上形成一层球底金属材料360a。接着于球底金属材料360a上形成光刻胶层330，其中形成光刻胶层330的方式例如是涂布、电着沉积(electro deposition)或是直接将干膜(dry-film)光刻胶贴附于保护层320b上。然后通过光刻/蚀刻工艺在光刻胶层330上形成多个开口332，其中开口332暴露出球底金属材料360a之对应于接点314的区域。然后通过电镀的方式将凸块340形成于开口332内，其中凸块340机械及电连接于球底金属材料360a，并且凸块340的材质例如为金。Then a layer of UBM material 360a is formed on the passivation layer 320b and the contacts 314 . Then a photoresist layer 330 is formed on the bottom metal material 360a, wherein the photoresist layer 330 is formed by coating, electrodeposition (electro deposition) or directly applying a dry film (dry-film) photoresist Attached to the protection layer 320b. A plurality of openings 332 are then formed on the photoresist layer 330 by a photolithography/etching process, wherein the openings 332 expose the area of the UBM material 360 a corresponding to the contact 314 . Then, the bump 340 is formed in the opening 332 by electroplating, wherein the bump 340 is mechanically and electrically connected to the UBM material 360a, and the material of the bump 340 is, for example, gold.

请参照图3C，先移除光刻胶层330。之后以凸块340为掩膜，移除不为凸块340所覆盖的球底金属材料360a，以形成多个球底金属垫360b，并且得到半导体元件300。值得注意的是，由于保护层320b的厚度实质上为定值，因此保护层320b之邻近于开口322的隆起部分S的高度实质上与凸起物324之高度相同。如此一来，设置于接点314、凸起物324与隆起部分S上的凸块340的顶部亦会有多个相应的隆起部分X，并且每一个隆起部分X的高度实质上相同。Referring to FIG. 3C , the photoresist layer 330 is removed first. Afterwards, using the bump 340 as a mask, the UBM material 360 a not covered by the bump 340 is removed to form a plurality of UBM pads 360 b and obtain the semiconductor device 300 . It should be noted that since the thickness of the protection layer 320b is substantially constant, the height of the raised portion S of the protection layer 320b adjacent to the opening 322 is substantially the same as the height of the protrusion 324 . In this way, the top of the protrusion 340 disposed on the contact 314 , the protrusion 324 and the raised portion S also has a plurality of corresponding raised portions X, and the height of each raised portion X is substantially the same.

图4为图3C之半导体元件电连接至基板的示意图。请参照图4，本实施例可以通过单向导电接着膜250以及已经制造完成的凸块340，而将线路板200电连接于电路结构310，其中单向导电接着膜250具有多个内层为导体而外层为绝缘体的颗粒252，而线路板200具有多个接合垫210。FIG. 4 is a schematic diagram of the semiconductor device in FIG. 3C being electrically connected to a substrate. Please refer to FIG. 4 , in this embodiment, the circuit board 200 can be electrically connected to the circuit structure 310 through the unidirectional conductive adhesive film 250 and the manufactured bump 340, wherein the unidirectional conductive adhesive film 250 has multiple inner layers. The particles 252 are conductors and the outer layer is an insulator, and the circuit board 200 has a plurality of bonding pads 210 .

详细地说，当线路板200通过单向导电接着膜250以及凸块340而与电路结构310电连接时，部分的颗粒252会同时受到凸块340之多个隆起部分X以及接合垫210的压迫。此时颗粒252外层之绝缘体受到这些隆起部分X以及接合垫210压迫的部位便会破裂，并且暴露出内层的导体。如此一来，颗粒252内层之导体便能够通过外层之绝缘体的破裂处而与凸块340以及接合垫210电接触，进而达到电路结构310与线路板200之间的电连接。In detail, when the circuit board 200 is electrically connected to the circuit structure 310 through the unidirectional conductive adhesive film 250 and the bump 340 , part of the particles 252 will be simultaneously pressed by the raised portions X of the bump 340 and the bonding pad 210 . At this time, the insulator of the outer layer of the particle 252 is broken at the portion pressed by the raised portion X and the bonding pad 210 , and the conductor of the inner layer is exposed. In this way, the conductors in the inner layer of the particles 252 can electrically contact the bumps 340 and the bonding pads 210 through the breaks in the outer layer of the insulator, thereby achieving electrical connection between the circuit structure 310 and the circuit board 200 .

综上所述，由于本发明之电路结构的接点上具有多个凸起物，因此覆盖于这些接点上的凸块亦会具有多个对应于这些凸起物的隆起部分，其中这些隆起部分的厚度实质上相同。当电路结构通过这些凸块而与基板电连接时，由于凸块之顶部上的多个隆起部分都可以用来压迫单向导电接着膜内的颗粒，而公知技术所制造的金凸块仅能通过其表面上的单一个隆起部分来压迫单向导电接着膜内的颗粒，所以本发明之半导体元件的凸块与接合垫之间的电连接关系会具有较高的可靠性。In summary, since the contacts of the circuit structure of the present invention have a plurality of protrusions, the bumps covering these contacts will also have a plurality of raised portions corresponding to these protrusions, wherein the raised portions The thicknesses are substantially the same. When the circuit structure is electrically connected to the substrate through these bumps, the gold bumps produced by the known technology can only be The particles in the one-way conductive bonding film are pressed by a single raised portion on the surface, so the electrical connection relationship between the bump and the bonding pad of the semiconductor element of the present invention has higher reliability.

虽然本发明已以较佳实施例披露如上，然其并非用以限定本发明，任何所属技术领域的技术人员，在不脱离本发明之精神和范围内，当可作些许之更动与改进，因此本发明之保护范围当视权利要求所界定者为准。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (8)

1. semiconductor element is characterized in that comprising:
Circuit structure has a plurality of contacts;
Protective layer is positioned on the foregoing circuit structure, and this protective layer has a plurality of openings and a plurality of protrusion, and wherein above-mentioned these openings expose above-mentioned these contacts, and above-mentioned these protrusions are positioned on above-mentioned these contacts; And
Ball substrate pad and projection, above-mentioned ball substrate pad is arranged on above-mentioned these contacts and above-mentioned these protrusions, and above-mentioned projection is arranged on above-mentioned these ball substrate pads.
2. the semiconductor element according to claim 1 is characterized in that the material of above-mentioned these projections is gold.
3. the semiconductor element according to claim 1 is characterized in that each above-mentioned these contact is provided with an above-mentioned protrusion.
4. the semiconductor element according to claim 3 is characterized in that shape is ring-type, strip or bulk outside above-mentioned these protrusions.
5. the semiconductor element according to claim 1 is characterized in that each above-mentioned these contact is provided with a plurality of above-mentioned these protrusions.
6. the semiconductor element according to claim 5 is characterized in that shape is ring-type, strip, bulk or aforesaid combination outside above-mentioned these protrusions.
7. the manufacture method of a semiconductor element is characterized in that its step comprises:
Circuit structure is provided, and wherein this circuit structure has a plurality of contacts;
One deck protective material is covered on the foregoing circuit structure;
This layer protective material carried out patterning, and to form protective layer, wherein this protective layer has a plurality of openings and a plurality of protrusion, and above-mentioned these openings expose above-mentioned these contacts, and above-mentioned these protrusions are positioned on above-mentioned these contacts; And
Form a plurality of projections on above-mentioned these contacts and above-mentioned these protrusions, wherein the position of above-mentioned these projections is corresponding to above-mentioned these contacts.
8. according to the manufacture method of the described semiconductor element of claim 7, it is characterized in that also comprising:
After being carried out patterning, this layer protective material, on above-mentioned these contacts and above-mentioned these protrusions, form one deck ball substrate material, and above-mentioned these projections are formed on the above-mentioned ball substrate material with before forming above-mentioned these projections; And
What remove above-mentioned ball substrate material is not the part that above-mentioned these projections covered.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952718A (en) * 1996-02-23 1999-09-14 Matsushita Electric Industrial Co., Ltd. Semiconductor devices having protruding contacts
CN1512566A (en) * 2002-12-27 2004-07-14 威宇科技测试封装（上海）有限公司 Substrate for face down bonding
CN1619807A (en) * 2004-12-06 2005-05-25 友达光电股份有限公司 Substrates including integrated circuit chips and integrated circuits thereon

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952718A (en) * 1996-02-23 1999-09-14 Matsushita Electric Industrial Co., Ltd. Semiconductor devices having protruding contacts
CN1512566A (en) * 2002-12-27 2004-07-14 威宇科技测试封装（上海）有限公司 Substrate for face down bonding
CN1619807A (en) * 2004-12-06 2005-05-25 友达光电股份有限公司 Substrates including integrated circuit chips and integrated circuits thereon

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