CN100414667C - Storage capacitor, forming method thereof and display comprising storage capacitor - Google Patents

Abstract

A method for forming a storage capacitor includes: sequentially forming a semiconductor layer and a first dielectric layer on a substrate; forming a patterned photoresist layer on the first dielectric layer, the patterned photoresist layer including a first region and a second region adjacent to the first region; removing the first dielectric layer and the semiconductor layer which are not shielded by the patterned photoresist layer; removing the first region to expose the first dielectric layer; carrying out a doping process by taking the second region as a shield to form at least one doped region in a part of the semiconductor layer to be used as a first electrode; removing the second region; forming a second dielectric layer and a conductive layer in sequence to cover the substrate and the first dielectric layer; and patterning the conductive layer to form a second electrode substantially corresponding to the first electrode.

Description

Storage capacitor, method for forming the same, and display including the storage capacitor

technical field

The invention relates to a storage capacitor, in particular to a manufacturing process capable of reducing the storage capacitor of a photomask and the formed storage capacitor.

Background technique

1 to 3 show cross-sectional views of the manufacturing process of thin film transistors and capacitors of conventional active element substrates. As shown in FIG. 1 , a substrate 100 is provided, including a transistor region 100A and a capacitor region 100B. The semiconductor layer 101 is deposited and patterned on the substrate 100 , respectively located in the transistor region 100A and the capacitor region 100B. As shown in FIG. 2 , an insulating layer 103 is deposited on the semiconductor layer 101 and the substrate 100 , serving as the gate insulating layer of the TFT in the transistor region 100A and as the dielectric layer of the storage capacitor in the capacitor region 100B. Next, a photoresist is formed on the insulating layer 103 , and a patterned photoresist 105 is patterned to expose both ends of the semiconductor layer 101 in the transistor region 100A and the semiconductor layer 101 in the storage capacitor region 100B. After that, source/drain electrodes 102 are formed at both ends of the semiconductor layer 101 in the transistor region 100A by doping process 107 , and the semiconductor layer 101 in the capacitor region 100B is doped to form the lower electrode of the storage capacitor. The patterned photoresist 105 is removed after the doping process 107 is completed.

Next, a conductive layer 109 is deposited and patterned on the insulating layer 103 to serve as the gate of the transistor region 100A and the upper electrode of the capacitor region 100B, respectively. Finally, with the conductive layer 109 of the transistor region 100A as a shield, a lightly doped process 111 is performed to form a lightly doped region 115 .

Traditionally, three photomasks are required in the process steps of forming thin film transistors and storage capacitors. Firstly, the first photomask is required in patterning the semiconductor layer 101 . Then, a second photomask is required when the photoresist 105 is patterned to form a mask for doping the doped region 102 , and the doped region 102 can also be called a source region/drain region. Finally, a third photomask is required when patterning the conductive layer 109 as the gate and the upper electrode.

In the process, the number of photomasks is an important factor determining the cost of the process, so there is an urgent need in the art for a method that can reduce the number of photomasks to reduce its manufacturing cost.

Contents of the invention

In view of this, the object of the present invention is to provide a method for forming a storage capacitor, which uses photomasks with different light transmittances to reduce the number of photomasks required for the manufacturing process of thin film transistors and storage capacitors.

To achieve the above object, the present invention provides a method for forming a storage capacitor, comprising: sequentially forming a semiconductor layer and a first dielectric layer on a substrate; forming a patterned photoresist layer on the first dielectric layer, and the patterned photoresist includes a first region and a second region adjacent to the first region; removing the first dielectric layer and the semiconductor layer not shielded by the patterned photoresist layer ; removing the first region to expose the first dielectric layer; performing a doping process using the second region as a mask to form at least one doped region in part of the semiconductor layer to serve as a first electrode; removing the second region; sequentially forming a second dielectric layer and a conductive layer covering the substrate and the first dielectric layer; and patterning the conductive layer to form a second electrode substantially corresponding to the first an electrode.

The present invention also provides a storage capacitor, comprising: a first electrode disposed on a substrate, and the first electrode has a depletion region located on one of two ends of the first electrode and at least one doped region adjacent to the first electrode. A depletion region; a dielectric layer disposed on the first electrode; and a second electrode disposed on the dielectric layer substantially corresponding to the first electrode.

The present invention still provides a display, which has a substrate, including: a semiconductor pattern layer, respectively formed on at least one transistor region and at least one capacitor region of the substrate, wherein the semiconductor pattern layer on the capacitor region has at least one power dissipation The depletion region is located on one of the two ends of the first electrode and at least one doped region is adjacent to the depletion region, and the two ends of the semiconductor pattern layer on the transistor region have a high-concentration doped region; A dielectric layer, formed on the semiconductor pattern layer; a first conductor pattern layer, formed on the first dielectric layer, and respectively corresponding to the semiconductor pattern layer located on the capacitor region and the transistor region; a protective layer formed on the substrate, covering the first patterned conductor layer; and a second patterned conductor layer, formed on the protection layer, and respectively electrically connected to the high-concentration-doped two ends of the semiconductor patterned layer on the transistor region district.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with reference to the accompanying drawings.

Description of drawings

1 to 3 show cross-sectional views of the manufacturing process of thin film transistors and capacitors on conventional active device substrates.

4 to 15 show cross-sectional views of the process flow of the active device substrate according to the preferred embodiment of the present invention.

16 to 19 show cross-sectional views of variations of the embodiments of the present invention.

simple notation

Substrate ~ 100; Transistor area ~ 100A;

Capacitance area ~ 100B; Insulation layer ~ 103;

Source region/drain region ~ 102; Conductive layer ~ 109;

Patterned photoresist ~ 105; Substrate ~ 400;

Transistor area ~ 400A; Capacitance area ~ 400B;

Semiconductor layer ~ 401; Dielectric layer ~ 403;

Photoresist ~ 405A and 405B; Thick photoresist area ~ 405a;

Thin photoresist region ~ 405b; Doping process ~ 407;

Doping region ~ 409; Depletion region ~ 408;

Step difference ~ 402a, 402b; Conductive layer ~ 413;

Dielectric layer ~ 411; Photoresist ~ 415A, 415B;

Doping area ~ 419; Doping process ~ 417;

Lightly doped region ~ 421; Lightly doped process ~ 418;

Dielectric layer ~ 423; Contact window ~ 425;

Source region/drain region contact ~ 427; Protective layer ~ 429;

Contact window ~ 431; Conductive layer ~ 433;

Dielectric layer ~ 437; Light emitting layer ~ 435.

Detailed ways

The preferred embodiment of the present invention will be described below in conjunction with FIGS. It is worth noting that the storage capacitor of the present invention is not limited to be matched with a specific type of thin film transistor (TFT), nor is it limited to the storage capacitor applied to a display panel.

As shown in FIG. 4 , a substrate 400 is provided, including a transistor region 400A and a capacitor region 400B, wherein the substrate 400 can be a transparent substrate, such as glass or quartz, or an opaque substrate, such as a wafer (wafer) or ceramics, Alternatively, in addition to the above-mentioned rigid substrate, it may also be a flexible substrate, such as plastic, polyester or rubber. Form semiconductor layer 401 sequentially on substrate 400, its material comprises polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon or the combination of above-mentioned material, and dielectric layer 403, its material comprises inorganic compound (such as: silicon oxide, nitrogen silicon carbide, silicon oxynitride, silicon carbide, silicon oxycarbide or a combination of the above materials), organic compounds (such as: polyesters, epoxy polymers, organosilicon compounds, acrylic polymers, similar materials or combinations of the above materials combination). Next, a photoresist layer is formed on the dielectric layer 403, and photoresists 405A and 405B are respectively formed in the transistor region 400A and the capacitor region 400B by a photolithography process, wherein the photoresist of the capacitor region 400B 405B is through a photomask with different light penetration (such as: half-tone photomask, gray-level photomask, grid pattern photomask (slit photomask), etc. -pattern photomask), around (diffraction) photomask (diffraction photomask)) patterned formation, have thick photoresist region 405a and thin photoresist region 405b, and thick photoresist region 405a is adjacent to thin photoresist region 405b. As shown in FIG. 5, the etching process is carried out with the photoresist 405A and 405B as a mask, preferably an isotropic etching process, which can be dry etching or wet etching, and is used to remove the uncoated photoresist. 405A and 405B shield the dielectric layer 403 . The wet etching method includes immersion etching, spray etching or other similar etching methods, and the dry etching method includes reactive ion etching, plasma etching or other similar etching methods.

Next, as shown in FIG. 6A , the semiconductor layer 401 not covered by the photoresists 405A and 405B is removed by an isotropic etching step, such as dry etching or wet etching. Alternatively, as shown in FIG. 6B , the semiconductor layer 401 not covered by the photoresists 405A and 405B is removed by an anisotropic etching process, such as a dry etching process or a wet etching process. The wet etching method includes immersion etching, spray etching or other similar etching methods, and the dry etching method includes reactive ion etching, plasma etching or other similar etching methods. Then as shown in Figures 7A and 7B, where Figure 7A continues the process of Figure 6A, and Figure 7B continues the process of Figure 6B, a plasma trimming process (plasma trimming process, such as: ashing process (ashing process)) is performed to photoresist The thin photoresist region 405b of the etchant 405B is completely removed, exposing a portion of the top surface of the dielectric layer 403 in the capacitor region 400B, while the thick photoresist region 405a remains on the dielectric layer 403, And shield both ends of the semiconductor layer 401 . Afterwards, a doping process 407 is performed, such as N-type doping or P-type doping, to form a doping region 409 in the semiconductor layer 401 that is not covered by the thick photoresist 405a in the capacitor region 400B, as the first capacitor of the storage capacitor. an electrode. As shown in FIGS. 7A and 7B, since the thick photoresist region 405a covers both ends of the semiconductor layer 401, a depletion region will be formed at both ends of the semiconductor layer 401 in the capacitor region 400B after the doping process 407. 408 , because there is no N-type or P-type doping substance used in the doping process 407 in the depletion region 408 , so the depletion region 408 can also be called a non-doped region.

As shown in FIGS. 8A and 8B , where FIG. 8A is a continuation of FIG. 7A , and FIG. 8B is a continuation of the process of FIG. 7B , the photoresist in the transistor region 400A and capacitor region 400B is completely removed. 5 to 7B, the dielectric layer 403 not covered by the photoresist is removed by an isotropic etching process, and then the dielectric layer 403 not covered by the photoresist is removed by an anisotropic etching process. The semiconductor layer 401 will produce step differences 402a and 402b at the two ends of the semiconductor layer 401 and the dielectric layer 403 in the transistor region 400A and the capacitor region 400B, so the photoresist in the transistor region 400A and the capacitor region 400B Afterwards, an anisotropic etching process (not shown) is performed again to eliminate the step differences 402a and 402b as shown in FIG. 7B , as shown in FIG. 8B . However, if in order to reduce the requirements on the process, the etching process for eliminating the step differences 402a and 402b as shown in FIG. 7B can be omitted, and the formed structure is substantially removed from the photoresist pattern layer 405a as shown in FIG. 7B shown after.

As shown in FIG. 9, a dielectric layer 411 and a conductive layer 413 are sequentially deposited on the substrate 400 and the dielectric layer 403, wherein the dielectric layer 411 includes an inorganic compound (such as: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide , silicon carbide or a combination of the above materials), organic compounds (such as: polyester, epoxy polymer, organosilicon compound, acrylic polymer, similar materials or a combination of the above materials), and the conductive layer 413 includes transparent Conductive layer (such as: indium tin oxide (ITO), aluminum zinc oxide (aluminum zinc oxide, AZO), indium zinc oxide (indium zinc oxide, IZO), cadmium tin oxide (cadmium tin oxide, CTO)), non-transparent conductive layer (such as: titanium (titanium, Ti), tantalum (tantalum, Ta), molybdenum (molybdenum, Mo), aluminum (aluminum, Al), neodymium (neodymium, Nd), gold (golden, Au), silver (silver, Ag), copper (copper, Cu)) or a combination of the above materials. Next, deposit and pattern a photoresist layer on the conductive layer 413, and form patterned photoresists 415A and 415B in the transistor region 400A and the capacitor region 400B, respectively, as shown in FIG. 10 , wherein the patterned photoresist The resist 415A corresponds to the semiconductor layer 401 of the transistor region 400A and does not cover both ends of the semiconductor layer 401 in the transistor region 400A, so as to facilitate subsequent source and drain doping processes. The photoresist 415B completely covers the capacitor region 400B and partially covers the substrate 400 .

As shown in FIG. 11 , with an isotropic etching process, such as dry etching or wet etching, the conductive layer 413 that is not covered by the photoresist 415A and the photoresist 415B is etched away, and then the doping process 417, such as N-type doping or P-type doping, forming a doping region 419 at both ends of the semiconductor layer 401 not covered by the photoresist 415A in the transistor region 400A as the source region/drain region of the transistor , wherein the doping concentration of the doping region 419 may be the same as or different from the doping concentration of the doping region 409 in the capacitor region 400B. The aforementioned wet etching methods include immersion etching, spray etching or other similar etching methods, and the dry etching methods include reactive ion etching, plasma etching or other similar etching methods. As shown in FIG. 12 , after removing the photoresists 415A and 415B, the conductive layer 413 is used as a shield to perform a light doping process 418, and the semiconductor layer between the conductive layer 413 and the doped region 419 in the transistor region 400A is A lightly doped region (LDD region) 421 is formed in 401, in other words, there is an unshielded region between the conductive layer 413 projected on the semiconductor layer 401 and the doped region 419 in the semiconductor layer 401 in the transistor region 400A, and After the lightly doped process 418 is performed, a lightly doped region (LDD region) 421 is formed in the unshielded region, wherein the doping concentration of the lightly doped region 421 can be compared with the doping concentration of the doped region 409 in the capacitor region 400B The same or different, in another embodiment, the doping concentration of the doped region 409 in the capacitor region 400B is approximately between the doping concentrations of the lightly doped region 421 and the doped region 419 in the transistor region 400A. Compared with the process of thin-film transistors and capacitors on the traditional active element substrate, the present invention uses photomasks with different light penetration to form thin and thick photoresists in the capacitor area, and only one photomask is used. Complete the patterning and doping of the first electrode, so that only one more photomask (patterned to form photoresist 415A and 415B) is needed to complete the source region/drain region and The process of the lightly doped region (LDD) greatly reduces its manufacturing cost. As shown in Figure 12, the storage capacitor of the present invention has a first electrode, including a doped region 409 and a depletion region 408 at both ends thereof, a second electrode 413, and dielectric layers 403, 411, which are sandwiched between the second electrode and the first electrode. between one electrode.

FIG. 13 to FIG. 15 show the cross-sectional process views of the display active element substrate using the storage capacitor of the present invention. As shown in FIG. 13, a dielectric layer 423 is formed on the structure shown in FIG. 12, which can be an inorganic compound (such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or a combination of the above materials) , organic compound (such as: polyester, epoxy polymer, organosilicon compound, acrylic polymer, similar materials or combinations of the above materials), and pattern the dielectric layer 423, the dielectric layer 411 and the dielectric layer 403 forms a contact window 425 and exposes the pre-partial surface of the partially doped region 419 in the transistor region 400A. Next, a conductive layer is formed on the structure shown in FIG. 13, and its material includes a transparent conductive material (such as: indium tin oxide (indium tin oxide, ITO), aluminum zinc oxide (aluminum zinc oxide, AZO), indium zinc oxide (indium zinc oxide, IZO), cadmium tin oxide (cadmium tin oxide, CTO)), non-transparent conductive materials (such as: titanium (titanium, Ti), tantalum (tantalum, Ta), molybdenum (molybdenum, Mo), Aluminum (aluminum, Al), neodymium (neodymium, Nd), gold (golden, Au), silver (silver, Ag), copper (copper, Cu)) or a combination of the above materials, filling the contact window 425 and doping The top surface of region 419 is electrically connected and then patterned to form source/drain region contacts 427 as shown in FIG. 14 .

As shown in FIG. 15, a protective layer 429 is formed on the structure shown in FIG. 14, and its material includes an inorganic compound (such as: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or a combination of the above materials) , organic compound (such as: polyester, epoxy polymer, organosilicon compound, propylene polymer, similar materials or a combination of the above materials), and pattern it to form a contact window 431, and expose the source region/ Part of the top surface of the drain region contact 427, then, form a conductive layer 433 on the protection layer 429, fill the contact window 431 and be electrically connected with the source/drain contact 427, as the pixel electrode of the display, if applied to a liquid crystal display Among them, the pixel electrode includes a penetrating electrode, a reflective electrode, or a combination of a penetrating electrode and a reflective electrode, and is used to control the direction of liquid crystal molecules in the liquid crystal layer in the liquid crystal display. If the liquid crystal display is a penetrating type, the pixel electrode uses Transparent conductive material is used as the penetrating electrode, and the material of the conductive layer 433 is preferably ITO, IZO, CTO, AZO or a combination of the above materials. If the liquid crystal display is reflective, the pixel electrode uses a non-transparent conductive material as the reflective electrode, and its material can be The non-transparent conductive material is preferably Ti, Ta, Mo, Al, Nd, Au, Ag, Cu or a combination of the above materials. If the liquid crystal display is a semi-transparent and semi-reflective type, the pixel electrode uses a non-transparent conductive material and a transparent conductive material. material, the material of the conductive layer 433 is preferably ITO, IZO, CTO, AZO, Ti, Ta, Mo, Al, Nd, Au, Ag, Cu, alloy or a combination of the above materials. If it is applied in an electroluminescence display (electroluminescence display) such as: organic light-emitting diode (organicelectroluminescence diode, OLED), polymer light-emitting diode (polymerelectroluminescence diode, PLED), or light emitting diode (light emitting diode, LED), there will be light-emitting materials 435 is electrically connected to the conductive layer 433 or the source/drain contact 427, and the luminescent material 435 can be an organic material (including small molecules or polymers) or an inorganic material, and the light emitted by the luminescent material 435 includes fluorescence, phosphorescence or the above-mentioned combination, or form a liquid crystal layer as a liquid crystal display. Furthermore, in order to increase the adhesion between the semiconductor layer 401 and the substrate 400, the dielectric layer 437 can be formed on the substrate 400 before the semiconductor layer 401 is formed on the substrate, and the subsequent steps are the same as those of the present invention. The graphics and steps described above are not repeated here, as shown in FIG. 15 .

Although the areas of the second depletion region 408, the second doped region 419 and the second lightly doped region 421 described in the embodiment of the present invention are all symmetrical, however, the second depletion region 408, the second doped region 419 and the second lightly doped region The area of the doped region 421 can also be asymmetric. As shown in FIG. 16, the depletion region 408 is asymmetric. In addition, since the areas of the second doped region 419 and the second lightly doped region 421 can be symmetrical or asymmetrical, that is to say, their combination can include that the area of the second doped region 419 is asymmetrical, and the area of the second lightly doped region 421 can be asymmetrical. The area of the region 421 is symmetric or the area of the second doped region 419 is symmetric, while the area of the second lightly doped region 421 is asymmetric, as shown in FIGS. 17a and 17b. Furthermore, only the lightly doped region 421 may exist between the two doped regions 419, and the area of the second doped region 419 may also be asymmetric or symmetrical, as shown in FIGS. 18a and 18b. The only difference in the steps of the pattern is that the patterned photoresist 415A and the design changes of the conductive layer 413 are used, and there is no need to redesign the steps, and the current steps can also be used. Furthermore, it should be noted that the above-mentioned embodiments are all described with the depletion region 408 at both ends of the storage capacitor region 400B as an example. However, one of the two ends of the storage capacitor region 400B may also have a depletion region. 408 , as shown in FIG. 19 , in other words, the depletion region 408 is adjacent to the doped region 409 . And the step of this figure, only difference is in the thick photoresist region 405a and the thin photoresist region 405b design change of patterned photoresist 405B among Fig. 6 to Fig. 7, and does not have any new The design steps are considered, and the current steps can also be used, so I won’t repeat them here.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can make some changes and modifications to it without departing from the spirit and scope of the present invention, therefore The scope of protection of the present invention is defined by the appended claims.

Claims (22)

1. A method for forming a storage capacitor, comprising: sequentially forming a semiconductor layer and a first dielectric layer on the substrate; forming a patterned photoresist layer on the first dielectric layer, and the patterned photoresist includes a first region and a second region adjacent to the first region; removing the first dielectric layer and the semiconductor layer not masked by the patterned photoresist layer; removing the first region to expose the first dielectric layer; performing a doping process using the second region as a mask, forming at least one doped region in a part of the semiconductor layer to serve as a first electrode; remove the second zone; sequentially forming a second dielectric layer and a conductive layer covering the substrate and the first dielectric layer; and The conductive layer is patterned to form a second electrode substantially corresponding to the first electrode. 2. The method for forming a storage capacitor according to claim 1, wherein in the doping process, the undoped semiconductor layer forms a depletion region on one of the two ends of the first electrode. 3. The method for forming a storage capacitor according to claim 1, wherein the step of removing the first region to expose the first dielectric layer is to sequentially remove the light not patterned by isotropic etching. The first dielectric layer and the semiconductor layer are masked by resist. 4. The method for forming a storage capacitor according to claim 1 , wherein the step of removing the first region to expose the first dielectric layer is to remove the photoinduced by the patterning by isotropic etching. resist masking the first dielectric layer; and Anisotropic etching removes the semiconductor layer not masked by the patterned photoresist. 5. The method for forming a storage capacitor as claimed in claim 1, wherein the doping process comprises N-type doping or P-type doping. 6. The method for forming a storage capacitor as claimed in claim 1, wherein patterning the conductive layer further comprises: forming a photoresist pattern on the conductive layer substantially corresponding to the first electrode, wherein the photoresist pattern has a width greater than that of the first electrode; and An isotropic etching process is performed to remove the conductive layer not covered by the photoresist pattern. 7. A storage capacitor, comprising: a first electrode disposed on the substrate, and the first electrode has at least one depletion region on one of the two ends of the first electrode and at least one doping region adjacent to the depletion region; a dielectric layer disposed on the first electrode; and The second electrode is arranged on the dielectric layer and basically corresponds to the first electrode. 8. The storage capacitor as claimed in claim 7, wherein the first electrode comprises: polycrystalline silicon, single crystal silicon, amorphous silicon, microcrystalline silicon or a combination of the above materials. 9. The storage capacitor according to claim 7, wherein the two ends of the first electrode respectively have the depletion region, and the doped region is located between the depletion regions. 10. A display comprising: The semiconductor pattern layer is respectively formed on at least one transistor region and at least one capacitor region of the substrate, wherein the semiconductor pattern layer located on the capacitor region has a depletion region and at least one doping region, and the depletion region is located on the capacitor One of the two ends of the semiconductor pattern layer on the region, and the at least one doped region is adjacent to the depletion region, and the two ends of the semiconductor pattern layer on the transistor region have a high-concentration doped region; a first dielectric layer formed on the semiconductor pattern layer; a first conductor pattern layer, formed on the first dielectric layer, and respectively corresponding to the semiconductor pattern layer on the capacitor region and on the transistor region; a protective layer formed on the substrate and covering the first conductor pattern layer; and The second conductor pattern layer is formed on the protection layer and electrically connected to the high-concentration doped regions at two ends of the semiconductor pattern layer on the transistor region. 11. The display device according to claim 10 , further comprising a second dielectric layer formed on the substrate, and the semiconductor pattern layer is formed on the second dielectric layer. 12. The display device according to claim 11 , further comprising a third dielectric layer formed on the substrate and covering the first dielectric layer. 13. The display device according to claim 10 , further comprising at least one low-concentration doped region formed between two ends of the semiconductor pattern layer on the transistor region, and the low-concentration doped region is adjacent to the high One of the two concentration doped regions. 14. The display device according to claim 10 , further comprising a pixel electrode electrically connected to the second conductive pattern layer. 15. The display device according to claim 14 , further comprising a luminescent material electrically connected to the pixel electrode. 16. The display device according to claim 10, further comprising a luminescent material electrically connected to the second conductor pattern layer. 17. The display as claimed in claim 13 , wherein the doping concentration of the doped region of the capacitor region is the same as the doping concentration of the low concentration doped region of the transistor region. 18. The display as claimed in claim 13 , wherein the doping concentration of the doped region of the capacitor region is different from the doping concentration of the low concentration doped region of the transistor region. 19. The display as claimed in claim 10 , wherein the doping concentration of the doped region of the capacitor region is the same as the doping concentration of the highly doped region of the transistor region. 20. The display as claimed in claim 10 , wherein the doping concentration of the doped region of the capacitor region is different from the doping concentration of the highly doped region of the transistor region. 21. The display as claimed in claim 13 , wherein the doping concentration of the doped region of the capacitor region is between the doping concentrations of the high-concentration doped region and the low-concentration doped region of the transistor region. 22. The display device as claimed in claim 10, wherein two ends of the first electrode respectively have the depletion region, and the doping region is located between the depletion regions.

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