CN100414551C - Back marking/analyzing flow for integrated circuit drawing parasitic parameter - Google Patents
Back marking/analyzing flow for integrated circuit drawing parasitic parameter Download PDFInfo
- Publication number
- CN100414551C CN100414551C CNB2005100936667A CN200510093666A CN100414551C CN 100414551 C CN100414551 C CN 100414551C CN B2005100936667 A CNB2005100936667 A CN B2005100936667A CN 200510093666 A CN200510093666 A CN 200510093666A CN 100414551 C CN100414551 C CN 100414551C
- Authority
- CN
- China
- Prior art keywords
- schematic diagram
- parasitic parameter
- parameter
- domain
- net table
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003071 parasitic effect Effects 0.000 title claims description 29
- 238000010586 diagram Methods 0.000 claims description 31
- 239000000284 extract Substances 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 6
- 238000013459 approach Methods 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 12
- 230000010354 integration Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 238000011161 development Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Landscapes
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
This invention relates to integration circuit page register parameter mark and analysis flow, which marks the register parameter to principle map according to the design layer module and provides one direct page register situation and helps designer analyze their impact one circuit and rapidly positions and improve debug efficiency.
Description
Technical field
The present invention handles the back reactionary slogan, anti-communist poster to schematic diagram with the parasitic parameter on the domain, helps the deviser to analyze, and is the assistant analysis instrument at physical Design.
Background technology
The important ring that whether the domain physics realization of checking circuit can meet design requirement after physical Design was finished in the parasitic parameter reactionary slogan, anti-communist poster knowledge integrated circuit (IC) design flow process.Efficiently and accurately parasitic parameter extraction reactionary slogan, anti-communist poster can improve the efficient of design, shortens the time that is designed into market, reduces risk.Yet along with the development of technology, the scale of design is increasing, and the scale of domain becomes greatly thereupon, and the parasitic parameter in the domain also sharply increases.In the face of more and more parasitic parameters, though their reactionary slogan, anti-communist poster can be done the back simulation in the net table, the performance of domain circuit is had gained some understanding, still not enough to some extent for the location is wrong.
Here the parasitic parameter that disperses is carried out abbreviation (parameter centralization) with the integrated method of signal, and the result is marked on the current schematic diagram.Like this,, just can the net distribution parasitic parameter on the domain be got information about, help the deviser to find the place of problem fast, improve design efficiency by watching the situation of the parasitic parameter on the schematic diagram.Simultaneously, the parasitic parameter of reactionary slogan, anti-communist poster can also be extracted the net table again, be directly passed to simulator.
Summary of the invention
The objective of the invention is to: a kind of method fast is provided, helps the deviser to analyze the parasitic parameter of domain, and locate their (reactionary slogan, anti-communist poster are in schematic diagram), improve design efficiency.
Thinking of the present invention is relatively to set up a corresponding contact by LVS between domain and net table (schematic diagram), then according to the level of current design, handle the abbreviation of parasitic parameter at current level, and help to the schematic diagram the deviser to understand in the domain parasitic parameter reactionary slogan, anti-communist poster as a result behind the abbreviation the influence of each module in the current schematic diagram view.
The instrument that flow process relied on is surrounded by: LVS, parasitic parameter extract (PE), RC network yojan (RCR), schematic diagram editing machine (SE).Flow process comprises the steps: that 1. the net table of the current level of schematic diagram extracts (SE); 2. generate the domain unit and the net table unit table of comparisons (LVS); 3. 4. the parasitic parameter (PE) that extracts relevant gauze carries out abbreviation (RCR) with the parasitic parameter network of gauze and 5. the parasitic parameter reactionary slogan, anti-communist poster behind the abbreviation is returned schematic diagram (SE).
5. 1. step all be to be finished by schematic diagram editing machine (SE) with step, is responsible for finishing the extraction of current schematic diagram net table in 1., keeps the hierarchical information of current design simultaneously; Call the subsequent tool bag and finish the extraction of parasitic parameter, network abbreviation; And mark is got back in the schematic diagram.
Step is 2. by compare the corresponding relation of determining between them between the net table of domain and schematic diagram extraction, for PE provides information.
The hierarchical information that 3. step provides according to SE, extract to require and mapping table extracts, simultaneously, for the parasitic parameter that extracts can being carried out abbreviation according to the requirement of SE, merge at some nodes of net table.
4. step utilizes the information that provides among the PE, and the parasitic parameter network that disperses is carried out abbreviation according to the division of module, provides the equivalent parameter of each port.
3. merge according to the Module Division in the design and the I/O character of module port in, the method for merging is that same gauze, the end that belongs to same module, same input and output attribute are merged together (gauze of domain is changed to the wire mesh models of schematic diagram).Because be the reactionary slogan, anti-communist poster of carrying out at current level, so, have only the gauze on the current level to be arrived on the schematic diagram by reactionary slogan, anti-communist poster, the end points of dividing according to current level between the module of nesting allocation distributes and merges (as Fig. 3).
Description of drawings
Fig. 1 is the graph of a relation between the kit
Fig. 2 is the reactionary slogan, anti-communist poster process flow diagram
Fig. 3 is the synoptic diagram that gauze is carried out abbreviation according to module
Embodiment
Fig. 1 is the graph of a relation between the involved calling function bag of reactionary slogan, anti-communist poster flow process,
The SE kit, the person of sending as order calls other instrument, is accomplished to the reactionary slogan, anti-communist poster of domain to schematic diagram.
Functional description:
A) call LVS and obtain domain to the corresponding relation between the schematic diagram.
B) produce the net meter file of breaing up that band calls hierarchical path.
C) produce the command file * .sn that comprises needs extraction node, and pass to PE.
D) accept output from RCR, with the parameter reactionary slogan, anti-communist poster behind the abbreviation to schematic diagram.
The LVS kit, for providing corresponding relation between schematic diagram net table and the domain net table, two throw the net shows all to break up.
Functional description:
A) find the corresponding relation of device, net table.
B) routing information that calls with device passes to PE.
The PE kit extracts needed parasitic parameter according to the requirement of SE from domain, generate the parasitic net table of band, passs RCR with net table wound after treatment and carries out abbreviation.
Functional description:
E) accept the * .sn file that SE imports.
F) accept the * .map file that LVS exports.
G) resolve, extract the circuit node that needs reactionary slogan, anti-communist poster.
H) output file * .rcr is handled (providing port information), and pass to RCR.
The RCR kit is accepted the net meter file that PE exports, and the RC parameter between the port is carried out yojan.
Functional description:
A) net meter file to PE output carries out yojan.
B) result after the yojan is passed to SE.
Fig. 3 is the synoptic diagram of a gauze abbreviation.When passing through gauze net0 driver module A and C for analysis module B, the influence of the parasitic factor on the gauze, the part of gauze net0 in modules A among the figure can be merged into A`, and B` is the input of net0, and A` and C` are the output of gauze.
Claims (1)
1. reactionary slogan, anti-communist poster/the analytical approach of an integrated circuit diagram parasitic parameter, it has following feature: the net table that 1. extracts the current level of schematic diagram, the hierarchical relationship that keeps schematic diagram, the parasitic parameter of gauze utilizes lvs to determine the net table corresponding relation of domain and schematic diagram on the extraction domain; 2. divide the parasitic parameter that will disperse according to the module level of schematic diagram and carry out abbreviation, provide the equivalent parameter of the online parasitic parameter of each module port top-stitching of schematic diagram according to the level division of module; 3. with parasitic parameter reactionary slogan, anti-communist poster of equal value behind the abbreviation to schematic diagram, carry out emulation in order to extract the net table again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100936667A CN100414551C (en) | 2005-09-01 | 2005-09-01 | Back marking/analyzing flow for integrated circuit drawing parasitic parameter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100936667A CN100414551C (en) | 2005-09-01 | 2005-09-01 | Back marking/analyzing flow for integrated circuit drawing parasitic parameter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1924872A CN1924872A (en) | 2007-03-07 |
| CN100414551C true CN100414551C (en) | 2008-08-27 |
Family
ID=37817508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100936667A Active CN100414551C (en) | 2005-09-01 | 2005-09-01 | Back marking/analyzing flow for integrated circuit drawing parasitic parameter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100414551C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923595B (en) * | 2010-08-25 | 2012-10-24 | 清华大学 | System and method for extracting parasitic components in analog integrated circuit layout |
| CN103093016B (en) * | 2011-11-04 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | After simplifying storer, imitative net table realizes the method for mass storage emulation |
| CN103123656B (en) * | 2011-11-21 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | The anti-calibration method of load is carried out to simplification circuit meshwork list |
| CN103324768A (en) * | 2012-03-21 | 2013-09-25 | 苏州芯禾电子科技有限公司 | Quickly marking method of schematic circuit diagram |
| CN106875979B (en) * | 2015-12-11 | 2020-04-14 | 展讯通信（上海）有限公司 | Method and device for measuring pin capacitance of IP core of memory |
| CN112765916B (en) * | 2021-01-22 | 2024-02-20 | 上海华虹宏力半导体制造有限公司 | Method for generating simulation parameter netlist after integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001125934A (en) * | 1999-10-25 | 2001-05-11 | Matsushita Electric Ind Co Ltd | Layout pattern verification method and back annotation system |
| US20030188277A1 (en) * | 2001-11-09 | 2003-10-02 | Hideaki Murakami | Method of evaluating semiconductor integrated circuit to be designed in consideration of standby DC leakage current |
| CN1510737A (en) * | 2002-12-24 | 2004-07-07 | 北京艾克赛利微电子技术有限公司 | Physic design method for analog and radio frequency integrated circuit |
-
2005
- 2005-09-01 CN CNB2005100936667A patent/CN100414551C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001125934A (en) * | 1999-10-25 | 2001-05-11 | Matsushita Electric Ind Co Ltd | Layout pattern verification method and back annotation system |
| US20030188277A1 (en) * | 2001-11-09 | 2003-10-02 | Hideaki Murakami | Method of evaluating semiconductor integrated circuit to be designed in consideration of standby DC leakage current |
| CN1510737A (en) * | 2002-12-24 | 2004-07-07 | 北京艾克赛利微电子技术有限公司 | Physic design method for analog and radio frequency integrated circuit |
Non-Patent Citations (2)
| Title |
|---|
| LVS版图验证方法的研究. 石春琦，吴金，常昌远，魏同立.电子器件，第25卷第2期. 2002 |
| LVS版图验证方法的研究. 石春琦，吴金，常昌远，魏同立.电子器件，第25卷第2期. 2002 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1924872A (en) | 2007-03-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101620644A (en) | Integrated circuit design in optical shrink technology node | |
| CN109214023B (en) | Test method and device for process design toolkit | |
| CN100414551C (en) | Back marking/analyzing flow for integrated circuit drawing parasitic parameter | |
| CN107016143A (en) | The method and its system of parameter extraction | |
| CN112527587B (en) | Verification progress determining method, device, equipment and readable storage medium | |
| Martin | Cadence design environment | |
| CN105868437A (en) | Method and apparatus for capacitance extraction | |
| CN102339341B (en) | Method for automatically controlling parasitic parameter extraction precision through physical layout simulation | |
| US20070070737A1 (en) | Method and auxiliary device for creating and checking the circuit diagram for a circuit which is to be integrated | |
| CN104636324B (en) | Topic source tracing method and system | |
| KR960040230A (en) | A method and system for enabling an integrated circuit to be created and moved from one manufacturing process to another. | |
| CN104731987B (en) | A kind of dead resistance electric capacity evaluation method of early stage domain | |
| US20050108672A1 (en) | Method of generating a physical netlist for a hierarchical integrated circuit design | |
| CN105550459A (en) | ASIC design clock network extraction system | |
| CN110941932B (en) | Demand modeling and verifying method for hardware logic design | |
| JP2003233637A (en) | Power supply voltage drop simulation method and apparatus for semiconductor integrated circuit | |
| CN112214955B (en) | Method for extracting power model parameters of very large scale integrated circuit chip | |
| CN104951609B (en) | A kind of method of synchronous logic structure in processing gate level netlist | |
| CN111259616B (en) | Processing method of integrated circuit layout data | |
| CN110489814A (en) | A method of by extracting the allocation plan of data flow companion chip in code | |
| JP5229834B2 (en) | Circuit design method, circuit design system, and recording medium | |
| CN106100917B (en) | A kind of network management matching business configuration system and its data configuration method | |
| CN111783373A (en) | A topology analysis method of PSCAD simulation model | |
| Pelz | An interpreter for general netlist design rule checking | |
| JP3512531B2 (en) | Internal wiring method and apparatus for semiconductor integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: BEIJING HUADAJIUTIAN SOFTWARE CO., LTD. Free format text: FORMER OWNER: BEIJING ZHONGDIANHUADA ELEKTRON DESIGN LIMITED LIABILITY COMPANY Effective date: 20090821 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20090821 Address after: Beijing city Chaoyang District Gaojiayuan No. 1 Patentee after: Beijing Jiutian Digital Technology Co., Ltd. Address before: Beijing city Chaoyang District District No. 1 Gaojiayuan Patentee before: Beijing CEC Huada Electronic Design Co., Ltd. |
|
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 100102 Beijing city two Chaoyang District Lize Road No. 2 A block 2 layer Patentee after: Beijing Jiutian Digital Technology Co., Ltd. Address before: 100015 Beijing city Chaoyang District Gaojiayuan No. 1 Patentee before: Beijing Jiutian Digital Technology Co., Ltd. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 100102 Beijing city two Chaoyang District Lize Road No. 2 A block 2 layer Patentee after: Beijing Huada Jiutian Technology Co.,Ltd. Address before: 100102 Beijing city two Chaoyang District Lize Road No. 2 A block 2 layer Patentee before: HUADA EMPYREAN SOFTWARE Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |