CN100412749C - Timing adjustment method for memory signal and related device - Google Patents

Abstract

The invention provides a method and a related device for adjusting/calibrating timing of a memory signal. In the preferred embodiment of the present invention, a plurality of co-frequency reference signals with different phases are generated by the same phase-locked loop, and signals with different timings/delays are generated according to the trigger sampling of the reference signals, so as to adjust/calibrate the timing of the relevant signals during the operation of the memory, such as the timing of memory clock pulses, command signals, data indication signals, and the like. Therefore, the invention can avoid using the delay line to adjust the signal timing as much as possible, and reduce the negative influence of the performance drift and variation of the delay line on the timing adjustment.

Description

Memory signal timing adjustment method and related device

technical field

The present invention provides a method and a related device for adjusting the timing of memory-related signals, especially a method and a related device for adjusting the timing of memory signals by using a phase-locked loop with the same frequency and out-of-phase signals to perform trigger sampling.

Background technique

The computer system is one of the most important hardware foundations of the modern information society; improving the performance of the computer system and maintaining the correct operation of the computer has also become the research and development focus of information manufacturers.

As known to those skilled in the art, a computer system will be provided with a central processing unit, a chipset, and a memory (such as a random access memory); Programs, materials, and data required during operation can be temporarily stored in the memory. The chipset is arranged between the CPU and the memory to manage the access of the CPU (and other devices in the computer system) to the memory.

In order to manage access to the memory, the chipset is electrically connected to the memory with a bus, and various signals on the bus are used to control the data access of the memory. For example, the chipset needs to provide memory clock pulses to the memory to control the timing of the logic operation of the memory; when manipulating the memory, the chipset needs to send command signals in accordance with the timing of the memory clock pulse to control the memory to write and read data. Fetch or other memory operations (such as paging, paging, operations). When the chipset and the memory need to transmit data, other signals are also used; In addition to the data to be stored, a data indication signal should be sent to the memory in conjunction with the timing of the memory clock pulse to indicate when the memory will start receiving the data.

In order to correctly complete memory access control, the above-mentioned signals, including memory clock pulses, command signals, data signals and data indication signals, etc., must have an appropriate mutual timing relationship. For example, under the preferred mutual timing relationship, the signal trigger edges (such as rising edges) of the data indication signal and the memory clock pulse should be able to align (align), and the trigger edges of the memory clock pulse and the data indication signal should be able to trigger the memory. Receive command signals and data signals between the set-up time and hold time.

However, in practical applications, there are often many unsatisfactory factors that make it difficult for the above signals to maintain a normal mutual timing relationship. For example, when the chipset transmits electronic signals to the memory, the memory can be regarded as a circuit load of the chipset; different memory configurations will cause different circuit loads to the chipset, thereby affecting the timing of data transmission. For example, in different memory configurations, the memories connected to the same bus may contain only single-inline memory modules (SIMMs), or double-inline memory modules (double-inline memory modules). , DIMM); for the chipset, the latter configuration will form a larger circuit load, and there may be a larger delay when the signal is transmitted to the memory of this configuration. Whether the signal delay is too long or too short, it is possible that the chipset cannot maintain the correct and proper mutual timing relationship of the various signals sent by the memory.

In order to ensure that the chipset can maintain a good mutual timing relationship with the signals sent by the memory, generally speaking, when the computer system is turned on, the timing of each memory signal sent by the chipset will be adjusted to compensate for the difference between the various memory signals. Timing misalignment due to ideality factors. When adjusting the timing of memory signals in the prior art, different programmable delay lines (delay lines) are used to introduce corresponding delay times to each memory signal, so that the mutual timing relationship between each memory signal can be maintained. For example, if the trigger edge of the data indicator signal is not aligned with the trigger edge of the memory clock pulse, the delay line can be used to delay the data indicator signal, so that the delayed data indicator signal can be aligned with the memory clock pulse.

However, the prior art of using delay lines to adjust the timing also has disadvantages. Such as parameter drift in the semiconductor manufacturing process (such as uneven doping concentration), or temperature changes in the operating environment (such as using computer systems in different environments, seasons, or temperature rises caused by continuous operation of computer systems), will cause The delay time that can be introduced by each delay line drifts/varies, and the preset delay time cannot be successfully introduced into each memory signal, and the correct mutual timing relationship between each memory signal cannot be maintained as expected. Generally speaking, the programmable delay line can selectively delay the signal by 1*td, 2*td or 3*td based on a unit of preset delay time td; but due to the drift/variation of the delay time, the delay The delay time actually introduced by the line may be 1*(1-5%)td, 2*(1-5%)td, and so on. For example, when adjusting the timing of memory signals, if the chip set expects to delay a signal for K*td time (K is a certain number) to achieve the mutual timing relationship between the signals, the chip set will program a corresponding delay line to delay the signal, but due to the performance drift/variation of the delay line, the delay time actually introduced by the delay line may only be K*(1-5%)td time, and this K*5%td time The error may be enough to destroy the correct timing relationship between the various memory signals. In addition, different delay lines used to delay different signals may also have different delay time drift/variation among each other, which may also cause timing misalignment between memory signals. Moreover, the delay line may introduce negative effects such as signal jitter into the signal.

Contents of the invention

Therefore, the present invention proposes a method and a related device for adjusting the timing of memory signals by using reference signals of the same frequency and different phases, so as to overcome the disadvantages of the prior art.

The invention provides a method for adjusting the timing of a computer system memory signal, comprising the following steps: generating a plurality of reference signals with the same frequency but different phases; selecting a first reference signal from the plurality of reference signals; adjusting an output delay time of a first signal so that the first signal is delayed in output; selecting a second reference signal from the plurality of reference signals; and adjusting an output delay time of a second signal according to the second reference signal so that The second signal is delayed output, wherein the first signal is a bus transmission clock pulse (DCLK) or a command signal (CMD), and wherein the second signal is a data indication signal (DQS) or a data signal (DQ).

The present invention also provides a computer system memory signal timing adjustment circuit, including: a clock pulse generator, used to generate a plurality of reference signals with the same frequency but different phases; a multiplexer, connected to the clock pulse generator A device for receiving the plurality of reference signals with the same frequency but different phases, wherein the multiplexer selects a first reference signal from the plurality of reference signals according to a selection signal; a control module , for sending a signal; and an adjustment unit, connected to the control module and the multiplexer, for receiving a signal and delaying the output according to the first reference signal selected by the multiplexer the signal.

The present invention uses a phase-locked loop as a clock pulse generator to generate multiple reference signals with the same frequency and different phases, and the phase difference between these reference signals is equivalent to the difference in delay time. A signal obtained by triggering and sampling a given signal by using the reference signal is equivalent to a delayed signal after delaying the given signal. Using this technique, the present invention can adjust the timing of each memory signal, so that each memory signal has a correct/preferable mutual timing relationship.

Basically, the present invention can use the technology of reference signal triggered sampling to adjust the timing of the memory clock pulse and command signal; when finely adjusting the data indication signal and data signal, it can first use the technology of reference signal triggered sampling for preliminary timing adjustment, and then use the delay line for further fine-tuning.

Because the present invention can continue to use the reference signal produced by the same phase-locked loop to adjust the timing between the various memory signals, it can minimize the timing misalignment caused by delay time drift/variation between delay lines; even if the reference signal of the phase-locked loop is caused by Timing drifts due to temperature changes, but because the timing of each memory signal is adjusted according to the same set of reference signals, each memory signal will drift synchronously, and the timing relationship between them can still be properly maintained. In addition, although the present invention also utilizes the delay line when adjusting the data indicating signal and the data signal, the delay line is only used for fine-tuning the timing and does not need to introduce a long delay time, so the delay time drift of the delay line is caused by The negative impact caused can be effectively limited, and the signal jitter caused by the delay line can also be reduced.

Description of drawings

FIG. 1 is a functional block diagram of a computer system.

FIG. 2 is a schematic diagram of the timing of each memory signal when the computer system in FIG. 1 is running.

FIG. 3 is a functional block diagram of implementing the timing adjustment mechanism of the present invention in the chipset shown in FIG. 1 .

FIG. 4 is a schematic diagram of the timing of each reference signal in FIG. 3 .

Fig. 5 and Fig. 6 schematically illustrate the operation of each adjustment unit in Fig. 3 .

FIG. 7 schematically shows the process of memory signal timing adjustment with the chip set in FIG. 3 according to the present invention.

FIG. 8 schematically shows the situation in which the relevant tests in FIG. 7 are carried out.

Explanation of main component symbols

10 Computer system 12 Central processing unit

14 Graphics card 16 Peripherals

18 buffers 20 chipsets

22A-22B memory slots 24 clock pulse generators

26 Comparison module 28 Detection module

30 Control Module 32 Scanning Module

34A-34D, 35C-35D setting module

36A-36D Multiplexer

38A-38D adjustment unit 40A-40B delay line

CMD, CMDi command signal DCLK, DCLKi clock pulse

DQ, DQi data signal DQS, DQSi data indication signal

cmd1, cmd command

ta1-ta2, tb0-tb2, tc0-tc2 time points

R_1-R_N, Ra-Rd, Rc0-Rd0 reference signal

Sa-Sb, Sc1-Sc2, Sd1-Sd2 selection signal

T period

Detailed ways

Please refer to FIG. 1 ; FIG. 1 is a functional block diagram of a computer system 10 . In the computer system 10, a central processing unit 12, a chipset 20, a display card 14, each peripheral device (there may be one or more peripheral devices; a peripheral device 16 is shown as a representative among Fig. 1 ) and each memory slots (two memory slots 22A, 22B are shown in FIG. 1 as representatives). In the computer system 10, the central processing unit 12 is used to control the program execution of the computer system and the calculation of data and data; each memory slot 22A, 22B can accommodate a memory module respectively, and integrate the memory modules installed on each memory slot. A memory module (such as a dynamic random access memory module) can constitute the memory of the computer system 10 . The chipset 20 is used to manage the operation of the memory, so that the CPU 12 can access the data in the memory through the chipset 20 . Other devices, such as display card 14 and peripheral device 16 (which can be a hard disk drive, an optical drive, various add-in cards, such as network cards, etc.) used to process graphics data, can also be connected to the central processing unit 12 through the chipset 20. Data exchange with memory.

In order to manage and control the data access of the memory, the chipset 20 can be provided with one or more channels, and these channels are electrically connected to each memory slot. As shown in FIG. 1 , the chipset 20 can be electrically connected to the memory slots 22A and 22B via the bus of the same channel, and the clock pulse DCLK, the command signal CMD, the data indication signal DQS and the data signal DQ, etc. are transmitted on the bus. memory signals to control the operation of each memory module on the memory slots 22A, 22B. Among them, the clock pulse DCLK is used as a memory clock pulse to control the timing of the sequential operation of each memory module; the command signal CMD is used to transmit instructions to each memory module to control each memory module to perform necessary operations, such as in the memory module. Write (store) data in a specific address, read data, or perform memory paging (paging) operations, etc. The data signal DQ is used to transmit data for memory access; in conjunction with the transmission of the data signal DQ, the data indication signal DQS is used to indicate the timing of data signal transmission. As shown in FIG. 1 , in order to maintain the correct transmission of the clock pulse DCLK, the clock pulse DCLK is often transmitted to the memory slots 22A and 22B through a buffer (buffer) 18 for signal buffering (such as enhancing its driving force).

Please refer to FIG. 2 (and refer to FIG. 1 together); FIG. 2 is a timing schematic diagram of the above-mentioned memory signals; the horizontal axis of FIG. 2 is time. As discussed above, in order to correctly control the data access of the memory, a good mutual timing relationship between the above-mentioned memory signals must be maintained; and this correct (or preferred) mutual timing relationship is shown in the diagram of FIG. 2 face left. In this preferred timing, the triggering edge (rising edge in this example) of the clock pulse DCLK (its period is T) can trigger each memory module to sample to the most stable signal in the command signal CMD, that is, a command In the middle section, each memory module is prevented from sampling signal transitions/instabilities such as the beginning or end of a command. In addition, in this preferred timing, the rising edge of the data indication signal DQS can be aligned with the rising edge of the clock pulse DCLK; in conjunction with the rising edge and falling edge of the data indication signal DQS, each piece of data can be transmitted in the data signal DQ. In FIG. 2, it is assumed that each memory module is a double data rate (DDR, double data rate) memory module, so a piece of data can be transmitted every half cycle of the data signal DQ. However, in this preferred timing, the situation in which the memory signals cooperate with each other can be described as follows. First, at the time point tal, the memory module mounted on the memory slot can sample the received command cmd1 in the command signal CMD according to the trigger of the clock pulse DCLK. Assuming that the command cmd1 indicates that data is to be written into the memory module, the data indication signal DQS will pull out a low-level signal for a cycle T from the time point ta1 as a preamble signal, representing that the chipset 20 is about to Start transferring data. When the time point ta2 is reached, the chipset 20 cooperates with the data indication signal DQS and starts to transmit the data D1 to D4 to be written into the memory module to the memory module with the data signal DQ. Cooperating with the triggering of the rising edge and falling edge of the data indication signal, the memory module can receive the data D1 to D4 and store them.

However, due to various unfavorable factors, the above-mentioned good relationship cannot be maintained among the memory signals. As discussed earlier, different memory block configurations in the memory place different loads on the chipset and affect the timing of signal transmissions. If only one slot on the memory slots 22A, 22B is equipped with a single-in-line (SIMM) memory module, the load is lighter, and the signal transmitted to the memory module has a shorter delay; If a dual in-line (DIMM) memory module is respectively installed on the two memory slots 22A, 22B, a heavier circuit load will be formed on the chipset 20; Signals may have a long delay. These varying lengths of delay due to memory configuration can cause timing aberrations between the various memory signals. On the right side of the panel in Figure 2, what might happen with bad timing is shown. For example, due to a timing aberration between the command signal CMD and the clock pulse DCLK, when the memory module samples the command signal CMD triggered by the rising edge of the clock pulse DCLK, it may sample at the signal instability of the command signal CMD , cannot correctly receive the command cmd1. Even if the memory module receives the command cmd1 (assuming it is a write command), when the memory module starts to receive the data from the chipset, it will not be able to receive data according to the indication signal DQS because the data indication signal DQS is not aligned with the clock pulse DCLK. to the data D1 to D4 to be written. Because when the memory module receives the write command, it needs to receive the data to be written within a certain period of time to write the data correctly; if the memory module starts to transmit the data to the memory module before receiving the write command, or The data is transmitted to the memory module after a long delay after the memory module receives the write command, and the memory module cannot write the data correctly.

In order to avoid timing irregularities among the memory signals, a related timing adjustment mechanism is provided in the chipset so as to perform timing adjustment of the memory signals when the computer system is turned on. Please refer to FIG. 3 (and refer to FIG. 1 together); FIG. 3 is a functional block diagram of an embodiment of implementing timing adjustment by the chipset 20 of the present invention. Chipset 20 is provided with a control module 30, a clock pulse generator 24, multiplexers 36A to 36D, adjustment units 38A to 38D, setting modules 34A to 34D, 35C to 35D, programmable delay lines 40A to 40B, and the detection module 28 , the comparison module 26 and the scanning module 32 . The control module 30 is used to control the functions of the chipset 20, and generate the clock pulse DCLKi, the command signal CMDi, the data indication signal DQSi and the data signal DQi inside the chipset, and the adjustment units 38A to 38D are used to adjust these signals respectively. The clock pulse DCLK, the command signal CMD, the data indicator signal DQS and the data signal DQ are correspondingly generated as memory signals output to each memory module. The clock pulse generator 24 can be a phase-locked loop, such as a phase-locked loop constructed by a ring oscillator (ring oscillator), used to generate N reference signals R_1 to R_N with the same frequency and different phases; The multiplexers 36A to 36D can respectively receive a selection signal Sa to Sb, Sc1 to Sc2 to select a reference signal from the N reference signals according to the indication of the selection signal. Collective clock pulse generation circuit 24, each multiplexer 36A to 36D, each adjustment unit 38A to 38D, control module 30, each setting module, detection module 28, comparison module 26, scanning module 32, each delay line 40A And 40B etc., just can realize a computer system memory signal timing adjustment circuit, reach the purpose of the present invention to adjust memory signal timing.

According to the reference signals Ra and Rb respectively selected by the multiplexers 36A to 36B, the adjustment units 38A to 38B can adjust the timing of the clock pulses DCLKi and CMDi respectively. In addition, in order to fine-tune the timing of the data indication signal DQSi and the data signal DQi, the timing of the reference signals Rc0 and Rd0 selected by the multiplexers 36C and 36D can be further delayed through a programmable delay line 40A and 40B respectively, The delayed reference signals Rc and Rd are generated; and the adjustment units 38C and 38D can adjust the timing of the data indication signals DQSi and DQi according to the reference signals Rc and Rd respectively. The delay lines 40A and 40B respectively set the length of the delay time introduced into the signal according to the control of the selection signals Sc2 and Sd2 . In addition, the selection signals Sa to Sb, Sc1 to Sd1 and Sc2 to Sd2 are respectively generated by the setting modules 34A to 34D, 35C to 35D. These setting modules can be registers; according to the content of the temporarily stored setting data, these setting modules can control corresponding multiplexers or delay lines through corresponding selection signals. The content of the setting data in these setting modules can be set by the control module 30 , the detection module 28 and the scanning module 32 .

In order to further illustrate the operation of various related circuits when the chipset 20 performs timing adjustment, please refer to FIG. 4 (and refer to FIG. 3 together); the timing schematic diagram of FIG. reference signals R_1 to R_N, and the horizontal axis in FIG. 4 is time. The periods of these reference signals are the same as T (that is, the period of the memory clock pulse), but the phases of each reference signal are evenly distributed in 360 degrees, and the phase difference between each reference signal is expressed as a delay time. For example, compared to the rising edge of the first reference signal R_1, the rising edge of the nth reference signal R_n has a delay time of (n−1)*T/N, as shown in FIG. 4 . In a preferred embodiment of the present invention, the clock pulse generator 24 can generate 8 reference signals (that is, N=8).

The situations in which the adjustment units adjust the timing according to the reference signals are shown in FIGS. 5 to 6 . Please refer to FIG. 5 first (and refer to FIGS. 3 and 4 together); FIG. 5 illustrates the operation of the adjusting unit 38B. One or more flip-flops can be provided in the adjustment unit 38B, and these flip-flops can sample the input signal Si according to the trigger of the reference signal Ri, and obtain the corresponding output signal So. As shown in FIG. 5 , if the input signal Si has three pieces of data Si0 to Si2 with a period T in sequence starting from the time point tb0, and the reference signal Ri is the reference signal R_3, the adjustment unit 38B will follow the rise of the reference signal R_3 The corresponding output signal So is sequentially sampled from the time point tb1 by edge triggering, so that the output signal So starts to transmit the data Si0 to Si2 after the time point tb1. That is to say, when the adjustment unit 38B is triggered by the reference signal R_3 , its output signal So is equivalent to the signal generated by delaying the input signal Si from the time point tb0 to the time point tb1 . Similarly, for the same input signal Si, if the reference signal R_i received by the adjustment unit 38B is the reference signal R_7 in FIG. The time point tb0 is delayed to the time point tb2; and the time difference between the time points tb1 and tb2 corresponds to the phase difference between the reference signals R_3 and R_7. It can be seen that selecting different reference signals to trigger the adjustment unit 38B is equivalent to delaying the output signal Si by different times; and the present invention uses this principle to adjust the timing of each memory signal.

Please refer to Fig. 6 (and refer to Fig. 3, 4 together); What Fig. 6 illustrates is the operation situation of adjustment unit 38D; Adjustment unit 38D also accepts the trigger of a reference signal R_i and samples its input signal Si, to adjust The timing of the input signal Si forms the output signal So. As shown in the embodiment of FIG. 6 , when the adjustment unit 38D actually operates, its input signal Si may include two signals Si_H and Si_L; these two signals have a time difference of half a period T between each other, and carry For data with a long period T (such as data D1 and D3 in signal Si_H and signals D2 and D4 in signal Si_L), these two signals Si_H and Si_L can equivalently form an input signal Si with half-period data. When the adjustment unit 38D is triggered by the reference signal R_i, it will sample the signal Si_H on the rising edge of the reference signal R_i, and sample the signal Si_H on the falling edge of the reference signal (or the rising edge of another signal with a phase difference of 180 degrees from the reference signal R_i edge) to sample the signal Si_L, and alternately generate the output signal So according to the sampling results triggered by the rising edge and the falling edge.

For example, when the reference signal R_i is the reference signal R_3 in FIG. 4 , the rising edge of the reference signal R_3 at the time point tc1 will trigger the adjustment unit 38D to start sampling the data D1 in the signal Si_H, and then the falling edge of the reference signal R_3 will be Sample signal D2 in Si_L; and so on. The adjustment unit 38D combines the signals sampled by the rising edge and the falling edge to form a corresponding output signal So. It can be seen from FIG. 6 that when the adjustment unit 38D is triggered by the reference signal R_3 , the output signal So is the result of delaying the input signal Si from the time point tc0 to the time point tc1 . Similarly, if the adjusting unit 38D is triggered by the reference signal R_7 , the corresponding output signal So is the result of delaying the input signal Si from the time point tc0 to tc2 . In other words, even if the input signal Si carries half-period T data, the present invention can use the reference signal to adjust its timing.

Similar to the adjustment units 38B and 38D in FIG. 5 and FIG. 6 , the adjustment units 38A and 38C can also use similar principles to adjust the signal timing of the clock pulse DCLKi and the data indication signal DQSi respectively according to each reference signal, and correspondingly generate a clock Pulse DCLK and data indication signal DQS. As for the process of adjusting these memory signals in the present invention, FIG. 7 can be used to illustrate; please refer to FIG. 7 (and refer to FIG. 1 and FIG. 3 together). The process 100 in FIG. 7 is an embodiment of memory signal calibration performed by the chipset 20 of the present invention. The process 100 has the following steps:

Step 102: start. The process 100 may be performed when the computer system 10 ( FIG. 1 ) is turned on, so as to adjust the timing relationship among the memory signals.

Step 104: Use the clock pulse generator 24 (that is, the phase-locked loop, FIG. 3 ) to generate a plurality of reference signals R_1 to R_N with the same frequency and different phases.

Step 106: Select an appropriate reference signal to adjust the timing of the clock pulse DCLKi and the command signal CMDi, so that the corresponding output clock pulse DCLK and the command signal CMD have a good mutual timing relationship. When the computer system 10 is powered on, it will detect the configuration of the memory to know whether memory modules are installed in each memory slot on the same bus (channel), whether a single-sided or double-sided memory module is installed, and the like. According to the memory configuration, the equivalent load caused by the memory configuration to the chipset can be inferred, and the timing impact of the equivalent load on each memory signal can be inferred. When step 106 is performed, the detection module 28 ( FIG. 3 ) in the chipset 20 can also estimate which reference signal should be selected to compensate for the timing impact caused by the memory configuration according to the detection result of the memory configuration, and set it accordingly. The setting modules 34A, 34B are used to control the corresponding multiplexers 36A, 36B to select appropriate reference signals, so that the corresponding adjustment units 38A, 38B can adjust the timing of the clock pulse DCLKi and the command signal CMDi according to these reference signals, Compensate for possible timing impacts caused by memory configuration.

In actual implementation, chipset R&D manufacturers can first estimate/test the timing impact caused by various memory configurations, estimate which memory configuration should be matched with which reference signal to compensate for its timing impact, and establish this information Built into the detection module as a look-up table. In this way, the detection module 28 can use a look-up table to select an appropriate reference signal according to the actual memory configuration during operation, and adjust the timing relationship between the clock pulse DCLK and the command signal CMD.

Step 108: After adjusting the timing relationship between the clock pulse DCLK and the command signal CMD, the timing of these two signals can be used as a reference to further adjust the timing of the data indicating signal DQSi and the data signal DQi, so that the output data indicating signal DQS/data signal DQ and the clock pulse DCLK/command signal CMD generally have a good mutual timing relationship. When performing step 108, the scanning module 32 first fixes the delay time introduced by each delay line 40A, 40B through the setting modules 35C, 35D, and controls the multiplexers 36C, 36D to try to select the same reference signal to adjust the timing of the data indication signal DQSi and the data signal DQi, and then the control module 30 can issue instructions to the memory (via the clock pulse DCLK and the command signal CMD) to write specific data in conjunction with the data indication signal DQ/data signal DQ to the memory, and read the data from the memory again; and the comparison module 26 can compare whether the read data is consistent with the original written data. If the read data does not match the written data, it means that the timing of the data indication signal DQS/data signal DQ and the timing of the clock pulse DCLK/command signal CMD cannot be matched correctly, resulting in an error in the process of data writing. At this point, the scanning module 32 can select another reference signal to readjust the timing of the data indication signal DQS/data signal DQ, and write/read data to the memory again, and test to see if this reference signal can enable The timing of the data indication signal DQS/data signal DQ is coordinated with the timing of the clock pulse DCLK/command signal CMD. If the written data matches the read data, it means that this reference signal can make the data indication signal DQS/data signal DQ and the clock pulse DCLK/command signal CMD have a good timing relationship, and can be written/read through this test.

As discussed above, when the clock pulse DCLK/command signal CMD triggers the memory module to receive the write command, the data to be written must be transmitted to the memory module with the data indication signal DQS/data signal DQ within a certain time limit. Or too late data transmission will cause writing failure, so according to the above writing/reading test, it can be judged whether the timing of the data indication signal DQS/data signal DQ can match with other memory signals.

When actually performing step 108, the scanning module 32 can sequentially select all N reference signals, respectively write/read data for each reference signal, and test to see the data indication signal DQS adjusted by the reference signal /Whether the data signal DQ can make the process of data writing/reading go smoothly. Please refer to FIG. 8 ; FIG. 8 illustrates the situation where the scanning module 32 performs the (n-1)th, nth, and (n+1)th writing/reading tests successively. Basically, the scanning module 32 performs these tests sequentially, but in order to compare the performance of each test, in FIG. 8 , the timing of each related signal during each test is aligned and displayed according to the clock pulse DCLK/command signal CMD. When these tests are performed sequentially, the scanning module 32 will use the reference signals R_(n-1), R_n and R_(n+1) to adjust the timing of the data indication signal DQS/data signal DQ respectively, to match the timing of the command signal CMD The write command cmd controls the memory module to receive data D1 to D4 in the data signal DQ. As shown in Figure 8, when different reference signals are selected, the timing of the data indicating signal DQS/data signal DQ will gradually increase its delay time; and the timing difference between the two tests of the data indicating signal DQS/data signal is quite at N/T.

After the writing/reading test is performed with all reference signals in a scanning manner, the scanning module 32 can select a preferred reference signal from among the reference signals that have passed the test, and set the setting module according to this reference signal 34C, 34D, so that the multitasking modules 36C, 36D can fixedly select this preferred reference signal during subsequent operation.

Step 110: Use the delay lines 40A and 40B to fine-tune the timing of the data indicating signal DQS/data signal DQ respectively. In the embodiment of FIG. 3, the present invention uses delay lines 40A, 40B to respectively delay the reference signals selected by the multiplexers 36C, 36D, and the delay introduced to the reference signals will pass through the adjustment units 38C, 38D Respond to the data indication signal DQS/data signal DQ. Similar to the way of step 108, the scanning module 32 can sequentially select different setting values to set the programmable delay lines 40A, 40B, so that the delay lines 40A, 40B can provide different delay times in sequence, and for each Perform a write/fetch test on the delay time, fine-tune the timing of the data indication signal DQS/data signal DQ according to the test results, that is, select an optimal delay time, and set the corresponding set value to the set value The modules 35C and 35D enable each memory signal (clock pulse DCLK, command signal CMD, data indication signal DQS and data signal DQ) to achieve a preferred mutual timing relationship.

Step 112 : End the timing adjustment process, and complete the booting procedure of the computer system 10 . Thereafter, the chipset 20 can control each multiplexer and delay line according to the preferred values set by each setting module, select the preferred reference signal and delay time to adjust the timing of each memory signal respectively, so that each memory signal A good (preferred) mutual timing relationship can be maintained during subsequent operation of the computer system.

To sum up, the present invention adjusts the timing of each memory signal according to multiple out-of-phase reference signals of the same phase-locked loop; compared with the prior art of adjusting timing with a delay line, the technology of the present invention can effectively avoid delay line delay The negative impact of time drift/variation on signal timing is also effective in reducing signal jitter introduced by delay lines in individual memory signals. Although the present invention can also utilize the delay line to fine-tune the timing of the memory signal, the present invention can minimize the delay time introduced by the delay line; in a preferred situation, the delay time introduced by the delay line should be less than T/N( T is the period of the clock pulse DCLK, and N is the number of reference signals); because, in the present invention, the delay time difference formed because of the phase difference between each reference signal is exactly T/N, exceeds the delay time of T/N. This can be achieved using the selection of the reference signal. In other words, because the present invention is based on the timing adjustment based on the reference signal, it can minimize the dependence on the delay line in the timing adjustment mechanism and overcome the disadvantages of the prior art. In addition to adjusting the timing of memory signals, the technical spirit of the present invention can also be widely used in timing adjustment of other sequential control circuits. Each module and adjustment unit in Fig. 3 of the present invention can be realized by means of firmware or hardware; for example, the functions of the control module, the comparison module, the detection module and the scanning module can be realized by the same controller; each The adjustment unit can be realized by hardware logic circuit.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (11)

1. A method for adjusting the timing of a computer system memory signal, comprising the following steps: Generate multiple reference signals with the same frequency but different phases; selecting a first reference signal from the plurality of reference signals; adjusting an output delay time of a first signal according to the first reference signal, so that the first signal is delayed in output; selecting a second reference signal from the plurality of reference signals; and adjusting an output delay time of a second signal according to the second reference signal, so that the second signal is delayed in output, Wherein, the first signal is a bus transmission clock pulse (DCLK) or a command signal (CMD), and wherein the second signal is a data indication signal (DQS) or a data signal (DQ). 2. The method for adjusting the timing of computer system memory signals as claimed in claim 1, further comprising the step of: referring to a comparison table according to the memory configuration of the computer system when starting up, selecting the first reference signal. 3. The method for adjusting the timing of a computer system memory signal as claimed in claim 1, further comprising the step of: sending an instruction to the memory according to the delayed output of the bus transmission clock pulse and the instruction signal, and cooperating with the delayed output The subsequent data indication signal and data signal write a specific data into the memory. 4. The adjustment method of computer system memory signal timing as claimed in claim 3, wherein, also comprise the step: read described specific data written in described memory, in order to compare described write specific data and read Whether specific data match. 5. The method for adjusting the timing of a computer system memory signal as claimed in claim 4 , wherein, if the specific data for writing is not consistent with the specific data for reading, then the second reference signal is reselected. 6. The method for adjusting the timing of a computer system memory signal as claimed in claim 1, further comprising the step of: fixing a delay time for fine-tuning the output delay time of the second signal. 7. A computer system memory signal timing adjustment circuit, comprising: a clock pulse generator for generating multiple reference signals with the same frequency but different phases; a multiplexer, connected to the clock pulse generator, to receive the plurality of reference signals with the same frequency but different phases, wherein the multiplexer will select from the plurality of reference signals according to a selection signal selecting a first reference signal from the reference signals; a control module for sending a signal; An adjustment unit, connected to the control module and the multiplexer, is used to receive the signal and output the signal with delay according to the first reference signal selected by the multiplexer. 8. The computer system memory signal timing adjustment circuit as claimed in claim 7, wherein the signal sent by the control module is a bus transmission clock pulse (DCLK) or a command signal (CMD). 9. The computer system memory signal timing adjustment circuit as claimed in claim 7, further comprising: a setting module, connected to the multiplexer, providing the selection signal for selecting the first reference signal; and a detection module, connected to the setting module, used to detect the memory configuration of the computer system when it is turned on, so that the setting module determines the selection signal. 10. The computer system memory signal timing adjustment circuit as claimed in claim 7, further comprising: A comparison module, connected to the control module, for comparing whether the delayed output signal is correct; A scanning module, connected to the control module, used to reselect the first reference signal from the plurality of reference clock pulses when the comparison result is incorrect; A first setting module, connected between the scanning module and the multiplexer, outputs a selection signal for selecting the first reference signal; A delay line is connected between the multiplexer and the adjustment unit, and the delay line has a fixed delay time for further delaying the clock pulse of the first reference signal selected by the multiplexer a fixed size of said delay time; and A second setting module, connected between the scanning module and the delay line, is used to set the delay time. 11. The computer system memory signal timing adjustment circuit as claimed in claim 10, wherein the signal sent by the control module is a data indicating signal (DQS) or a data signal (DQ).

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