CN100410911C - Interrupt controller, interrupt signal preprocessing circuit and interrupt control method thereof - Google Patents

Abstract

The present invention relates to an interrupt controller of a computer system conforming to an Advanced Configuration and Power Interface (ACPI) power management standard, and an interrupt signal preprocessing circuit for the interrupt controller and an interrupt control method thereof, which can save power consumption when the computer system conforming to the ACPI power management standard is normally operated. According to an aspect of the present invention, there is provided an interrupt control method of a computer system, comprising the steps of: when the interrupt input signal exists in the system, enabling a gating clock signal in the interrupt control process, carrying out proper processing on the interrupt input signal, and introducing the processed interrupt input signal into the advanced programmable interrupt controller for normal interrupt processing; when the interrupt processing ends, the strobe clock signal is pulled low to a low level.

Description

Interrupt controller, interrupt signal preprocessing circuit and interrupt control method

technical field

The present invention generally relates to an interrupt control mechanism in a computer system, and more particularly, to an interrupt controller in a computer system conforming to the Advanced Configuration and Power Interface (ACPI) power management standard, and an interrupt signal for the interrupt controller The preprocessing circuit and its interrupt control method can save power consumption when the computer system conforming to the advanced configuration and power interface power management standard works normally.

Background technique

Computer system is one of the most important hardware infrastructures in modern information society. In addition to the pursuit of performance, modern computer systems also need to pay attention to the reduction of energy consumption, especially for notebook computers. Reducing energy consumption can prolong the battery life after each charge. Therefore, modern computer manufacturers also regard reducing energy consumption as one of the key points in the research and development of computer systems.

ACPI is a power management standard jointly developed by Intel, Microsoft, and Toshiba. The intention is to allow the system to fully control power management. It allocates energy consumption to peripherals on demand, making the system more power-efficient.

As a bridge between the BIOS and the operating system, ACPI sets a variety of energy-saving states for different objects, such as the GX state for the global system, the sleep state SX for the global sleep state G1, and the processor's state for the G0 state. A power consumption and performance state CX, and a DX state for power saving states of the device. Among them, X is a number 0, 1, 2, 3, etc., representing different degrees of energy-saving status. When X is 0, it refers to the normal working status.

The S0 state is a computer state in which the computer system dispatches and executes user code (application program) threads. In the S0 state, the power consumption state of the external device often changes. In the S0 state, the system responds to the interruption of external events or internal events in real time.

When the computer system works in the S0 state, the interrupt controller in the system is in the working state of monitoring and processing interrupts, so the strobe clock signal of the interrupt controller always exists. Moreover, the interrupt controller can ignore noises such as burrs in the interrupt signal, identify the real interrupt signal, and can identify whether it is a level-triggered interrupt or an edge-triggered interrupt. When the interrupt processing ends, the interrupt is automatically cleared. (For the above content, please refer to the advanced configuration and power interface technical specifications)

However, when the computer system works in the S0 state, interrupts do not occur frequently. Therefore, the interrupt controller must be in the working state of monitoring the occurrence of interrupts. At this time, the strobe clock signal of the interrupt controller needs to exist at the same time so that it can be detected in time. To the interrupt and process it, otherwise it will not be able to monitor the occurrence of the interrupt. Although such an approach can achieve the effect of monitoring at any time, it also consumes excess power.

Contents of the invention

In view of this, the object of the present invention is to provide an interrupt control circuit, which can turn off the gate clock signal of the interrupt controller when the system works normally without interruption, and can restore the gate clock signal when an interrupt occurs, Wake up the interrupt handler of the interrupt controller.

According to one aspect of the present invention, an interrupt controller for a computer system is provided, including n interrupt signal preprocessing circuits, receiving n interrupt input signals and corresponding interrupt level valid selection determination signals, and outputting nth An output signal and n second output signals; or an arithmetic unit, which performs an OR operation on the n second output signals; a clock module receives the clock signal generated by the phase-locked module of the computer system chipset, and generates a gate clock signal, The output of the OR operator is connected to the clock module for controlling the generation of the strobe clock signal; the APIC module has n interrupt entries, receives the corresponding n first output signals, and receives the strobe clock signal generated by the clock module. Among them, when there is an interrupt input signal, or the output of the arithmetic unit is high, the strobe clock signal input terminal of the APIC module receives a normal strobe clock signal and performs interrupt processing; when there is no interrupt input signal, or The output of the arithmetic unit is low level, and the gate clock signal received by the gate clock signal input terminal of the APIC module is pulled down to low level.

According to one aspect of the present invention, there is provided an interrupt signal pre-processing circuit used in the interrupt process of a computer system, that is, the interrupt signal pre-processing circuit used in the above-mentioned interrupt controller, including: a first inverter, which converts the interrupt Inversion of the input signal; the first multiplexer, receiving the interrupt input signal and the interrupt input signal inverted by the first inverter; the first latch, latching the output of the first multiplexer; the register, in the gating Under the control of the clock, the output of the first latch is stored; the second inverter inverts the output of the register; the second multiplexer receives the output signal of the register and the output signal of the second inverter, and its output signal As the first output signal of the interrupt signal preprocessing circuit; the second latch, its signal input terminal and clock input terminal are respectively connected to the output terminal of the register; the first OR gate, the output of the first multiplexer and the output of the register The output is ORed, the output of the first OR gate is connected to the clock input of the first latch; the second OR gate, the output of the first latch is ORed with the output of the second latch, and the second The output signal of the OR gate is used as the second output signal of the interrupt signal preprocessing circuit. Wherein, the reset terminal of the first latch and the reset terminal of the register receive the reset signal of the system bus, and the reset terminal of the second latch receives a pulse reset signal, wherein, when there is an interrupt input signal, the second output signal follows When the interrupt input signal is valid, it becomes high level, enabling the strobe clock signal; when the pulse reset signal resets the second latch, the second output signal becomes low level, and the strobe clock signal is pulled to low level.

According to one aspect of the present invention, an interrupt control method of a computer system is provided, comprising the steps of: when it is judged that there is an interrupt input signal in the system, making the clock module used for interrupt control in the system generate an interrupt controller in the interrupt control process The strobe clock signal of the interrupt input signal is properly processed, and the processed interrupt input signal is introduced to the advanced programmable interrupt controller for normal interrupt processing; when the interrupt processing is completed, the strobe clock signal is pulled low to low level.

Description of drawings

The above and other objects and features of the present invention will become more apparent through the following description in conjunction with the accompanying drawings exemplarily showing an example, wherein:

1 is a schematic diagram of an interrupt controller for a computer system according to one embodiment of the present invention;

2 is a schematic diagram of an interrupt signal preprocessing circuit for a computer system according to an embodiment of the present invention;

3A-3C are timing diagrams of the interrupt signal preprocessing circuit in FIG. 2; and

FIG. 4 is a flowchart of an interrupt control method for a computer system according to an embodiment of the present invention.

Detailed ways

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram of an interrupt controller for a computer system according to one embodiment of the present invention.

A conventional interrupt controller in a computer system is generally set on the south bridge chip of the chipset or on a single chip integrating the north and south bridges. Therefore, the interrupt signal preprocessing circuit of the present invention can be applied not only to the traditional south bridge chip, but also to the traditional north bridge integrated chip.

As shown in Figure 1, the interrupt controller 1 according to the present invention includes a CLK module 410, an advanced programmable interrupt controller APIC (Advanced Programmable Interrupt Controller) module 420 (generally the APIC module 420 has 24 interrupt entries), and respectively in the APIC Interrupt signal preprocessing circuits 430_1 . . . 430_24 are connected in series at each interrupt entry of the module 420 .

The north bridge chip in the computer system (for north-south bridge integrated chip) or the PLL (phase-locked) module in the south bridge chip self produces clock signal CLK to the CLK module 410 of the south bridge chip, and the CLK module 410 produces suitable strobe clock signal I4 For the APIC module 420 and the interrupt signal preprocessing circuit 430_1...430_24, the external or internal interrupt input signal is respectively input to the input terminal I1_1 of the interrupt signal preprocessing circuit 430_1...430_24.. .I1_24, indicating that the external or internal interrupt input signals I1_1...I1_24 are active high or active low input signals respectively input to the input of the interrupt signal preprocessing circuit 430_1...430_24 Terminals I2_1...I2_24. The input terminals I3_1...I3_24 of the interrupt signal preprocessing circuits 430_1...430_24 are respectively input to the internal latches of each interrupt signal preprocessing circuit, respectively, when the APIC interrupt processing is completed and the status is cleared The last generated pulse signal is at least longer than 1 clock cycle, which is normally low level, and is a high level pulse signal only when the internal latch is reset. The input terminal I4_1...I4_24 of the interrupt signal preprocessing circuit 430_1...430_24 is the strobe clock signal of the APIC, and the I5_1...I5_24 is the PCIRST signal. When the whole system is powered on Perform reset action. The outputs O1_1...O1_24 of the interrupt signal preprocessing circuits 430_1...430_24 are respectively connected to the interrupt signal input terminals of the APIC, and the output O2_1 of the interrupt signal preprocessing circuits 430_1...430_24. .....O2_24 is connected to the CLK module 410 after performing the OR operation, so as to control the normal operation of the strobe clock signal or be pulled down to a low level, thereby generating a suitable strobe clock signal I4 to the APIC module 420 and an interrupt signal Preprocessing circuits 430_1 . . . 430_24.

When the system works normally, only when all interrupt signal input terminals of the interrupt controller 1 have no interrupt signal input, the strobe clock signal will be pulled down to low level, thereby saving power.

The interrupt signal preprocessing circuits 430_1...430_24 adopted by the interrupt controller 1 in FIG. 1, wherein the internal circuit of each interrupt signal preprocessing circuit is shown in FIG. The processing circuit 2 includes inverters 10 , 90 , multiplexers 20 , 50 , buffers 70 , 110 , OR gates 80 , 100 , latches 30 , 60 , and registers 40 .

The signal I1 is an interrupt input signal generated inside or outside the computer system, and can be a level (high level or low level) triggered interrupt or an edge triggered interrupt. The signal I1 is input to one input end of the multiplexer 20 , and the signal I1 is inverted by the inverter 20 and then input to the other input end of the multiplexer. The signal I2 is an interrupt level active selection determination signal indicating that the interrupt input is active at high level or active at low level, and is input to the selection control terminals of the multiplexers 20 and 50 . When the signal I2 is at a high level, it indicates that the interrupt input signal is active at a high level, and the multiplexer 20 selects the signal I1 as an output, and the output of the multiplexer 50 selects the register 40 as the output signal O1 of the interrupt signal preprocessing circuit 2; when the signal When I2 is low level, it indicates that the interrupt input signal is active at low level, the multiplexer 20 selects the inverted signal I1 as the output, and the multiplexer 50 selects the output of the register 40 inverted by the inverter 90 as the interrupt signal The output signal O1 of the preprocessing circuit 1. The output signal O1 is an interrupt input signal that will enter the Advanced Programmable Interrupt Controller (APIC) of the computer system after passing through the interrupt signal preprocessing circuit 2, and can be a level (high level or low level) trigger interrupt or an edge trigger interruption.

The output of the multiplexer 20 is input to the input terminal of the latch 30 through the buffer 70 . Meanwhile, the output of the multiplexer 20 is also connected to one input terminal of the OR gate 80 , the other input of the OR gate 80 is from the output terminal of the register 40 , and the output of the OR gate 80 is connected to the clock input terminal of the latch 30 . The output end of the latch 30 is connected to the input end of the register 40, and the output end of the register 40 is connected to an input end of the multiplexer 50, and the output of the register 40 is input to the multiplexer 50 after being inverted by the inverter 90. another input.

The output of the register 40 is input to the input terminal of the latch 60 through the buffer 110 . Meanwhile, the output of the register 40 is also connected to the clock input of the latch 60, the output of the latch 60 is connected to one input of the OR gate 100, and the output of the latch 30 is also connected to the other of the OR gate 100. The input terminal, the output of the OR gate 100 is used as the output signal O2 of the interrupt signal preprocessing circuit 2, the output signal O2 is the gating clock enable signal of the APIC when the system is working normally, and when the signal O2 is high level, the gating clock The signal works normally. When the signal O2 is low level, the strobe clock signal is pulled down to low level, so that when the system works normally without interrupt input, there is no strobe clock signal output, so as to achieve the purpose of energy saving.

The interrupt signal preprocessing circuit 2 also has three input signals I3, I4 and I5. The signal I3 is input to the reset terminal of the latch 60, which is a pulse signal at least longer than one clock period generated after the APIC interrupt processing is completed and the state is cleared. The normal state is low level, and only when the reset latch 60 Only when it is a high-level pulse signal.

Signal I4 is the strobe clock signal for the APIC and is input to the clock input of register 40 .

The signal I5 is a PCIRST signal, which is input to the reset terminals of the latch 30 and the register 40, and resets when the entire system is powered on.

FIG. 3 is a working sequence diagram of the interrupt signal preprocessing circuit 2 in FIG. 2 . The working process of the interrupt signal preprocessing circuit 2 will be described below in conjunction with the sequence diagram of FIG. 3 . Figure 3A shows the case where the interrupt input signal is active at high level; Figure 3B shows the case where the interrupt input signal is active at low level;

In FIG. 3A , the interrupt input signal I1 is an active-high interrupt trigger signal, and the signal I2 is therefore a high-level signal. The initial state of I1 is low level, and the multiplexer 20 selects I1 as an output signal. Under the reset action of the signal I5, the initial outputs of the latch 30 and the register 40 are low level, and the multiplexer 50 selects the output of the register 40 as the output O1 of the interrupt signal preprocessing circuit, and the signal O1 is low level. Under the reset action of the signal I3, the initial output of the latch 60 is low level, and the output O2 is low level, then there is no strobe clock signal output at this time, and the signal I4 is pulled down to low level.

When I1 changes from low level to high level, the output of multiplexer 20 becomes high level, then the output of OR gate 80 becomes high level, and the clock signal of latch 30 is valid, thus latch 30 The input of the input is the high level output by the buffer 70, the output of the latch 30 becomes high level, then the output of the OR gate 100 becomes high level, thereby the output O2 becomes high level, so that the gate clock signal I4 works normally, and then the output of register 40 becomes high level, the output of multiplexer 50 becomes high level, the output O1 becomes high level, the output of latch 60 becomes high level, enters normal Interrupt handling.

When the interrupt ends, when I1 changes from high level to low level, the output of multiplexer 20 becomes low level, and at this moment, because the output of register 40 still remains high level, so the output of OR gate 80 is still High level, the clock signal of the latch 30 is valid, so the output of the latch 30 is the low level output by the buffer 70, the output of the latch 30 becomes low level, and the output of the register 40 becomes low Level, the output of the multiplexer 50 becomes low level, the signal O1 becomes low level, and the output of the OR gate 80 becomes low level at the same time, making the clock signal of the latch 30 invalid, and the clock signal of the latch 30 The output is latched at a low level, and the output of the latch 60 is locked at a high level at the same time, then the output of the OR gate 100 is still at a high level, and the strobe clock signal I4 still works normally until the signal I3 that appears after the interrupt processing ends After the latch 60 is reset, the output of the OR gate 100 becomes low level, and the gate clock signal I4 is pulled to low level.

In FIG. 3B , the interrupt input signal I1 is an active-low interrupt trigger signal, and the signal I2 is therefore a low-level signal. The initial state of I1 is high level, and the multiplexer 20 selects the output of the inverter 10 as the output signal. Under the reset action of the signal I5, the initial output of the latch 30 and the register 40 is low level, the multiplexer 50 selects the output of the inverter 90 as the output O1 of the interrupt signal preprocessing circuit, and the signal O1 is high level . Under the reset action of the signal I3, the initial output of the latch 60 is low level, and the output O2 is low level, then there is no strobe clock signal output at this time, and the signal I4 is pulled down to low level.

When I1 changes from high level to low level, the output of multiplexer 20 becomes high level, then the output of OR gate 80 becomes high level, and the clock signal of latch 30 is valid, thus latch 30 The input of the input is the high level output by the buffer 70, the output of the latch 30 becomes high level, then the output of the OR gate 100 becomes high level, thereby the output O2 becomes high level, so that the gate clock signal I4 works normally, and then the output of register 40 becomes high level, the output of multiplexer 50 becomes low level, the output O1 becomes low level, the output of latch 60 becomes high level, and enters normal Interrupt handling.

When the interrupt ends, when I1 changes from low level to high level, the output of multiplexer 20 becomes low level, at this moment, because the output of register 40 still remains high level, so the output of OR gate 80 is still High level, the clock signal of the latch 30 is valid, so the output of the latch 30 is the low level output by the buffer 70, the output of the latch 30 becomes low level, and the output of the register 40 becomes low Level, the output of the multiplexer 50 becomes high level, the signal O1 becomes high level, and the output of the OR gate 80 becomes low level at the same time, so that the clock signal of the latch 30 is invalid, and the clock signal of the latch 30 The output is latched at a low level, and the output of the latch 60 is locked at a high level at the same time, then the output of the OR gate 100 is still at a high level, and the strobe clock signal I4 still works normally until the signal I3 that appears after the interrupt processing ends After the latch 60 is reset, the output of the OR gate 100 becomes low level, and the gate clock signal I4 is pulled to low level.

It can be seen from the waveform diagrams of FIGS. 3A and 3B that the output signal O1 is a repeating signal lagging behind I1 by 1 clock period, and the time period for the gate clock signal I4 to work normally is longer than the existence period of the output signal O1. Therefore, the interrupt processing situation when the output signal O1 is connected to the interrupt signal input terminal of the APIC is the same as the conventional interrupt processing situation when the signal I1 is directly connected to the interrupt signal input terminal of the APIC. That is to say, the interrupt signal preprocessing circuit in Fig. 2 has no effect on the interrupt processing of the system except that the strobe clock signal I4 is pulled low when there is no interrupt input, so as to achieve the technical effect of power saving.

In FIG. 3C , the interrupt input signal I1 is a false interrupt input signal, that is, the interrupt input signal is a noise signal such as a glitch. According to the analysis of Figures 3A and 3B above, no matter whether the signal I2 is high or low, the output signal O1 is a repeating signal lagging behind I1 by 1 clock cycle. For the APIC interrupt mechanism, when the interrupt When the input signal I1 is a false interrupt input signal, the output signal O1 of the interrupt signal preprocessing circuit 2 will not cause a system interrupt. And under the reset of the signal I3, the strobe clock signal will still be pulled down.

In addition, although the situation that the edge (rising edge or falling edge) of the interrupt input signal triggers the interrupt is not given here, those of ordinary skill in the art can obviously understand that the above-mentioned interrupt signal preprocessing circuit 2 can also be applied to the situation of the edge triggering the interrupt . And it can achieve the same technical effect, that is, it has no effect on the interrupt processing of the system except that the strobe clock signal I4 is pulled low without interrupt input, so as to achieve the technical effect of saving power.

FIG. 4 is a flowchart of an interrupt control method for a computer system according to an embodiment of the present invention.

First, at step S10, it is judged whether there is an interrupt input signal, wherein the interrupt input signal includes an external interrupt signal and an internal interrupt signal. If it is determined in step S10 that the input signal is not interrupted, then step S10 is repeated. If it is determined in step S10 that there is an interrupt input signal, then proceed to step S20.

In step S20, the strobe clock signal in the interrupt control process is enabled. Then in step S30, the interrupt input signal is properly processed, such as delay, active level selection processing, etc., and the processed interrupt input signal is introduced into the Advanced Programmable Interrupt Controller (APIC) for normal interrupt processing. Interrupt processing generally includes ignoring noise such as burrs in the interrupt signal, identifying the real interrupt signal, and being able to identify whether it is a level-triggered interrupt or an edge-triggered interrupt, and performing related processing according to the interrupt signal. When the interrupt processing ends, the interrupt is automatically cleared.

Then proceed to step S40, and in step S40, it is judged whether the interrupt processing is finished. If the interrupt processing is not over, step S40 is repeated. If the interrupt processing ends, go to step S50.

In step S50, pull down the gate clock signal to low level, and then return to step S10.

According to the interrupt control method of the embodiment of the present invention, when the system is working normally, the gate clock signal is pulled down to low level only when no interrupt signal is input, thereby saving power.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore The protection scope of the present invention shall be determined by the claims of the present invention.

Claims (15)

1. interruptable controller that is used for computer system comprises:

N look-at-me pre-process circuit receives n and interrupts input signal and effective definite signal, n first output signal of output and individual second output signal of n selected of corresponding interrupt level;

The exclusive disjunction device carries out exclusive disjunction with n second output signal and handles;

Clock module, the clock signal that the phase-locked module of receiving computer system chipset produces produces the gated clock signal, and the output of exclusive disjunction device is connected to clock module, is used to control the generation of gated clock signal;

The APIC module has n and interrupts inlet, receives corresponding n first output signal, the gated clock signal that the receive clock module produces,

Wherein each look-at-me pre-process circuit comprises:

First phase inverter, it is anti-phase to interrupt input signal;

First Port Multiplier receive to interrupt input signal and through the anti-phase interruption input signal of first phase inverter;

First latch latchs the output of first Port Multiplier;

Register under the control of gated clock, is stored the output of first latch;

Second phase inverter, the output of register is anti-phase;

Second Port Multiplier, the output signal of the receiving register output signal and second phase inverter, its output signal is as first output signal of look-at-me pre-process circuit;

Second latch, its signal input part and input end of clock are connected respectively to the output terminal of register;

First or door, the output of first Port Multiplier and the output of register carried out or handled, first or output be connected to the input end of clock of first latch;

Second or door, the output of first latch and the output of second latch carried out or handled, second or output signal as second output signal of look-at-me pre-process circuit;

Wherein, the reset signal of the reset terminal receiving system bus of the reset terminal of first latch and register, the reset terminal of second latch receives a pulse reset signal,

Wherein, when having the interruption input signal, the exclusive disjunction device is output as high level, and the gated clock signal input part of APIC module receives normal gated clock signal, carries out Interrupt Process; When not having any interruption input signal, the exclusive disjunction device is output as low level, and the gated clock signal that the gated clock signal input part of APIC module receives is pulled down to low level.

2. interruptable controller as claimed in claim 1, each look-at-me pre-process circuit wherein also comprises first impact damper and second impact damper, is respectively applied for the output of buffering first Port Multiplier and the output of register; Wherein first latch latchs the output of first impact damper under the signal controlling of its input end of clock; Second latch latchs the output of second impact damper under the signal controlling of its input end of clock.

3. interruptable controller as claimed in claim 1, wherein computer working is at the S0 state.

4. interruptable controller as claimed in claim 1, wherein this first Port Multiplier is effectively to select to determine that according to interrupt level signal selects interruption input signal that output received or anti-phase interruption input signal; This second Port Multiplier is an output signal of effectively selecting to determine the signal selection output register output signal or second phase inverter according to interrupt level.

5. interruptable controller as claimed in claim 1, wherein this first latch is the output of latching first Port Multiplier under the signal controlling of its input end of clock.

6. interruptable controller as claimed in claim 4, wherein for each look-at-me pre-process circuit, in the middle of outage is flat selects effectively to determine that signal is that high level is when effectively selecting to determine signal, the interruption input signal that first Port Multiplier selects output to be received, second Port Multiplier is selected the output register output signal.

7. interruptable controller as claimed in claim 4, wherein for each look-at-me pre-process circuit, in the middle of outage is flat selects effectively to determine that signal is that low level is when effectively selecting to determine signal, first Port Multiplier selects output through the anti-phase interruption input signal of first phase inverter, and second Port Multiplier is selected the output signal of output second phase inverter.

8. look-at-me pre-process circuit that is used for computer system comprises:

First phase inverter, it is anti-phase to interrupt input signal;

First Port Multiplier receive to interrupt input signal and through the anti-phase interruption input signal of first phase inverter;

First latch latchs the output of first Port Multiplier;

Register under the control of gated clock, is stored the output of first latch;

Second phase inverter, the output of register is anti-phase;

Second Port Multiplier, the output signal of the receiving register output signal and second phase inverter, its output signal is as first output signal of look-at-me pre-process circuit;

Second latch, its signal input part and input end of clock are connected respectively to the output terminal of register;

First or door, the output of first Port Multiplier and the output of register carried out or handled, first or output be connected to the input end of clock of first latch;

Second or door, the output of first latch and the output of second latch carried out or handled, second or output signal as second output signal of look-at-me pre-process circuit;

Wherein, the reset signal of the reset terminal receiving system bus of the reset terminal of first latch and register, the reset terminal of second latch receives a pulse reset signal,

Wherein, when having the interruption input signal, second output signal becomes high level along with interrupting the effective of input signal, enables the gated clock signal; After pulse reset signal resetted second latch, second output signal became low level, moved the gated clock signal to low level.

9. look-at-me pre-process circuit as claimed in claim 8 also comprises first impact damper and second impact damper, is respectively applied for the output of buffering first Port Multiplier and the output of register; Wherein first latch latchs the output of first impact damper under the signal controlling of its input end of clock, and second latch latchs the output of second impact damper under the signal controlling of its input end of clock.

10. look-at-me pre-process circuit as claimed in claim 8, wherein this first Port Multiplier is effectively to select to determine that according to interrupt level signal selects interruption input signal that output received or anti-phase interruption input signal; This second Port Multiplier is an output signal of effectively selecting to determine the signal selection output register output signal or second phase inverter according to interrupt level.

11. look-at-me pre-process circuit as claimed in claim 10, wherein interrupt level selects effectively to determine that signal is that high level effectively selects to determine signal, then first Port Multiplier is selected the interruption input signal that output is received, and second Port Multiplier is selected the output register output signal.

12. look-at-me pre-process circuit as claimed in claim 10, wherein interrupt level selects effectively to determine that signal is that low level effectively selects to determine signal, then first Port Multiplier selects output through the anti-phase interruption input signal of first phase inverter, and second Port Multiplier is selected the output signal of output second phase inverter.

13. look-at-me pre-process circuit as claimed in claim 8, wherein this first latch is the output of latching first Port Multiplier under the signal controlling of its input end of clock.

14. the interrupt control method of a computer system comprises step:

In judging system, exist when interrupting input signal, make the clock module that is used for interrupt control in the system produce the gated clock signal of the interruptable controller of interrupt control process, carry out suitable processing to interrupting input signal, and the interruption input signal that will handle is incorporated into Advanced Programmable Interrupt Controllers APICs and carries out normal Interrupt Process;

When interrupting the processing end, the gated clock signal is pulled down to low level.

15. interrupt control method as claimed in claim 14, wherein computer working is at the S0 state.

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