CN100409436C - Application method of press welding block on top of logic integrated circuit - Google Patents
Application method of press welding block on top of logic integrated circuit Download PDFInfo
- Publication number
- CN100409436C CN100409436C CNB2005101110438A CN200510111043A CN100409436C CN 100409436 C CN100409436 C CN 100409436C CN B2005101110438 A CNB2005101110438 A CN B2005101110438A CN 200510111043 A CN200510111043 A CN 200510111043A CN 100409436 C CN100409436 C CN 100409436C
- Authority
- CN
- China
- Prior art keywords
- welding block
- press welding
- integrated circuit
- thickness
- pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000003466 welding Methods 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 241000218202 Coptis Species 0.000 description 16
- 235000002991 Coptis groenlandica Nutrition 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000003139 buffering effect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 2
- 239000000428 dust Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The disclosed method includes following ways to use pressure-welding block: increasing thickness of pressure-welding block on top of IC, i.e. a direct approach; stacking pressure-welding blocks to increase thickness of total blocks; changing structure under pressure-welding block, i.e. restricting structure of metal layer under pressure-welding block, or restricting graphics of metal wires under pressure-welding block, or restricting structure of interlayer film under pressure-welding block. Method for increasing thickness of pressure-welding block on top of IC, and method of changing structure under pressure-welding block can be combined to use. Changing method for fabricating and designing IC, the invention saves area of IC chip effectively, and reduces cost.
Description
Technical field
The present invention relates to a kind of manufacturing and method for designing of logical integrated circuit, particularly a kind of application process of realizing the press welding block on the logical integrated circuit top.
Background technology
When carrying out traditional integrated circuit (IC) design, forbid on the circuit top, placing press welding block (Pad), but make and method for designing at present, can cancel above-mentioned restriction wholly or in part,, reduced the purpose of cost to reach the minimizing chip area by corresponding.
As shown in Figure 1, general logical integrated circuit adopts the metal (Metal) of 8000 dust thickness as top-level metallic (Top metal), and the thickness of press welding block is exactly 8000 dusts.When integrated circuit encapsulates, need be on press welding block bonding (Bonding) gold thread as the line of chip pin.Because the pressure in the time of the bonding gold thread can make product failure to the circuit under the press welding block is damaged, the stress behind the bonding gold thread can integrity problem occur to product simultaneously, so forbid placing circuit under press welding block in design.Therefore how addressing the above problem, is to need in the present technological design to solve.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of application process of realizing the press welding block on the logical integrated circuit top, makes and method for designing by changing, and realizes the application of " press welding block on the circuit top ".
For solving the problems of the technologies described above, the inventive method can promptly directly by increasing the thickness of press welding block piece, also can increase press welding block thickness by the stack press welding block by increasing the thickness of the press welding block on the integrated circuit top; The structure below the press welding block be can also change, metal-layer structure, the metal line pattern below the restriction press welding block or the interlayer membrane structure below the restriction press welding block below the press welding block promptly limited; The thickness of the press welding block on the above-mentioned increase integrated circuit top or the method for the structure below the change press welding block can be used in combination.
The present invention effectively saves integrated circuit chip area owing to, realize the application of " press welding block on the circuit top " by changing the manufacturing and the method for designing of integrated circuit, has reduced cost.
Description of drawings
Fig. 1 is the generalized section of the product under the common technology;
Fig. 2 is the thickness schematic diagram that directly increases the press welding block piece in the inventive method;
Fig. 3 is the schematic diagram that increases thickness in the inventive method by the stack press welding block;
Fig. 4 is the schematic diagram of the metal-layer structure below the restriction press welding block in the inventive method;
Fig. 5 is the schematic diagram of the metal line pattern below the restriction press welding block in the inventive method;
Fig. 6 is the schematic diagram of the interlayer membrane structure below the restriction press welding block in the inventive method.
Embodiment
The present invention is further detailed explanation below in conjunction with accompanying drawing.
The inventive method is by changing the manufacturing and the method for designing of integrated circuit in essence.Fig. 1 is the generalized section (bonding gold thread) of the product under the common technology, comprises structures such as press welding block, top-level metallic, metal level, interlayer film, and the present invention promptly redesigns manufacturing to these structures.
As shown in Figure 2, be the thickness schematic diagram that directly increases the press welding block piece in the inventive method, promptly logical increasing adds a layer metal thickness, increases the thickness of press welding block, realizes " press welding block on the circuit top ".In the manufacturing of integrated circuit, metal wire and press welding block are simultaneously produced, their thickness is consistent, by increasing metal thickness, press welding block thickness is increased, pressure when giving the bonding gold thread like this and the stress behind the bonding gold thread have more buffering,, realize the application of " press welding block on the circuit top " to a little less influence of product
As shown in Figure 3, be the schematic diagram that increases thickness in the inventive method by the stack press welding block, promptly, increase press welding block thickness by the stack press welding block, realize " press welding block on the circuit top ".After traditional press welding block manufacturing is finished, certain thickness press welding block of extra increase on press welding block, press welding block thickness is increased, pressure when giving the bonding gold thread like this and the stress behind the bonding gold thread have more buffering, to a little less influence of product, realize the application of " press welding block on the circuit top ".
As shown in Figure 4, be the schematic diagram of the metal-layer structure below the restriction press welding block in the inventive method, promptly the metal-layer structure below the restriction press welding block is realized " press welding block on the circuit top ".Because the metal connecting line (Metal Interconnect) of integrated circuit is a sandwich construction, can change wherein the structure of which floor or whole metal, reduce temperature to 300 degree even 270 degree of metal deposit such as change, pressure when giving the bonding gold thread like this and the stress behind the bonding gold thread have more buffering, to a little less influence of product, realize the application of " press welding block on the circuit top ".
As shown in Figure 5, be the schematic diagram of the metal line pattern below the restriction press welding block in the inventive method, promptly the metal line pattern below the restriction press welding block realizes " press welding block on the circuit top ".Because the metal connecting line (Metal Interconnect) of integrated circuit is a sandwich construction, can design wherein which floor or whole metal wire special graphs, web metal level such as rule, pressure when giving the bonding gold thread like this and the stress behind the bonding gold thread have more buffering, to a little less influence of product, realize the application of " press welding block on the circuit top ".
As shown in Figure 6, be the schematic diagram of the interlayer membrane structure below the restriction press welding block in the inventive method, promptly the interlayer membrane structure below the restriction press welding block realizes " press welding block on the circuit top ".Because the metal connecting line (Metal Interconnect) of integrated circuit is a sandwich construction, interlayer film (IMD) is arranged at interval between each layer of metal connecting line, can change wherein the structure of which floor or whole interlayer film, form fluorine silex glass (FSG) such as in undoped silicon glass (USG), mixing fluorine, pressure when giving the bonding gold thread like this and the stress behind the bonding gold thread have more buffering, to a little less influence of product, realize the application of " press welding block on the circuit top ".
Must point out emphatically, more than as Fig. 2 to the several method of Fig. 6, combination in any is used simultaneously, realizes the application of " press welding block on the circuit top ".
In addition on the basis of above all methods, following circuit for press welding block carries out some restrictions, for example only allow placement imput output circuit (I/O), electrostatic discharge circuit (ESD) to wait the pressure of some relative insensitivity when the bonding gold thread and the circuit of the stress behind the bonding gold thread, realize the inventive method.
In sum, the inventive method is exactly by changing the manufacturing and the method for designing of integrated circuit, making the product of the placement press welding block on the circuit top obtain common encapsulation rate of finished products, package reliability and product reliability under common encapsulation condition.
Claims (1)
1. application process of realizing the press welding block on the logical integrated circuit top, directly by increasing the thickness of press welding block, or by the stack press welding block increase press welding block thickness, it is characterized in that, change the structure under the described press welding block, temperature when being the deposit of press welding block lower metal layer is between 270 degrees centigrade to 300 degrees centigrade, or change the press welding block lower metal layer web of rule into, or mix fluorine in the undoped silicon glass that the interlayer film between the press welding block lower metal layer is adopted and form the fluorine silex glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101110438A CN100409436C (en) | 2005-12-01 | 2005-12-01 | Application method of press welding block on top of logic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101110438A CN100409436C (en) | 2005-12-01 | 2005-12-01 | Application method of press welding block on top of logic integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1979837A CN1979837A (en) | 2007-06-13 |
| CN100409436C true CN100409436C (en) | 2008-08-06 |
Family
ID=38130933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101110438A Expired - Fee Related CN100409436C (en) | 2005-12-01 | 2005-12-01 | Application method of press welding block on top of logic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100409436C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
| CN103050418B (en) * | 2011-10-13 | 2015-05-27 | 北大方正集团有限公司 | Pad manufacturing method and pad |
| CN103065974B (en) * | 2011-10-24 | 2015-10-14 | 北大方正集团有限公司 | A kind of method and chip making chip pressure welding block |
| CN103094134B (en) * | 2011-10-31 | 2015-07-15 | 北大方正集团有限公司 | Method and chip of increasing thickness of metal layer of chip bonding block area |
| CN103426848A (en) * | 2012-05-25 | 2013-12-04 | 北大方正集团有限公司 | Chip and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5455195A (en) * | 1994-05-06 | 1995-10-03 | Texas Instruments Incorporated | Method for obtaining metallurgical stability in integrated circuit conductive bonds |
| CN1204153A (en) * | 1997-06-13 | 1999-01-06 | 株式会社日立制作所 | Semiconductor integrated circuit device |
| CN1387681A (en) * | 1999-11-05 | 2002-12-25 | 爱特梅尔股份有限公司 | Metal redistribution layer having solderable pads and wire bondable pads |
| CN1466211A (en) * | 2002-06-28 | 2004-01-07 | ��Ʒ���ܹ�ҵ�ɷ�����˾ | Semiconductor package and manufacturing method thereof |
| WO2004032223A1 (en) * | 2002-09-30 | 2004-04-15 | Renesas Technology Corp. | Semiconductor device |
-
2005
- 2005-12-01 CN CNB2005101110438A patent/CN100409436C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5455195A (en) * | 1994-05-06 | 1995-10-03 | Texas Instruments Incorporated | Method for obtaining metallurgical stability in integrated circuit conductive bonds |
| CN1204153A (en) * | 1997-06-13 | 1999-01-06 | 株式会社日立制作所 | Semiconductor integrated circuit device |
| CN1387681A (en) * | 1999-11-05 | 2002-12-25 | 爱特梅尔股份有限公司 | Metal redistribution layer having solderable pads and wire bondable pads |
| CN1466211A (en) * | 2002-06-28 | 2004-01-07 | ��Ʒ���ܹ�ҵ�ɷ�����˾ | Semiconductor package and manufacturing method thereof |
| WO2004032223A1 (en) * | 2002-09-30 | 2004-04-15 | Renesas Technology Corp. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1979837A (en) | 2007-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6313537B1 (en) | Semiconductor device having multi-layered pad and a manufacturing method thereof | |
| TWI323493B (en) | Bond pad structure amd method for forming the same | |
| CN101593738B (en) | Semiconductor device and method of manufacturing same | |
| TWI451545B (en) | Bump pad structure and method for creating the same | |
| EP1519411A2 (en) | Semiconductor device and method for fabricating the same | |
| CN103311202B (en) | The wirebond structures of integrated circuit | |
| US7956461B2 (en) | Semiconductor apparatus including semiconductor chip with stress material selectively provided in region of wiring layer | |
| CN102148204B (en) | Multi-direction design for bump pad structures | |
| US6462427B2 (en) | Semiconductor chip, set of semiconductor chips and multichip module | |
| JP2000307057A5 (en) | ||
| JPH113984A (en) | Semiconductor integrated circuit device | |
| TWI335650B (en) | Bonding pad structure and method for forming thereof | |
| US7470994B2 (en) | Bonding pad structure and method for making the same | |
| CN102593043B (en) | Increasing dielectric strength by optimizing dummy metal distribution | |
| CN100409436C (en) | Application method of press welding block on top of logic integrated circuit | |
| CN101882608B (en) | Bump pad structure and manufacturing method thereof | |
| US20070138609A1 (en) | Semiconductor die structure featuring a triple pad organization | |
| CN208767302U (en) | semiconductor device | |
| US7666712B2 (en) | Design of BEOL patterns to reduce the stresses on structures below chip bondpads | |
| WO2016035251A1 (en) | Semiconductor device | |
| US20040016980A1 (en) | Semiconductor integrated device | |
| CN113410204A (en) | Wiring substrate and semiconductor device | |
| US20040232448A1 (en) | Layout style in the interface between input/output (I/O) cell and bond pad | |
| JP2007335511A (en) | Semiconductor integrated circuit device design method, semiconductor integrated circuit device and manufacturing method thereof | |
| CN116666308B (en) | Sealing ring, semiconductor device and terminal device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Hua Hong NEC Electronics Co.,Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080806 Termination date: 20211201 |