CN100405615C - Integrated chip type diode - Google Patents

Abstract

An integrated chip type diode, utilize diffusion technology, in top and bottom of a semiconductor wafer, form p + and n + type semiconductor (or n + and p + type semiconductor) of a predetermined thickness separately, reuse the semiconductor manufacturing technology such as carving, etching, implanting and sintering, etc., make a plurality of diodes on the wafer separately, the lateral margin of each diode is sealed with the insulating glass, on p + and n + type semiconductor of its two-terminal surface, have a conductive metal layer separately, wherein on the partial surface of a conductive metal layer, and coat with an insulating material, make another conductive metal layer can be conducted to the insulating material of another end through another conductive metal layer sintered on the insulating glass; the chip type diode of the invention can be directly installed on a related electronic circuit without subsequent packaging procedures, can effectively improve the heat conduction characteristic of the diode, ensures that the diode can bear higher working temperature and greatly reduces the volume of the diode.

Description

Integrated Chip Diode

technical field

The invention relates to the structure of a diode, especially a chip-type diode in which the two welding conductive ends are located on the same end surface (top or bottom) and can be directly packaged in glass during the production process of the diode crystal grain, so that the thermal conductivity of the diode can be effectively improved. , and greatly reduce its size.

Background technique

Commonly seen diode elements on the market, its basic structure includes a silicon crystal grain, the two ends of the silicon crystal grain are respectively welded with a conductive metal sheet, and the other side of the conductive metal sheet is respectively welded with a wire, so that by these The wires are connected to other electronic pins. In the production process of this common diode element, after the silicon crystal grain and the conductive metal sheet are integrated, the silicon crystal grain needs to be etched. The silicon crystal grain and the periphery of the conductive metal sheet are packaged with an insulating colloid to make a common diode element.

In the manufacturing process of these conventional diode elements, after the silicon crystal grains are etched, they are all encapsulated with resin or other colloids. When used as a rectifier element for high-power input current, or when used in a high-temperature environment, it is very easy to be damaged by high heat, causing related electronic equipment to fail to work normally, seriously affecting the service life and quality of electronic equipment, and causing maintenance problems. In addition, since the encapsulation shell formed by the resin or colloid must occupy a certain amount of space, the size of the conventional diode elements cannot be further reduced.

Contents of the invention

In view of many problems existing in existing diodes, the inventor has developed an integrated chip type diode through continuous efforts in research and experiments in order to uphold years of experience in this industry.

One purpose of the present invention is to form two independent soldering conductive terminals on the same end (top or bottom) of each diode, so that each of the soldering conductive terminals can be respectively conducted with the p+ and n+ type semiconductors of the diodes , so that the fabricated chip-type diode has the characteristics of a surface-mounting (surface-mounting) type component, and can be directly installed on the relevant electronic circuit.

Another object of the present invention is to use glass sintering treatment to directly cover the periphery of the crystal grain with insulating glass during the manufacturing process, so as to effectively improve the thermal conductivity of the diode, ensure that it can withstand a relatively high operating temperature, and greatly reduce its size.

Another object of the present invention is to produce a finished diode for surface mount (SMD) without subsequent packaging procedures.

In order to achieve the above object, the integrated chip type diode of the present invention mainly utilizes diffusion (diffusion) technology to form a predetermined thickness of p+ and n+ type semiconductors (or n+ and p+ type semiconductor), and then use semiconductor manufacturing techniques such as sculpture, etching, implantation and sintering to manufacture a plurality of diodes on the wafer (Wafer), and the side edges of each diode are sealed with insulating glass. A conductive metal layer is respectively formed on the p+ and n+ type semiconductors on the two end faces, and a part of the surface of one of the conductive metal layers is coated with an insulating material so that the other conductive metal layer can pass through the insulating glass. Another sintered conductive metal layer is conducted to the insulating material at the other end.

The chip-type diode of the present invention can be directly installed on related electronic circuits without subsequent packaging procedures, and can effectively improve the heat conduction characteristics of the diode to ensure that it can withstand a relatively high working temperature and greatly reduce its volume.

In order to express the design concept, structural features and manufacturing procedures of the present invention more specifically and clearly, hereby enumerate the embodiments of several organs, and cooperate with diagrams, the detailed description is as follows:

Description of drawings

Fig. 1 shows that in a preferred embodiment of the present invention, the schematic cross-sectional view after the p+ type semiconductor layer is diffused on the wafer;

Figures 2a and 2b are schematic diagrams of X-X and Y-Y cross-sectional structures after forming a plurality of rectangular grooves on the wafer in the preferred embodiment using statue and etching trench technology;

Figure 3a and 3b show that in this preferred embodiment, the X-X and Y-Y cross-sectional structural schematic diagrams after the n+ type semiconductor layer is diffused on the wafer;

Figures 4a and 4b show the X-X and Y-Y cross-sectional structural schematic diagrams of filling the grooves with metal paste and sintering it in the preferred embodiment;

Figure 5 shows that in the preferred embodiment, on the cross-section X-X, at the position between two adjacent first metal layers, along the Y-axis direction, using statues and etching trench technology to open a channel Schematic diagram of X-X section structure;

6a and 6b are schematic diagrams of X-X and Y-Y cross-sectional structures after a silicon dioxide layer is epitaxy or implanted on the bottom of the wafer in the preferred embodiment using epitaxy or implantation technology;

Fig. 7 shows in this preferred embodiment, utilizes statue and etched ditch technology, between two adjacent grooves, along the Y-axis direction, opens the X-X cross-sectional structure schematic diagram after a groove;

Fig. 8 shows that in this preferred embodiment, metal paste is filled in the positions of the grooves and grooves, and it is sintered to form the X-X cross-sectional structure diagram of the second and third metal layers ;

Figures 9a and 9b show the X-X and Y-Y cross-sectional structural schematic diagrams of another groove and another groove on the wafer along the Y-axis direction in the preferred embodiment using statue and etched trench technology ;

Figures 10a and 10b show the X-X and Y-Y cross-sectional structural schematic diagrams of filling glass paste into the channels and grooves and sintering them in the preferred embodiment;

Fig. 11 shows that in this preferred embodiment, from the top surface of the wafer, along the Y-axis direction, the glass in each of the channels is subjected to the X-X cross-sectional structural schematic diagram after the hole-digging operation;

Figures 12a and 12b show X-X and Y-Y after forming the fourth metal layer on the top surface of the wafer corresponding to the upper surface of the p+ type semiconductor to the slots in the preferred embodiment. Schematic diagram of the cross-sectional structure;

13a and 13b are schematic diagrams of X-X and Y-Y cross-sectional structures after sintering a layer of insulating glass on the top surface of the wafer corresponding to the position of the p+ type semiconductor in the preferred embodiment;

Figures 14a and 14b show the X-X and Y-Y cross-sectional structural schematic diagrams of the finished wafer-type diode after the wafer is cut and granulated in the preferred embodiment;

15a and 15b are X-X and Y-Y cross-sectional schematic diagrams of the finished wafer-type diode in another preferred embodiment of the present invention.

Detailed ways

The present invention is an integrated chip type diode and its manufacturing method. It mainly utilizes diffusion technology to form different types of semiconductors with a predetermined thickness on the top and bottom of a semiconductor wafer respectively, and then manufactures semiconductors of different types on the wafer respectively. A plurality of diodes, the side edges of each diode are sealed with insulating glass, and a conductive metal layer is formed on the different semiconductor surfaces of the two end faces, and an insulating layer is covered on a part of the surface of one of the conductive metal layers. material, so that the other conductive metal layer can be conducted to the insulating material at the other end through another conductive metal layer sintered on the insulating glass, and the conductive metal layer is on the same end face of the diode, Two independent soldering conductive ends are formed, so that each soldering conductive end can be connected to different types of semiconductors on each diode, so that it can produce finished diodes for surface mounting without post-packaging procedures. . In the subsequent description of the present invention, it is called an Integrated Chip Diode (ICD for short).

Since, in the manufacturing process of the integrated chip type diode, the structures produced along the X-X and Y-Y cross-sections of the above-mentioned semiconductor materials are not the same, so the present invention will specifically indicate its characteristics in X and Y in the description of the following embodiments. The difference in the structure of the Y-axis profile.

In a preferred embodiment of the present invention, above a wafer 10 (wafer) of an n-type semiconductor, as shown in FIG. p+ type semiconductor 11; then use statue and etching trench technology to etch a plurality of rectangular grooves 20 at the bottom of n-type wafer 10 according to the required actual size, as shown in FIG. 2a, to make four wafer-type diodes The X-X cross-sectional schematic diagram of the required wafer, wherein it is shown that two rectangular grooves 20 are provided on the X-X cross-section, as shown in FIG. It is shown that four rectangular grooves 20 are opened on the Y-Y longitudinal section; then, the present invention diffuses phosphorus ions into the bottom of the n-type wafer 10 to form an n+-type semiconductor 12 with a predetermined thickness, see Fig. 3a, 3b The X-X and Y-Y cross-sectional structural schematic diagrams shown; then, fill the metal paste (such as copper paste, silver paste, gold paste, etc.) in the grooves 20, and sinter it, see Figure 4a , X-X and Y-Y cross-sectional structural schematic diagrams shown in 4b, in order to form a first metal layer 13 in each of the grooves 20; the present invention is located between two adjacent first metal layers 13 on the cross-section X-X At the position along the Y axis, a channel 21 is opened by using statue and trench etching technology, referring to the X-X cross-sectional structural schematic diagram shown in Figure 5, the depth of the channel 21 needs to pass through the n+ type semiconductor 12 to reach the wafer 10 n-type semiconductor parts; then, with CVD (Chemical Vapor Deposition) epitaxial method (in other embodiments of the present invention, PVD (Physical Vapor Deposition) or PCVD (Photon-induce Chemical Vapor Deposition) etc. can also be used Epitaxy method) or implantation technology, on the bottom of the wafer 10, that is, on the surface of the metal layer 13 and the channel 21, a silicon dioxide layer 14 is epitaxy (or implanted), as shown in FIGS. 6a and 6b. X-X and Y-Y cross-sectional schematic diagrams shown, the silicon dioxide layer 14 is used as the first insulating layer of the wafer-type diode.

It should be noted here that in this embodiment, although the ion diffusion method is used to form a p+ type semiconductor 11 and n+ type semiconductor 12 with a predetermined thickness on the top and bottom of an n type semiconductor wafer 10, but The scope of rights claimed by the present invention is not limited thereto. According to those who are familiar with the art, according to the technical content disclosed in the present invention, use other diffusion methods or implantation Round 10 (wafer) top and bottom (or bottom and top), form a predetermined thickness of n + type semiconductor and p + type semiconductor (or p + type semiconductor and n + type semiconductor), should still belong to the semiconductor wafer referred to in the present invention, Together first Chen Ming.

Then, in this embodiment, a groove 22 is opened between two adjacent grooves 21 along the Y-axis direction by using statue and trench etching techniques. Referring to the X-X cross-sectional structural schematic diagram shown in FIG. The depth of the groove 22 reaches the first metal layer 13 through the insulating material layer 14 (i.e. the silicon dioxide layer); then, fill the metal paste (such as : copper paste, silver paste, gold paste... and other materials), and it is sintered to form the second and third metal layers 15 and 16 respectively, referring to the X-X cross-sectional structural schematic diagram shown in Figure 8, so that the first The three metal layers 16 can just pass through the first metal layer 13 to conduct with the n+ type semiconductor 12 , and serve as a solder metal layer for conducting with the n+ type semiconductor 12 on the chip type diode of the present invention.

Then, in this embodiment, using the statue and etching trench technology, along the Y-axis direction, at the positions corresponding to the second and third metal layers 15 and 16 above the wafer 10, open another groove 31 and 16 respectively. Another trench 32, referring to the X-X cross-sectional schematic diagram shown in FIG. 12, reach the first metal layer 13, and along the X-axis direction, respectively open a groove 33 above the wafer 10 corresponding to the position between the adjacent first metal layer 13, as shown in FIG. 9b A schematic diagram of the Y-Y cross-sectional structure, the depth of the trench 33 just reaches the silicon dioxide layer 14 .

Then, the present invention fills the glass paste uniformly prepared and mixed by glass powder and glue into the grooves 32, 33, referring to the X-X and Y-Y cross-sectional structural schematic diagrams shown in Fig. 10a, 10b, and performing The sintering process makes the sintered glass 34, 35 and 36 just coat the side edge of the chip-type diode of the present invention to complete the packaging of the side edge of the chip-type diode; then, from the top surface of the wafer 10, Along the Y-axis direction, the glass 34 in each channel 31 is drilled, and the excess glass is removed, and only the part sufficient to seal the side edge of the chip-type diode is reserved. Refer to the X-X cross-sectional structure shown in FIG. 11 Schematic diagram, and make the depth of the slots 40 excavated just enough to reach the second metal layer 15; Within the range of 40, fill low-temperature metal paste (such as copper paste, silver paste, gold paste, etc.) and sinter it. The fourth metal layer 41, so that the second metal layer 15 can just pass through the fourth metal layer 41, and conduct with the p+ type semiconductor 11, so that the second metal layer 15 can be used as an upper layer of the wafer type diode of the present invention. Another solder metal layer for conducting the P+ type semiconductor 11 .

Finally, on the top surface of the wafer 10, corresponding to the position of the P+ type semiconductor 11, a layer of insulating glass paste is coated and sintered. Refer to the X-X and Y-Y cross-sectional structural schematic diagrams shown in FIGS. 13a and 13b , to form an insulating glass layer 42 on the p+ type semiconductor 11 to complete the packaging of the top surface of the chip type diode; 32 and the position of the trench 33, the wafer 10 is cut and granulated to produce a plurality of chip-type diodes 50 that have been packaged. Refer to the X-X and Y-Y cross-sectional structural schematic diagrams shown in FIGS. In this embodiment, two independent solder metal layers (i.e. the second and third metal layers 15 and 16) are formed on the same end face (bottom) of each wafer-type diode 50, so that each solder metal layer can be separately It conducts with the p+ and n+ type semiconductors of each diode, and serves as a soldering conductive terminal for surface mounting (SMD).

The present invention is to protect each metal layer on the chip type diode 50 so that it is not easy to be oxidized, and it can be electroplated to form a protective layer on each metal layer; Diodes are tested and packaged. In this way, chip-type diodes for surface mounting (SMD) can be produced without subsequent packaging procedures, which can not only greatly reduce its size, but also effectively improve the conductance of the diode. characteristic.

In another embodiment of the present invention, the X-X and Y-Y cross-sectional structures of the finished product 60, as shown in FIGS. The top and bottom of the top and bottom of the p+ and n+ type semiconductors 11 and 12 of a predetermined thickness are respectively formed, and then metal paste is filled in the groove formed at the bottom of the n+ type semiconductor 12, and it is sintered, so as to be in each of the A first metal layer 13 is formed in the groove; a silicon dioxide layer 14 is epitaxially (or implanted) on the surface of the metal layer 13, so that the silicon dioxide layer 14 is used as the first layer of the wafer type diode. Insulation. Then, using the statue and etching trench technology, a groove is opened on the silicon dioxide layer 14 corresponding to the position between the adjacent first metal layers 13 along the Y-axis direction, and the depth of the groove just reaches the first metal layer 13. The metal layer 13 is filled with metal paste in these grooves, and it is sintered to form a second metal layer 61, so that the second metal layer 61 can just pass through the first metal layer 13, and The n+ type semiconductor 12 is turned on.

Then, in this other embodiment, a trench 62 is opened on the wafer 10 above the wafer 10 corresponding to the position between the adjacent first metal layers 13 along the X and Y axis directions respectively by using the statue and trench etching technology. , the depth of the trench 62 passes through the n+ type semiconductor 12, reaches the first metal layer 13, and on the X-X section, between the two adjacent trenches 62, another trench is opened along the Y-axis direction 63, the depth of the channel 63 just reaches the n+ type semiconductor 12, so that the p+ type semiconductor 11 is partitioned into two parts on the X-X section.

Then, in this other embodiment, the glass slurry uniformly prepared and mixed by glass powder and glue is filled into the grooves 63, the grooves 62 and the upper surface of a part of the P+ type semiconductor 11, and the The sintering process is performed so that the sintered glass 74, 75 and 76 can be coated on the side edge of the wafer type diode of the present invention to complete the packaging of the side edge of the chip type diode; then, the wafer top surface , along the Y-axis direction, the glass 74 in the groove 62 corresponding to the second metal layer 61 is drilled, and the redundant glass is removed, and only the part that is enough to seal the side edge of the chip-type diode is reserved, and the The depth of the slot hole 80 excavated is just enough to reach the second metal layer 61; In the hole 80, fill the low-temperature metal paste, and it is sintered, to form a third metal layer 64 and the fourth metal layer 65 respectively, so that the fourth metal layer 65 can pass through the second metal layer and the The first metal layers 61 and 13 are conducted with the n+ type semiconductor 12, so that the fourth metal layer 65 can be used as a welding metal layer for conducting the n+ type semiconductor 12 on the chip type diode of the present invention, The third metal layer 64 can conduct with the p+ type semiconductor 11 , and is used as another welding metal layer for conducting with the p+ type semiconductor 11 on the chip type diode of the present invention. In this way, this other embodiment can form two independent solder metal layers (i.e. the third and fourth metal layers 64 and 65) on the same end face (top) of each of the wafer-type diodes 60, so that each of the solder metal layers It can be connected with the p+ and n+ type semiconductors 11 and 12 of the diodes respectively, and can be used as the soldering conductive terminal during surface mounting (SMD).

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of an invention shall be defined by the scope of the claims.

Claims (2)

1. integrated wafer diode, it is characterized in that: utilize diffusion technique, biend at the semiconductor wafer, form veriform first semiconductor and second semiconductor of a predetermined thickness respectively, on this wafer, produce a plurality of diodes more respectively, respectively the lateral margin of this diode gives involution with insulating glass, wherein be formed with the first metal layer on first semiconductor surface of an end face, be provided with first groove in the position that is positioned between adjacent the first metal layer, on the surface of this first metal layer and this groove, be coated with an insulation material layer, second metal level is set on the insulation material layer in first groove, side insulating glass in the lateral margin of described respectively this diode arrives this insulation material layer from the second semiconductor end face, the 3rd metal level is positioned at second metal level, one side and passes insulation material layer and contacts with the first metal layer, in this side insulating glass, be provided with and pass the 4th metal level that insulation material layer arrives this second metal level, second semiconductor of this diode other end passes insulation material layer and this second metal level conducting by the 4th metal level, on the first semiconductor end face of this diode, form two by second metal level and the 3rd metal level and independently weld conducting end, make respectively this welding conducting end can be respectively with this diode respectively on veriform first and second semiconductors be conducted.

2. integrated wafer diode, it is characterized in that: utilize diffusion technique, biend at the semiconductor wafer, form veriform first and second semiconductors of a predetermined thickness respectively, on this wafer, produce a plurality of diodes more respectively, respectively offer a conduit on this diode, this conduit passes second semiconductor of an end face, its degree of depth just arrives first semiconductor of other end, make this second semiconductor be separated into two partly, respectively the lateral margin of this diode and this conduit give involution with insulating glass, wherein be formed with the first metal layer on the surface of the first semiconductor end face, the first metal layer is provided with insulation material layer, at adjacent insulating material interlayer second metal level being set passes insulation material layer and contacts with the first metal layer, side insulating glass in the lateral margin of described respectively this diode arrives second metal level from the second semiconductor end face, the 4th metal level that arrives this second metal level is set in this side insulating glass, at the second semiconductor end face the 3rd metal level is set, on the second semiconductor end face of this diode, form two by the 3rd metal level and the 4th metal level and independently weld conducting end, make respectively this welding conducting end can be respectively with this diode respectively on veriform semiconductor be conducted.

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