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CN100405548C - bump manufacturing process and structure - Google Patents

bump manufacturing process and structure Download PDF

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Publication number
CN100405548C
CN100405548C CNB200510069102XA CN200510069102A CN100405548C CN 100405548 C CN100405548 C CN 100405548C CN B200510069102X A CNB200510069102X A CN B200510069102XA CN 200510069102 A CN200510069102 A CN 200510069102A CN 100405548 C CN100405548 C CN 100405548C
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rete
projection
sheath
joint sheet
bump
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CN1862771A (en
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胡钧屏
陈正中
蔡建文
李育青
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Elan Microelectronics Corp
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Elan Microelectronics Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)

Abstract

A bump manufacturing process and structure includes forming a passivation layer with a planarized surface covering a bonding pad of a substrate, forming an opening through the passivation layer to expose a contact surface of the bonding pad, and forming a bump on the contact surface and the planarized surface. The protective layer has the flattened surface, so that the bonding pad can be reduced, the mechanical strength of the protective layer in the edge area of the bonding pad is increased, the bump has a larger effective area during pressing, the selection space of the anisotropic conductive film is larger, the short circuit and electric leakage probability in the bump gap are reduced, and the pressing yield and the conductive quality of the bump are improved.

Description

凸块制作工艺及结构 Bump manufacturing process and structure

技术领域 technical field

本发明是有关一种凸块(bump)制作工艺及结构,特别是关于一种平坦化凸块的制作工艺及结构。The present invention relates to a manufacturing process and structure of a bump, in particular to a manufacturing process and structure of a planarized bump.

背景技术 Background technique

打线接合(wire bonding)、卷带自动接合(Tap Automatic Bonding;TAB)与覆晶(flip chip)接合是集成电路(IC)封装的典型技术。一般而言,打线接合应用在约300个接点以下的低密度连线封装,TAB应用的高连线密度封装达到约600个接点,覆晶接合提供600个以上接点的更高连线密度封装。使用覆晶接合的封装必须先在IC的接合垫(bonding pad)上成长凸块,以便在芯片贴合玻璃(Chip On Glass;COG)、芯片贴合电路板(ChipOn Board;COB)、芯片贴合膜片(Chip On Film;COF)或其它封装程序中进行压合。为降低电信干扰、增加黏着性及导电性,一般凸块多采用金的材质,这使得凸块的制作昂贵且困难,因此凸块制作工艺与结构成为封装技术改良的重要课题。另一方面,封装的密度及性能表现也限制了芯片的尺寸及性能表现。当IC不断地微缩,如果封装的密度及性能表现无法跟着提高,例如凸块的尺寸及节距受到局限,或者凸块的传导性能不够好,那么封装将成为芯片尺寸进一步缩小的瓶颈。Wire bonding (wire bonding), tape automatic bonding (Tap Automatic Bonding; TAB) and flip chip (flip chip) bonding are typical technologies for integrated circuit (IC) packaging. Generally speaking, wire bonding is used in low-density wiring packages with less than about 300 contacts, high-connection-density packages for TAB applications reach about 600 contacts, and flip-chip bonding provides higher connection density packages with more than 600 contacts. . Packages that use flip-chip bonding must first grow bumps on the bonding pad of the IC so that they can be bonded to the chip on glass (Chip On Glass; COG), chip on board (Chip On Board; COB), chip Lamination in Chip On Film (COF) or other packaging procedures. In order to reduce telecommunication interference, increase adhesion and conductivity, gold is generally used for bumps, which makes the production of bumps expensive and difficult. Therefore, the process and structure of bump manufacturing has become an important issue for packaging technology improvement. On the other hand, the density and performance of the package also limit the size and performance of the chip. As ICs continue to shrink, if the packaging density and performance cannot be improved, for example, the size and pitch of the bumps are limited, or the conductivity of the bumps is not good enough, then the packaging will become a bottleneck for the further reduction of the chip size.

图1显示已知的金凸块结构10,在基板12上的接合垫14被护层16覆盖一部分,凸块底层金属(Under-Bump Metallization;UBM)18在接合垫14露出的接触面及护层16上,金膜20与金凸块22在UBM 18上。典型地,接合垫14的材质为铝,护层16包含一层二氧化硅24及一层氮化硅26、UBM18为钛及钨的叠层。金膜20以溅镀法制作,其结晶粒子较细密,可增加金凸块22与UBM18之间的黏着力,金凸块22以电镀法制作,其结晶粒子较大,硬度较高。由于护层16在接合垫14边缘形成的阶梯28,凸块22的上表面边缘也跟着形成阶梯30。因此只有中心的凹陷区域32成为在压合时的有效区域,此上表面的粗糙度h约为2μm。如果要得到足够大的有效区域32,接合垫14必须较大,如果只增加凸块22的宽度,如图2所示,由于凸块22的上表面不平坦,增加的区域34仍然是无效区域,有效区域32的尺寸并无改变。图3显示在基底12上有多个凸块22的情况,接合垫14的宽度为w1,凸块间隙为g,凸块节距为p,凸块22的宽度w2不大于接合垫14的宽度w1,因此,有效区域32与接合垫14比较起来是非常小的。为增加有效区域32,要求接合垫14较大,因此芯片的接点密度较低,芯片的尺寸也无法缩小。大的接合垫14也导致大的凸块节距p,如果凸块间隙g不变,要提高接点密度唯有缩小接合垫14,但是缩小接合垫14将造成有效区域32缩小,因此已知技术有无法克服的困难。1 shows a known gold bump structure 10, the bonding pad 14 on the substrate 12 is partially covered by the protective layer 16, and the under-bump metallization (Under-Bump Metallization; UBM) 18 is exposed on the contact surface of the bonding pad 14 and the protective layer. On layer 16, gold film 20 and gold bumps 22 are on UBM 18. Typically, the bonding pad 14 is made of aluminum, the protective layer 16 includes a layer of silicon dioxide 24 and a layer of silicon nitride 26 , and the UBM 18 is a stack of titanium and tungsten. The gold film 20 is made by sputtering, and its crystal particles are finer, which can increase the adhesion between the gold bump 22 and the UBM 18 . The gold bump 22 is made by electroplating, and its crystal particles are larger and its hardness is higher. Due to the step 28 formed by the covering 16 at the edge of the bond pad 14 , the edge of the upper surface of the bump 22 also forms a step 30 . Therefore, only the central recessed region 32 becomes an effective region during pressing, and the roughness h of this upper surface is approximately 2 μm. If a sufficiently large effective area 32 is to be obtained, the bonding pad 14 must be larger. If only the width of the bump 22 is increased, as shown in FIG. 2 , since the upper surface of the bump 22 is uneven, the increased area 34 is still an inactive area , the size of the active area 32 does not change. FIG. 3 shows the situation that there are a plurality of bumps 22 on the substrate 12, the width of the bonding pad 14 is w1, the bump gap is g, the bump pitch is p, and the width w2 of the bump 22 is not greater than the width of the bonding pad 14. w1 , therefore, active area 32 is very small compared to bond pad 14 . In order to increase the effective area 32 , the bonding pads 14 are required to be larger, so the chip's contact density is low, and the size of the chip cannot be reduced. Large bonding pads 14 also lead to large bump pitch p. If the bump gap g remains unchanged, the only way to increase the joint density is to shrink the bonding pads 14. However, shrinking the bonding pads 14 will cause the effective area 32 to shrink. Therefore, the known technology There are insurmountable difficulties.

已知的凸块制作工艺如图4A至4E所示。在图4A中,沉积厚度约1.2μm的护层16覆盖在基板12的接合垫14上。在图4B中,蚀刻护层16形成开口36以暴露接合垫14,于是在接合垫14的边缘也跟着形成阶梯38,当护层16的厚度越厚,阶梯38的高度就越高,开口36就越深。在图4C中,沉积厚度约800埃的钛/钨作为UBM18,以及沉积厚度约800埃的金膜20,由于阶梯38的缘故,随之形成的阶梯40更宽,当UBM18的厚度越厚,凹陷42的宽度就越窄。图案化UBM18与金膜20后如图4D所示。在图4E中,从金膜20成长厚度约17μm的金凸块22。从前述工艺中显示出,阶梯38是无法避免的。因此最终必定得到较小面积的有效区域32,而且护层16越厚,粗糙度h就越大,UBM18越厚,有效区域32就越小。虽然IC工艺可将元件尺寸缩小,但是后段的封装技术却跟不上元件尺寸微缩的速度,因而限制了芯片的最小尺寸。A known bumping process is shown in FIGS. 4A to 4E . In FIG. 4A , a covering layer 16 with a thickness of about 1.2 μm is deposited over the bonding pads 14 of the substrate 12 . In FIG. 4B, the etching protective layer 16 forms an opening 36 to expose the bonding pad 14, and then a step 38 is also formed on the edge of the bonding pad 14. When the thickness of the protective layer 16 is thicker, the height of the step 38 is higher, and the opening 36 deeper. In FIG. 4C, titanium/tungsten with a thickness of about 800 angstroms is deposited as UBM18, and a gold film 20 with a thickness of about 800 angstroms is deposited. Because of the steps 38, the resulting steps 40 are wider. When the thickness of UBM18 is thicker, The width of the depression 42 is narrower. After patterning the UBM 18 and the gold film 20 is shown in FIG. 4D . In FIG. 4E , a gold bump 22 is grown from the gold film 20 to a thickness of about 17 μm. It has been shown from the foregoing process that the step 38 cannot be avoided. Therefore, a smaller effective area 32 must be obtained in the end, and the thicker the sheath 16 is, the greater the roughness h is, and the thicker the UBM 18 is, the smaller the effective area 32 is. Although the IC process can reduce the size of the components, the packaging technology in the back stage cannot keep up with the speed of the shrinking of the size of the components, thus limiting the minimum size of the chip.

已知的凸块结构在压合时也有缺点。参照图5的COG结构44,在压合凸块22至玻璃基板46上的导线48时,两者之间使用异方性导电膜(Anisotropic Conductive Film;ACF)50作为接口。ACF是一种含有导电粒子的胶状聚乙醯,其导电粒子在压合时受压迫而在压合方向上形成传导路径。由于凸块22的表面粗糙度约2μm,因此ACF50中的导电粒子52的粒径必须大于3μm才能在凸块22与导线48之间获得良好的传导。然而,粒径较大的导电粒子52导致在压合时被掳获在有效区域32内的数量较少,因此接触阻抗较大,压合后的导电品质较差。另一方面。在进行压合时,凸块间隙54内的导电粒子56因为粒径较大容易挤压变形而造成相邻凸块22之间发生短路与漏电,造成压合良率低。如果使用粒径较小的导电粒子52,则无法提供凸块22与导线48之间良好的连接,因此已知技术有无法克服的困难。随着IC尺寸的缩小与高脚数(I/O count)的需求,IC的接合垫14也缩小,有效区域32因而缩小,造成压合良率与压合后的导电品质降低。再者,覆晶封装的一项天生的缺点是凸块22边缘区域58的机械强度较弱,容易因为横向的拉扯而破裂。然而,要在凸块22表面得到较小的粗糙度h,必须减少阶梯28的高度,因此护层16的厚度较薄,如此机械强度较弱的缺点也无法克服。The known bump structures also have disadvantages during pressing. Referring to the COG structure 44 in FIG. 5 , when the bump 22 is bonded to the wire 48 on the glass substrate 46 , an anisotropic conductive film (Anisotropic Conductive Film; ACF) 50 is used as an interface between the two. ACF is a colloidal polyethylene containing conductive particles, and its conductive particles are compressed during pressing to form a conductive path in the pressing direction. Since the surface roughness of the bump 22 is about 2 μm, the size of the conductive particles 52 in the ACF 50 must be greater than 3 μm to obtain good conduction between the bump 22 and the wire 48 . However, the conductive particles 52 with a larger particle size lead to a smaller number trapped in the effective region 32 during lamination, so the contact resistance is larger, and the conductive quality after lamination is poor. on the other hand. During lamination, the conductive particles 56 in the gaps 54 of the bumps are easily squeezed and deformed due to their large particle size, causing short circuit and electric leakage between adjacent bumps 22 , resulting in a low lamination yield. If the conductive particles 52 with a smaller particle size are used, a good connection between the bump 22 and the wire 48 cannot be provided, so the known technology has insurmountable difficulties. With the reduction of IC size and the demand for high I/O count, the bonding pad 14 of the IC is also reduced, and the effective area 32 is thus reduced, resulting in a reduction in the bonding yield and the conductive quality after bonding. Furthermore, a natural disadvantage of the flip-chip package is that the mechanical strength of the edge region 58 of the bump 22 is weak, and it is easy to be broken due to lateral pulling. However, to obtain a smaller roughness h on the surface of the bump 22, the height of the step 28 must be reduced, so the thickness of the sheath 16 is thinner, and the disadvantage of weaker mechanical strength cannot be overcome.

因此,一种改良的凸块制作工艺及结构是人们所期待的。Therefore, an improved bump manufacturing process and structure is expected.

发明内容 Contents of the invention

本发明的主要目的,在于提出一种平坦化凸块制作工艺及结构,以改善已知技术的种种缺点。The main purpose of the present invention is to provide a planarized bump manufacturing process and structure to improve various shortcomings of the known technology.

根据本发明,一种凸块制作工艺包括形成一具有一平坦化表面的护层以覆盖一基板上的一接合垫,形成一开口穿过该护层以暴露该接合垫的一接触面,以及形成一凸块在该接合垫的该接触面及该护层的该平坦化表面上。According to the present invention, a bumping process includes forming a cover layer having a planarized surface to cover a bonding pad on a substrate, forming an opening through the cover layer to expose a contact surface of the bonding pad, and A bump is formed on the contact surface of the bonding pad and the planarized surface of the protective layer.

根据本发明,一种凸块结构包括一具有一平坦化表面的护层覆盖一基板上的一接合垫的一部分,以及一凸块接触该接合垫未被该护层覆盖的接触面及该护层的该平坦化的表面。According to the present invention, a bump structure includes a protective layer having a planarized surface covering a portion of a bonding pad on a substrate, and a bump contacts the contact surface of the bonding pad not covered by the protective layer and the protective layer. The planarized surface of the layer.

较好的情况是,该护层包括硬度不同的多膜层堆叠。Preferably, the covering comprises a stack of layers of different hardness.

较好的情况还有,该接触面具有一狭长形状。It is also preferred that the contact surface has an elongated shape.

由于该护层具有该平坦化表面的缘故,该接合垫可以缩小,该护层在该接合垫边缘区域的机械强度增加,在压合时,该凸块具有较大的有效区域,异方性导电膜的选择空间较大,凸块间隙内的短路及漏电机率降低,该凸块的压合良率及导电品质提高。Due to the flattened surface of the sheath, the bonding pad can be reduced, the mechanical strength of the sheath is increased in the edge region of the bonding pad, the bump has a larger effective area during lamination, anisotropy The selection space of the conductive film is large, the short circuit and electric leakage rate in the gap between the bumps are reduced, and the pressing yield and the conductive quality of the bump are improved.

附图说明 Description of drawings

图1是已知金凸块结构的剖面图;1 is a cross-sectional view of a known gold bump structure;

图2是加大图1中的凸块22后的示意图;Fig. 2 is a schematic diagram after enlarging the bump 22 in Fig. 1;

图3是在基底12上有多个凸块22的示意图;3 is a schematic diagram of a plurality of bumps 22 on the substrate 12;

图4A至图4E是已知的凸块制作工艺;4A to 4E are known bump manufacturing processes;

图5是已知的COG结构;Figure 5 is a known COG structure;

图6A及图6B是本发明金凸块结构的剖面图;6A and 6B are cross-sectional views of the gold bump structure of the present invention;

图7A及图7B是本发明金凸块结构的上视图;7A and 7B are top views of the gold bump structure of the present invention;

图8A至图8G是本发明金凸块制作工艺的第一实施例;8A to 8G are the first embodiment of the gold bump manufacturing process of the present invention;

图9A至图9D是本发明金凸块制作工艺的第二实施例;9A to 9D are the second embodiment of the gold bump manufacturing process of the present invention;

图10是本发明的COG结构;以及Figure 10 is the COG structure of the present invention; and

图11是增加护层厚度的金凸块结构。Fig. 11 is a gold bump structure with increased thickness of the protective layer.

主要元件符号说明:Description of main component symbols:

10:金凸块结构10: Gold bump structure

12:基板12: Substrate

14:接合垫14: Bonding Pad

16:护层16: Sheath

18:凸块底层金属18: Bump Underlying Metal

20:金膜20: gold film

22:金凸块22: Gold bump

24:二氧化硅24: Silica

26:氮化硅26: Silicon nitride

28:阶梯28: Ladder

30:阶梯30: Ladder

32:有效区域32: Effective area

34:无效区域34: invalid area

36:开口36: opening

38:阶梯38: Ladder

40:阶梯40: Ladder

42:凹陷42: sunken

44:COG结构44: COG structure

46:玻璃基板46: Glass substrate

48:导线48: Wire

50:异方性导电膜50: Anisotropic conductive film

52:导电粒子52: Conductive particles

54:凸块间隙54: Bump clearance

56:导电粒子56: Conductive particles

58:边缘区域58: Edge area

60:金凸块结构60: Gold bump structure

62:接合垫62: Bonding Pad

64:护层64: Sheath

66:金凸块66: Gold bump

68:无效区域68: invalid area

70:有效区域70: effective area

72:接触面72: contact surface

74:接触面74: contact surface

76:膜层76: film layer

78:平坦化表面78: Planarized Surface

80:膜层80: film layer

82:平坦化表面82: Planarized Surface

84:开口84: opening

86:平坦化表面86: Planarized Surface

88:GOG结构88: GOG structure

90:异方性导电膜90: Anisotropic conductive film

92:导电粒子92: Conductive particles

94:凸块间隙94: bump clearance

96:边缘区域96: Edge area

98:膜层98: film layer

具体实施方式 Detailed ways

根据本发明,一种金凸块结构60如图6A及图6B所示,其上视图如图7A及图7B所示,图6A是在X方向上的剖面图、图6B是在Y方向上的剖面图。参照图6A及图6B,在凸块结构60中,具有平坦化表面的护层64覆盖在基板12的接合垫62上,UBM18及金膜20堆叠在接合垫62与护层64上,金凸块66在金膜20上。接合垫62的材质为铝、铝合金、或其他高度导电的金属或合金。护层64包括一或多层二氧化硅、氮化硅或其它抗化性强的材料或其组合,以保护其下方基板12内的电路。UBM18主要在保护接合垫62避免后续工艺中各种化学分子侵入接合垫62影响产品电性,同时提高金膜20与接合垫62之间的黏着性,在一实施例中,接合垫62为铝,UBM18包含钛和钨,钛在底层,与铝有良好的共结面,钨在上层,与金有良好的共结面。如图6A所示,接合垫62在X方向上的宽度w1x远小于已知的接合垫,凸块66在X方向上的宽度w2x也较小,因此凸块节距p可以大幅缩小。然而在Y方向上,如图6B所示,虽然接合垫62的宽度w1y也较已知的接合垫小,但是凸块66的宽度w2y远大于接合垫62的宽度w1y。因为接合垫62较小,所以凸块66上表面中心的凹陷区域68缩得更小,如果UBM18较厚的话,凹陷区域68可以完全消失。由于使用具有平坦化表面的护层64,因此凸块66上表面大部分为平坦化的区域70,可供作为压合时的有效区域。与已知的凸块结构10不同,凸块66的有效区域70是在上表面的周围,而非中心,也就是说,主要在护层64上方的区域。According to the present invention, a gold bump structure 60 is shown in Figure 6A and Figure 6B, its top view is shown in Figure 7A and Figure 7B, Figure 6A is a cross-sectional view in the X direction, Figure 6B is in the Y direction sectional view. 6A and 6B, in the bump structure 60, the protective layer 64 with a planarized surface covers the bonding pad 62 of the substrate 12, the UBM 18 and the gold film 20 are stacked on the bonding pad 62 and the protective layer 64, and the gold bump Block 66 is on gold film 20 . The bonding pad 62 is made of aluminum, aluminum alloy, or other highly conductive metal or alloy. The protective layer 64 includes one or more layers of silicon dioxide, silicon nitride, or other highly chemically resistant materials or a combination thereof, to protect the circuitry in the underlying substrate 12 . UBM18 is mainly used to protect the bonding pad 62 to prevent various chemical molecules from invading the bonding pad 62 in the subsequent process to affect the electrical properties of the product, and at the same time improve the adhesion between the gold film 20 and the bonding pad 62. In one embodiment, the bonding pad 62 is made of aluminum , UBM18 contains titanium and tungsten, titanium is on the bottom layer, has a good co-junction with aluminum, and tungsten is on the top, and has a good co-junction with gold. As shown in FIG. 6A , the width w1x of the bonding pad 62 in the X direction is much smaller than that of known bonding pads, and the width w2x of the bump 66 in the X direction is also smaller, so the bump pitch p can be greatly reduced. However, in the Y direction, as shown in FIG. 6B , although the width w1y of the bond pad 62 is also smaller than that of known bond pads, the width w2y of the bump 66 is much larger than the width w1y of the bond pad 62 . Because the bonding pad 62 is smaller, the recessed area 68 in the center of the upper surface of the bump 66 shrinks even smaller, and the recessed area 68 can disappear completely if the UBM 18 is thicker. Since the protective layer 64 with a planarized surface is used, most of the upper surface of the bump 66 is a planarized area 70 , which can be used as an effective area during lamination. Unlike the known bump structure 10 , the active area 70 of the bump 66 is at the periphery of the upper surface rather than at the center, ie, the area mainly above the covering layer 64 .

图7A进一步显示凸块66与接合垫62的关系,为了比较,已知的凸块22与接合垫14也显示在图7A的右侧。在已知的凸块结构10中,接合垫14比凸块22大,凸块22为得到足够的有效区域,接合垫14不能缩小。而在本发明的凸块结构60中,凸块66可以比接合垫62大,因此接合垫62可以尽量缩小。在本发明的凸块结构60中,接合垫62露出供连接凸块66的接触面72具有狭长形状。而在已知的凸块结构10中。接合垫14露出供连接凸块22的接触面74在X与Y方向上的宽度接近。图7B是在基板12上形成高密度凸块66的示意图,凸块66呈狭长条状在Y方向上延伸。在X方向上,由于接合垫62可以缩小,因此凸块66可以更紧密地排列,如果要增加凸块66的平坦化区域70,可以通过增加其Y方向的宽度而达成。由于接合垫62可以缩小,因此在相同尺寸的IC中可以容纳更多的凸块66,提高IC的接点密度及脚数。FIG. 7A further shows the relationship of bump 66 to bond pad 62 . For comparison, the known bump 22 and bond pad 14 are also shown on the right side of FIG. 7A . In the known bump structure 10 , the bonding pad 14 is larger than the bump 22 , and the bonding pad 14 cannot be shrunk in order to obtain sufficient effective area of the bump 22 . However, in the bump structure 60 of the present invention, the bump 66 can be larger than the bonding pad 62, so the bonding pad 62 can be reduced as much as possible. In the bump structure 60 of the present invention, the contact surface 72 exposed by the bonding pad 62 for connecting the bump 66 has an elongated shape. But in the known bump structure 10 . The bonding pad 14 is exposed for the contact surface 74 of the connecting bump 22 to have a width close to that in the X and Y directions. FIG. 7B is a schematic diagram of forming high-density bumps 66 on the substrate 12 , and the bumps 66 are elongated and extend in the Y direction. In the X direction, since the bond pads 62 can be shrunk, the bumps 66 can be arranged more closely. If the planarized area 70 of the bumps 66 is to be increased, it can be achieved by increasing the width of the bumps 66 in the Y direction. Since the bonding pads 62 can be reduced, more bumps 66 can be accommodated in an IC of the same size, increasing the contact density and the number of pins of the IC.

图8A至图8G是根据本发明的凸块制作工艺。在图8A中,沉积例如二氧化硅或氧化硅的膜层76约1000至1200埃覆盖基板12上的接合垫62。以例如化学机械研磨法回蚀刻膜层76至留下约600至800埃的厚度,因而使其具有平坦化表面78,如图8B所示。在图8C中,在膜层76上沉积例如氮化硅或氮氧化硅的膜层80约300至500埃,由于膜层76的平坦化表面78,膜层80也具有平坦化表面82。膜层76及80作为图6A中的护层64,较好的情况是,膜层80的材质比膜层76硬,较软的膜层76用来保护基板12及接合垫62的表面,较硬的膜层80用来抵抗外力。如图8D所示,蚀刻膜层80及76形成开口84从平坦化表面82穿过膜层80及76,暴露接合垫62的接触面72。在图8E中,以溅镀法沉积例如钛及钨约800埃作为UBM18在接合垫62的接触面72及膜层80的表面82上,以溅镀法沉积约800埃的金膜20在UBM18上。如图8F所示,图案化金膜20及UBM18。在图8G中,以电镀法从金膜20成长金凸块66约15至20μm。由于在先前的步骤中形成具有平坦化表面的护层76及80,因此凸块66上表面中心的凹陷68很小或没有凹陷,大部分为平坦化的区域70。8A to 8G are bump fabrication processes according to the present invention. In FIG. 8A , a film layer 76 such as silicon dioxide or silicon oxide is deposited to about 1000 to 1200 Angstroms over the bond pads 62 on the substrate 12 . The film layer 76 is etched back to a thickness of about 600 to 800 angstroms by, for example, chemical mechanical polishing, so that it has a planarized surface 78, as shown in FIG. 8B. In FIG. 8C , a layer 80 such as silicon nitride or silicon oxynitride is deposited at about 300 to 500 Angstroms on layer 76 , which also has a planarized surface 82 due to the planarized surface 78 of layer 76 . The film layers 76 and 80 are used as the protective layer 64 in FIG. 6A. Preferably, the material of the film layer 80 is harder than the film layer 76, and the softer film layer 76 is used to protect the surface of the substrate 12 and the bonding pad 62. The hard film layer 80 is used to resist external force. As shown in FIG. 8D , etching of the membrane layers 80 and 76 forms an opening 84 from the planarized surface 82 through the membrane layers 80 and 76 , exposing the contact surface 72 of the bonding pad 62 . In FIG. 8E, about 800 angstroms of titanium and tungsten are deposited as UBM18 on the contact surface 72 of the bonding pad 62 and the surface 82 of the film layer 80 by sputtering, and about 800 angstroms of gold film 20 is deposited on the UBM18 by sputtering. superior. As shown in FIG. 8F , the gold film 20 and the UBM 18 are patterned. In FIG. 8G, gold bumps 66 are grown from the gold film 20 by about 15 to 20 [mu]m by electroplating. Due to the formation of the protective layers 76 and 80 with planarized surfaces in the previous step, there is little or no depression 68 in the center of the upper surface of the bump 66 , mostly the planarized area 70 .

图9A至图9D是根据本发明的另一凸块制作工艺。在图9A中,连续沉积膜层76及80覆盖基板12上的接合垫62,较好的情况是,膜层80的材质比膜层76硬,较软的膜层76用来保护基板12及接合垫62的接触面,较硬的膜层80用来抵抗外力,例如,膜层76包含二氧化硅或氧化硅,厚度约200至800埃,膜层80包含氮化硅或氮氧化硅,厚度约300至500埃。在图9B中,以例如化学机械研磨法回蚀刻至膜层76及80的总厚度约600至1000埃的厚度,因而形成平坦化表面86。在图9C中,形成开口84暴露接合垫62的接触面72。在图9D中,以溅镀法沉积例如钛及钨约800埃作为UBM18在接合垫62的接触面72及平坦化表面86上,以溅镀法沉积约800埃的金膜20在UBM18上,图案化金膜20及UBM18,以电镀法从金膜20成长金凸块66约15至20μm。由于在先前的步骤中形成的平坦化表面86,因此凸块66上表面中心的凹陷68很小或没有凹陷,大部分为平坦化的区域70。9A to 9D are another bump fabrication process according to the present invention. In FIG. 9A, film layers 76 and 80 are continuously deposited to cover the bonding pads 62 on the substrate 12. Preferably, the material of the film layer 80 is harder than the film layer 76, and the softer film layer 76 is used to protect the substrate 12 and the substrate 12. On the contact surface of the bonding pad 62, a harder film layer 80 is used to resist external forces. For example, the film layer 76 includes silicon dioxide or silicon oxide with a thickness of about 200 to 800 angstroms, and the film layer 80 includes silicon nitride or silicon oxynitride. The thickness is about 300 to 500 Angstroms. In FIG. 9B , etch back to a total thickness of about 600 to 1000 angstroms of the film layers 76 and 80 by, for example, chemical mechanical polishing, thereby forming a planarized surface 86 . In FIG. 9C , opening 84 is formed to expose contact surface 72 of bond pad 62 . In FIG. 9D, about 800 angstroms of titanium and tungsten are deposited as UBM18 on the contact surface 72 and the planarized surface 86 of the bonding pad 62 by sputtering, and a gold film 20 of about 800 angstroms is deposited on the UBM18 by sputtering. The gold film 20 and the UBM 18 are patterned, and gold bumps 66 are grown from the gold film 20 to a thickness of about 15 to 20 μm by electroplating. Due to the planarized surface 86 formed in the previous step, there is little or no depression 68 in the center of the upper surface of the bump 66 , mostly the planarized area 70 .

在本发明的凸块制作工艺中,因为使用具有平坦化表面的护层64,所以UBM18在该平坦化表面上的面积可以远大于在接触面72上的面积,得到很大的有效区域70,因此可以将接合垫62尽量缩小。In the bump manufacturing process of the present invention, because the protective layer 64 with a planarized surface is used, the area of the UBM 18 on the planarized surface can be much larger than the area on the contact surface 72, resulting in a large effective area 70, Therefore, the bonding pad 62 can be made as small as possible.

图10显示压合凸块66至玻璃基板46上的导线48的结构88,与已知的COG结构44不同,凸块66提供压合的有效区域是平坦化的区域70,由于没有表面粗糙度的问题,因此ACF90中的导电粒子92的粒径有较大的选择空间,例如1至5μm,即使使用粒径较小的导电粒子92依然可以获得良好的导电品质。因为有效区域是平坦化的区域70,其面积较大,因此在压合时有效区域70可以掳获较多的导电粒子92,如果使用粒径较小的导电粒子92,掳获的数量更多,导电品质更好。另一方面,如果使用粒径较小的导电粒子92,在凸块间隙94内的导电粒子92受挤压而发生短路或漏电的机率降低。再者,由于使用具有平坦化表面的护层64,因此凸块66边缘区域96的机械强度提高,较不易发生破裂。由于在凸块结构60中使用具有平坦化表面的护层64,因此其厚度不会受到局限,图11是一示例,护层64包含膜层76、80及98,膜层76及98使用二氧化硅或氧化硅,膜层80使用氮化硅或氮氧化硅,并且膜层76、80及98的总厚度提高至1.2μm以上,因此增加机械强度。Figure 10 shows a structure 88 for bonding the bump 66 to the wire 48 on the glass substrate 46. Unlike the known COG structure 44, the effective area of the bump 66 to provide the bonding is the planarized area 70, since there is no surface roughness Therefore, the particle size of the conductive particles 92 in the ACF90 has a large selection space, for example, 1 to 5 μm. Even if the conductive particles 92 with a smaller particle size are used, good conductive quality can still be obtained. Because the effective area is a planarized area 70 with a larger area, more conductive particles 92 can be captured in the effective area 70 during lamination. If conductive particles 92 with smaller particle diameters are used, more conductive particles will be captured. , better conductive quality. On the other hand, if the conductive particles 92 with a smaller particle size are used, the probability of short circuit or electric leakage due to the compression of the conductive particles 92 in the bump gap 94 is reduced. Furthermore, due to the use of the cover layer 64 with a planarized surface, the mechanical strength of the edge region 96 of the bump 66 is improved and cracking is less likely to occur. Since the protective layer 64 with a planarized surface is used in the bump structure 60, its thickness will not be limited. FIG. 11 is an example. The protective layer 64 includes film layers 76, 80 and 98. Silicon oxide or silicon oxide, the film layer 80 uses silicon nitride or silicon oxynitride, and the total thickness of the film layers 76, 80 and 98 is increased to more than 1.2 μm, thus increasing the mechanical strength.

Claims (36)

1. producing lug technology is used for forming a projection and is electrically connected to a joint sheet on a substrate, it is characterized in that this technology comprises the following steps:
Form one and have the sheath of a planarized surface to cover this joint sheet;
Form an opening and pass this sheath to expose a contact-making surface of this joint sheet; And
Form this projection on this planarized surface of this contact-making surface of this joint sheet and this sheath.
2. producing lug technology as claimed in claim 1 is characterized in that, the step that described formation one has the sheath of a planarized surface comprises the following steps:
Depositing one first rete covers on this joint sheet;
One surface of this first rete of planarization; And
Deposit one second rete on this first rete.
3. producing lug technology as claimed in claim 2 is characterized in that, described second rete comprises that at least one layer material is hard than this first rete.
4. producing lug technology as claimed in claim 2 is characterized in that, described first rete comprises silicon dioxide or silica, and this second rete comprises silicon nitride or silicon oxynitride.
5. producing lug technology as claimed in claim 2 is characterized in that, described first rete comprises silicon dioxide or silica, and described second rete comprises that one deck is silicon nitride or silicon oxynitride, and another layer is the lamination of silicon dioxide or silica.
6. producing lug technology as claimed in claim 2 is characterized in that, the step on a surface of this first rete of described planarization comprises this first rete of etch-back.
7. producing lug technology as claimed in claim 6 is characterized in that, the step of this first rete of described etch-back comprises this first rete of cmp.
8. producing lug technology as claimed in claim 1 is characterized in that, the step that described formation one has the sheath of a planarized surface comprises the following steps:
Depositing a lamination covers on this joint sheet; And
One surface of this lamination of planarization.
9. producing lug technology as claimed in claim 8 is characterized in that, described lamination comprises:
One first rete; And
One second rete is on this described first rete, and this second rete is hard than this first rete.
10. producing lug technology as claimed in claim 9 is characterized in that, described first rete comprises silicon dioxide or silica, and described second rete comprises silicon nitride or silicon oxynitride.
11. producing lug technology as claimed in claim 8 is characterized in that, described lamination comprises:
One first rete;
One second rete is on this first rete, and this second rete is hard than this first rete; And
One tertiary membrane layer is on this second rete, and this tertiary membrane layer is soft than this second rete.
12. producing lug technology as claimed in claim 11 is characterized in that, described first and the tertiary membrane layer comprise silicon dioxide or silica, described second rete comprises silicon nitride or silicon oxynitride.
13. producing lug technology as claimed in claim 8 is characterized in that, the step on a surface of described this lamination of planarization comprises this lamination of etch-back.
14. producing lug technology as claimed in claim 13 is characterized in that, the step of described this lamination of etch-back comprises this lamination of cmp.
15. producing lug technology as claimed in claim 1 is characterized in that, described opening has an elongated shape on this contact-making surface of this joint sheet.
16. producing lug technology as claimed in claim 1 is characterized in that, the step of this projection of described formation on this planarized surface of this contact-making surface of this joint sheet and this sheath comprises the following steps:
Form a projection underlying metal and have a second area having on this contact-making surface of this joint sheet on one first area and this planarized surface at this sheath, this second area is greater than this first area; And
Form a conductive projection and contact this projection underlying metal.
17. producing lug technology as claimed in claim 16 is characterized in that, the step that described formation one conductive projection contacts this projection underlying metal comprises the following steps:
Sputter one gold medal film is on this projection underlying metal; And
From this gold film gold medal projection of growing up.
18. producing lug technology as claimed in claim 1 is characterized in that, the step of this projection of described formation on this planarized surface of this contact-making surface of this joint sheet and this sheath comprises the following steps:
Form a projection underlying metal on this planarized surface of this contact-making surface of this joint sheet and this sheath; And
Form a conductive projection and contact this projection underlying metal, this conductive projection has the surface of a planarization at the opposite side with respect to this projection underlying metal.
19. producing lug technology as claimed in claim 18 is characterized in that, the step that described formation one conductive projection contacts this projection underlying metal comprises the following steps:
Sputter one gold medal film is on this projection underlying metal; And
From this gold film gold medal projection of growing up.
20. producing lug technology as claimed in claim 1 is characterized in that the area of described conductive projection is greater than the area of this joint sheet.
21. a projection cube structure is used for being electrically connected to the joint sheet on a substrate, it is characterized in that this projection cube structure comprises:
One sheath with a planarized surface covers the part of this joint sheet; And
One projection contacts the surface of this planarization of contact-making surface that this joint sheet do not cover by this sheath and this sheath.
22. projection cube structure as claimed in claim 21 is characterized in that, described sheath comprises:
One has first rete of a planarized surface; And
One second rete is on this first rete.
23. projection cube structure as claimed in claim 22 is characterized in that, described second rete comprises that at least one layer material is hard than this first rete.
24. projection cube structure as claimed in claim 22 is characterized in that, described first rete comprises silicon dioxide or silica, and described second rete comprises silicon nitride or silicon oxynitride.
25. projection cube structure as claimed in claim 22 is characterized in that, described first rete comprises silicon dioxide or silica, and described second rete comprises that one deck is silicon nitride or silicon oxynitride, and another layer is the lamination of silicon dioxide or silica.
26. projection cube structure as claimed in claim 21 is characterized in that, described sheath comprises:
One first rete; And
One has second rete of this planarized surface on this first rete.
27. projection cube structure as claimed in claim 26 is characterized in that, described second rete comprises that at least one layer material is hard than this first rete.
28. projection cube structure as claimed in claim 26 is characterized in that, described first rete comprises silicon dioxide or silica, and described second rete comprises silicon nitride or silicon oxynitride.
29. projection cube structure as claimed in claim 26 is characterized in that, described first rete comprises silicon dioxide or silica, and described second rete comprises that one deck is silicon nitride or silicon oxynitride, and another layer is the lamination of silicon dioxide or silica.
30. projection cube structure as claimed in claim 21 is characterized in that, described sheath comprises that two retes press from both sides a rete hard than this two rete.
31. projection cube structure as claimed in claim 21 is characterized in that, described joint sheet is not had an elongated shape by this contact-making surface that this sheath covers.
32. projection cube structure as claimed in claim 21 is characterized in that, described projection comprises:
One projection underlying metal has a second area having on this contact-making surface that is not covered by this sheath of this joint sheet on one first area and the surface in this planarization of this sheath, and this second area is greater than this first area; And
One conductive projection is on this projection underlying metal.
33. projection cube structure as claimed in claim 32 is characterized in that, described conductive projection comprises:
One gold medal film is on this projection underlying metal; And
One gold medal projection is on this gold film.
34. projection cube structure as claimed in claim 21 is characterized in that, described projection comprises:
One projection underlying metal is on the surface of this planarization of this contact-making surface that is not covered by this sheath of this joint sheet and this sheath; And
One conductive projection contacts this projection underlying metal, and this conductive projection has the surface of a planarization at the opposite side with respect to this projection underlying metal.
35. projection cube structure as claimed in claim 21 is characterized in that, the area of described conductive projection is greater than the area of this joint sheet.
36. a projection pressing structure is used for being electrically connected at a joint sheet and a lead on one second substrate on one first substrate, it is characterized in that this projection pressing structure comprises:
One sheath with a planarized surface covers the part of this joint sheet;
One projection contacts the surface of this planarization of contact-making surface that this joint sheet do not cover by this sheath and this sheath, and this projection has the surface of the surface of a planarization in the face of this planarization of this sheath; And
Between the surface and this lead of oppressed this planarization in this projection of many conducting particless.
CNB200510069102XA 2005-05-10 2005-05-10 bump manufacturing process and structure Expired - Fee Related CN100405548C (en)

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CN1372312A (en) * 2001-02-26 2002-10-02 华泰电子股份有限公司 Wafer wire bonding metal bump packaging structure and manufacturing method thereof
US20040222520A1 (en) * 2002-09-19 2004-11-11 Yonggang Jin Integrated circuit package with flat metal bump and manufacturing method therefor
US20050017343A1 (en) * 2003-07-23 2005-01-27 Kwon Yong-Hwan Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same

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