CN100403653C - Maximum jitter tolerance deviation calibration method and device thereof - Google Patents

Abstract

The present invention provides a maximum jitter tolerance deviation calibration method and device for a phase-locked loop, the phase-locked loop includes a phase detector and a charge extractor connected in series, the method provides a first correction signal and a second correction signal to the phase detector for phase detection, so as to generate a rising pulse and a falling pulse according to the phase difference between the two to control the charge extractor to generate a net current, and utilizes a correction unit to selectively adjust the pulse width of the rising or falling pulse according to the net current until the net current reaches a target value, thereby calibrating the jitter deviation caused by the characteristic curves of the phase detector and the charge extractor.

Description

Method and device for calibrating maximum jitter tolerance deviation

technical field

The invention relates to a method and device for calibrating the maximum jitter tolerance deviation of a phase-locked loop, in particular to a calibration method that can effectively calibrate the characteristic deviation of the internal circuit of the phase-locked loop so that the phase-locked loop has the maximum jitter tolerance deviation and its devices.

Background technique

As shown in Figure 1, it is a typical phase-locked loop system 1, which includes a phase detector 11, a charge extractor 12, a loop filter 13, and a voltage-controlled oscillator (VCO) connected in series to form a loop. 14 and a frequency divider 15. The mode of operation of this phase-locked loop system 1 is that the phase detector 11 detects the phase difference between an input signal IN and a clock signal CLK generated by a voltage-controlled oscillator 14 and properly divided by a frequency divider 15, and according to the phase difference between the two The phase difference between them generates a rising pulse UP and a falling pulse DN to the charge extractor 12 for calculation, then outputs a current I _cp , and the current I _cp is then integrated (averaged) by a loop filter 13 and converted into a control voltage V _ct controls the voltage-controlled oscillator 14 to output a voltage-controlled signal correspondingly, so that the frequency of the clock signal CLK generated by the frequency-divided voltage-controlled signal by the frequency divider 15 can approach the frequency of the input signal IN to lock the input signal IN. Therefore, when the phase of the clock signal CLK is ahead of the input signal IN (that is, the frequency of the clock signal CLK is greater than that of the input signal IN), the phase detector 11 generates a rising pulse UP with a narrower width or a falling pulse DN with a wider width for the The charge extractor 12 makes the net current (average value) of the generated current I _cp positive, and integrates the loop filter 12 to generate a reduced voltage V _ct , and controls the voltage-controlled oscillator 14 to set the frequency of the clock signal CLK reduce. And when the phase of the clock signal CLK lags behind the input signal IN (that is, the frequency of the clock signal CLK is lower than the input signal IN), the phase detector 11 will generate a wider rising pulse UP or a narrower falling pulse DN to control The charge extractor 12 makes the generated net current a negative value, and makes the loop filter 13 output a rising voltage V _ct to drive the voltage-controlled oscillator 14 to increase the frequency of the clock signal CLK, thereby, when the net current When it approaches zero, the frequency of the clock signal CLK will gradually approach the input signal IN, and when the net current is equal to zero, the output voltage V _ct becomes a certain value, and the frequency and phase of the clock signal CLK are consistent with the input signal IN and locked .

However, in the general PLL system 1, the transfer curves of the phase detector 11 and the charge extractor 12 are usually not ideal, so that the phase lock point is shifted on the transfer curve, resulting in a reduction in the jitter tolerance, and such as In the situation shown in Figure 2, the phase lock point is the point A shown in the figure, that is, the point where the phase difference is zero. Although the positive phase jitter tolerance error of point A is greater than 1T, the maximum negative phase jitter tolerance error is only -0.625T, however, in an ideal situation, the phase lock point should be at point B in the diagram, and its positive and negative phase jitter tolerance errors will be 1T and -1T respectively. Therefore, if the transfer curves of the phase detector 11 and the charge extractor 12 are unsatisfactory, the maximum jitter allowable deviation will be reduced, resulting in poor phase-locking capability of the phase-locked loop.

Contents of the invention

Therefore, the object of the present invention is to provide a method and device for calibrating the maximum jitter tolerance deviation of a phase-locked loop, which can effectively calibrate the characteristic deviation of the internal circuit of the phase-locked loop system, so that the phase-locked loop system has a maximum jitter tolerance deviation scope.

Therefore, the method for calibrating the maximum jitter tolerance deviation of the phase-locked loop of the present invention, wherein the phase-locked loop includes a phase detector, a charge extractor, a loop filter and a voltage-controlled oscillator sequentially connected in series to form a loop. The method includes (a) temporarily opening the loop filter with the charge pump and the voltage controlled oscillator. (b) Provide a first correction signal and a second correction signal to the phase detector for phase detection, so that a rising pulse and a falling pulse are generated to the charge pump according to the phase difference between the two, so that the charge pump According to, to produce a net current. (c) Adjusting the pulse widths of the rising pulse and the falling pulse according to the net current until the net current output by the charge extractor reaches a target value. Thereby, the characteristic deviation of the phase detector and the charge extractor of the phase-locked loop is effectively calibrated, so as to have the largest jitter allowable deviation range.

Therefore, the present invention implements the maximum jitter tolerance calibration device of the phase-locked loop of the above method, wherein the phase-locked loop includes a phase detector, a charge extractor, a loop filter and a voltage control circuit connected in series in sequence. An oscillator, and when the device performs a calibration procedure, the loop filter is temporarily open with the charge extractor and the voltage-controlled oscillator, and the device includes a signal generating unit and a calibration unit. The signal generation unit is used to provide a first correction signal and a second correction signal to the phase detector, so that the phase detection of the two signals is performed, and a rising pulse and a falling pulse are generated according to the measured phase difference to The charge extractor is used to generate a net current according to the charge extractor. The calibration unit adjusts the pulse widths of the rising pulse and the falling pulse according to the net current until the net current output by the charge extractor reaches a target value.

Description of drawings

Other features and advantages of the present invention will be clearly understood in the following detailed description of the preferred embodiment with reference to the drawings, in the drawings:

Fig. 1 is a circuit block diagram of a typical phase-locked loop system;

Fig. 2 is the conversion curve of the output pulse width and the phase difference of the phase detector in the typical phase-locked loop system;

Fig. 3 is the circuit block diagram of a preferred embodiment of the maximum jitter tolerance calibration method and device of the phase-locked loop of the present invention;

Fig. 4 is a detailed circuit diagram of the integrator of the maximum jitter tolerance calibration device in this embodiment;

Fig. 5 is the conversion curve of the output pulse width and phase difference of the phase detector after applying the method of the present embodiment; and

FIG. 6 is a circuit block diagram of the present embodiment, which shows that the PLL operates in a normal mode.

Component designation comparison

2 phase locked loop

3 The maximum jitter allowable deviation calibration device of the phase-locked loop

21 Phase Detector 22 Charge Dump

23 Loop Filter 24 Voltage Controlled Oscillator

25 Frequency divider 31 Signal generating unit

32 Correction unit 33 Pulse generating circuit

34 Integrator 35 Analog/Digital Converter

36 decision circuit 37 rising pulse extender

38 falling pulse extender 210 first multiplexer

240 second multiplexer 341 operational amplifier

I _CP Current VR Voltage Source

V _err correction voltage C1 capacitor

V _ct control voltage CAL1 first correction signal

CAL2 second correction signal IN input signal

CLK clock signal

Detailed ways

Referring to Fig. 3, it is a circuit block diagram of a preferred embodiment of the method and device for calibrating the maximum jitter tolerance deviation of the phase-locked loop of the present invention, wherein the phase-locked loop 2 includes a phase detector 21 connected in series to form a loop , a charge extractor 22, a loop filter 23, a voltage-controlled oscillator (VCO) 24, and a frequency divider 25, and the mode of operation of the phase-locked loop 2 has been described in the aforementioned known technology, and will not be repeated here restate.

The maximum jitter tolerance calibration device 3 of the PLL of the present invention includes a signal generating unit 31 and a correction unit 32, and the maximum jitter tolerance calibration method of the PLL of the present invention includes the following steps:

Firstly, the signal generating unit 31 provides a first calibration signal CAL1 and a second calibration signal CAL2 with different frequencies to the phase detector 21 . In this embodiment, the signal generating unit 31 includes a pulse generator 33 for generating the first correction signal CAL1, and provides a voltage source VR to the voltage-controlled oscillator 24 to generate the second correction signal CAL2, and due to general The phase detector 21 designs the initial width of the rising pulse UP and the falling pulse DN according to the center frequency of the input signal IN, so that the maximum and optimal phase difference change is measured for energy, and the first correction signal CAL1 is usually taken from the input signal IN For example, when the frequency range of the input signal IN is from 1MHz to 10MHz, the frequency of the first correction signal CAL1 is 5.5MHz, and the second correction signal CAL2 is based on the system’s demand for sampling clock signals. For example, if the system sets the operating frequency of the sampling clock signal to 100MHz, then the second correction signal takes 100MHz as its correction frequency. In addition, in order to control the PLL 2 to operate in the calibration mode or the normal operation mode, a first multiplexer 210 is provided at the input signal terminal INX of the phase detector 21, and the first multiplexer 210 is configured to The input end is respectively connected to an input signal IN and the output end of the first correction signal CAL1 of the pulse generator 33. In addition, a second multiplexer 240 is provided at the input end of the voltage-controlled oscillator 24, and the second multiplexer The input terminals of the device 240 are respectively connected to the control voltage V _ct output terminal of the loop filter 23 and the voltage source VR. Therefore, when performing the calibration mode, the first multiplexer 210 is controlled and selectively connected to the pulse generator 33 and the phase detector 21, and the second multiplexer 240 is selectively connected to the constant voltage source VR and the voltage-controlled oscillator 24, The loop filter 23, the charge extractor 22 and the voltage-controlled oscillator 24 are temporarily open-circuited. At this time, the first correction signal CAL1 and the second correction signal CAL2 are sent to the phase detector 21 for phase detection, so that the phase detector 21 outputs a rising pulse UP and a falling pulse DN according to the phase difference between the two. The pulse UP and the down pulse DN are sent to the charge extractor 22 to generate a current I _cp after being subtracted. The current _Icp represents the phase difference between the second correction signal CAL2 and the first correction signal CAL1, and since the phase difference between the second correction signal CLK2 and the first correction signal CAL1 changes with time, the current I The size and the polarity of _cp are also constantly changing accordingly, and under the ideal situation of the phase-locked loop 2, the average value (i.e. the net current value) of the current I _cp of these changes should be zero (or close to zero), However, due to the non-ideal characteristics of the transfer curves of the phase detector 21 and the charge extractor 22 of the phase-locked loop 2, the rising pulse UP and the falling pulse DN output by the phase detector 21 have a deviation, and the charge extractor 22 generates The current I _cp has an offset value, so that the net current (average value) is not zero, thus producing the above-mentioned phase lock point shift. Therefore, if the net current can be made zero, the phase locking point can be corrected. Therefore, the net current is sent to the correction circuit 32 to correct the above-mentioned irrational situation.

As shown in Figure 3, the correction circuit 32 comprises an integrator 34 connected with the charge extractor 22, an analog/digital converter 35 connected with the integrator 34, a decision making device connected with the analog/digital converter 35 Circuit 36, and a rising pulse extender 37 and a falling pulse extender 38, which are controlled by the decision circuit 36 and connected between the phase detector 21 and the charge extractor 22, to adjust the rising pulse UP and the charge extractor 22 respectively. Pulse width of falling pulse DN. When the current _ICP output by the charge extractor 22 is sent into the integrator 34, as shown in FIG. Therefore, the positive or negative current I _CP flowing in from the negative terminal of the operational amplifier 341 will start to charge and discharge the capacitor C1 to obtain a net current value (ie, the average value of the current I _CP ), and in the operational amplifier 341 The output terminal generates a relative correction voltage _Verr (assuming that the initial value of the correction voltage _Verr is zero). Then the correction voltage V _err is sent to the analog/digital converter 35 for digitization and then sent to the decision circuit 36, and the decision circuit 36 _selects and adjusts the rising pulse according to the magnitude and positive and negative polarity of the digitized correction voltage Verr Pulse width of UP or down pulse DN. For example, when the net current output from the charge extractor 22 to the integrator 34 is positive, the integrator 34 will relatively generate a negative correction voltage V _err , and make the decision circuit 36 control the falling pulse extender 38 to make the falling The width of the pulse DN is extended to drive the charge extractor 22 to generate a negative current I _CP , and when the average (net current) of the current I _CP output by the charge extractor 22 is negative, the integrator 34 relatively generates a positive current I CP . correction voltage V _err , the decision-making circuit 36 controls the rising pulse extender 37 to extend the width of the rising pulse UP by a certain range according to the positive correction voltage _Verr , and drives the charge extractor 22 to generate a positive net current, thereby As the above-mentioned feedback control process is repeated, the net current value output by the charge pump 22 will gradually decrease and the correction voltage V _err will tend to zero. At the same time, the width of the rising pulse UP and the falling pulse DN will also pass through the rising pulse expander 37 and The proper expansion of the falling pulse extender 38 compensates the deviation of the output pulse width and the current I _CP caused by the characteristic curves of the phase detector 21 and the charge extractor 22, and when the net current reaches a target value (the target value here When referring to the minimum net current value), the best calibration state is reached. At this moment, the correction voltage V _err is almost zero, and the rising pulse extender 37 and the falling pulse extender 38 are kept in the final extension range (that is, the correction range) , therefore, by such an extension amplitude, as shown in Figure 5, the average value position of the rising pulse UP curve will be the same as the average value position of the falling pulse DN curve, and because in the present embodiment, the width of the falling pulse DN To be fixed, only adjust the width of the rising pulse UP, so the average position of the rising pulse UP curve will be equal to the position of the falling pulse DN curve, so the corrected phase lock point is point B in the figure, and its positive and negative phase jitter tolerance error They are 1T and -1T respectively, so the maximum jitter tolerance is increased.

Therefore, after the above-mentioned calibration procedure is completed, when the PLL 2 is switched to work in the normal mode, as shown in FIG. 6, the first multiplexer 210 connects the input signal IN to the phase detector 21, and the second multiplexer 210 The converter 240 connects the loop filter 23 to the voltage-controlled oscillator 24, and the voltage-controlled oscillator 24 correspondingly outputs a clock signal CLK and the input signal IN according to the control voltage V _ct generated by the charge extractor 22 through the loop filter 23. input into the phase detector 21 for phase detection, and the rising pulse UP and falling pulse DN correspondingly output by the phase detector 21 according to the phase difference between the two will pass through the rising pulse extender 37 and the falling pulse extender 38 according to their final expansion After the amplitude is appropriately expanded, it is sent to the charge extractor 22, thereby eliminating the deviation between the rising pulse UP and the falling pulse DN caused by the characteristic curve of the phase detector 21, and the net current I _CP caused by the non-ideality of the charge extractor 22 The deviation, so that when there is a large positive phase difference (1T, 0-180 degrees) or negative phase difference (-1T, 0-180 degrees) between the clock signal CLK and the input signal IN, the phase-locked loop 2 is still It can track and correspondingly generate a negative net current or a positive net current to the loop filter 23 to generate a relative control voltage V _ct to control the voltage-controlled oscillator 24 to gradually reduce the phase difference between the clock signal CLK and the input signal IN to lock , thus improving the phase-locking capability of the phase-locked loop 2, and enabling the phase-locked loop 2 to track and lock the phase deviation range to the maximum.

In summary, the present invention provides the first correction signal CAL1 and the second correction signal CAL2 with specific frequencies to be input into the phase detector 21 by making the phase-locked loop 2 in a correction mode, so that according to the phase difference between the two The rising pulse UP and the falling pulse DN are generated to be input into the charge pump 22, and the corresponding current I _CP is generated, and the non-zero value generated by the non-ideal characteristics of the phase detector 21 and the charge pump 22 is obtained from the current I _CP net current value, and by inputting the net current value into the integrator 34 and the analog/digital converter 35 of the correction circuit 32, integrating and digitizing to generate a correction voltage V _err , and the decision circuit 36 according to the correction voltage V The polarity selection of _err controls the rising pulse extender 37 and the falling pulse extender 38 to extend the pulse widths of the rising pulse UP and the falling pulse DN to an appropriate extent, tending to make the net current output by the charge extractor 22 reach the minimum, and then correct And compensate the non-ideal characteristics of the phase detector 21 and the charge extractor 22, and correct its phase lock point, thereby, when the phase locked loop 2 is working in the normal mode, it has the largest phase jitter tolerance range, and then improves the lock Phase lock capability of phase loop 2.

The above is only a preferred embodiment of the present invention, when the scope of the present invention cannot be limited with this, the simple equivalent changes and improvements made according to the scope of the claims of the present invention and the content of the description of the invention should still belong to this invention. scope of the invention.

Claims (12)

1. the acceptable deviation of maximum jitter calibration steps of a phase-locked loop, wherein this phase-locked loop comprises phase detectors, a charge pump, a loop filter and a voltage controlled oscillator that is concatenated into a loop in regular turn, this method comprises:

(a) make this loop filter and charge pump and voltage controlled oscillator be temporary transient open-circuit condition;

(b) provide one first correction signal and one second correction signal to these phase detectors, carrying out phase-detection, and produce a rising pulse and a decline pulse, produce a net current to control this charge pump according to both phase difference;

(c) adjust the pulse duration of this rising pulse and this falling pulse according to this net current, reach a desired value up to this net current of this charge pump output; With

Wherein, in step (b), more this net current is carried out integration, to obtain a correction voltage, and in step (c), adjust the pulse expansion amplitude of this rising pulse and falling pulse, use the size and the polarity of this net current that changes this charge pump output according to this correction voltage, and when this net current reaches this desired value, keep the final extended amplitude of this rising pulse and this falling pulse.

2. the acceptable deviation of maximum jitter calibration steps of phase-locked loop as claimed in claim 1, in step (c), this desired value is meant this minimum net current.

3. the acceptable deviation of maximum jitter calibration steps of phase-locked loop as claimed in claim 1, in step (c), this desired value is meant that this minimum net current adds a side-play amount.

4. the acceptable deviation of maximum jitter calibration steps of phase-locked loop as claimed in claim 1, wherein the frequency of this first correction signal is the average frequency of an input signal of this phase-locked loop of input.

5. the acceptable deviation of maximum jitter calibration steps of phase-locked loop as claimed in claim 1, wherein the frequency of this second correction signal is the operating frequency of the clock signal of this phase-locked loop.

6. the acceptable deviation of maximum jitter calibrating installation of a phase-locked loop, wherein this phase-locked loop comprises phase detectors, a charge pump, a loop filter and a voltage controlled oscillator that is concatenated into a loop in regular turn, and when this device carried out calibration procedure, this loop filter system was temporary transient open-circuit condition with this charge pump and voltage controlled oscillator; This device comprises:

One signal generation unit in order to providing one first correction signal and one second correction signal to these phase detectors, carrying out phase-detection, and produces a rising pulse and a decline pulse according to both phase difference, produces a net current to control this charge pump;

One correcting unit, it adjusts the pulse duration of this rising pulse and this falling pulse according to above-mentioned net current, up to this net current of this charge pump output reach a desired value and

Wherein, this correcting unit comprises an integrator, one analog/digital converter, one decision circuit, an one rising pulse stretcher and a decline pulse stretcher, this integrator system carries out integration in order to this net current to this charge pump output, to obtain a correction voltage, this analog/digital converter system will export this decision circuit to after this correction voltage digitlization, this decision circuit system is just reaching according to the size of this digitized correction voltage, negative polarity is selected this rising pulse stretcher of control or this falling pulse expander, adjust the pulse expansion amplitude of this rising pulse and falling pulse with selectivity, this rising pulse stretcher system be connected these phase detectors and this charge pump between, so that the pulse duration adjustment is carried out in this rising pulse, and this falling pulse expander system be connected these phase detectors and this charge pump between, so that this falling pulse is carried out the pulse duration adjustment.

7. the acceptable deviation of maximum jitter calibrating installation of phase-locked loop as claimed in claim 6, wherein this signal generation unit comprises one in order to producing the pulse generator of this first correction signal, and a usefulness is so that this voltage controlled oscillator of this phase-locked loop produces the power supply of this second correction signal.

8. the acceptable deviation of maximum jitter calibrating installation of phase-locked loop as claimed in claim 6, wherein when this charge pump changed the size of this net current of output and polarity and makes this net current reach this desired value according to the pulse expansion amplitude of this rising pulse and this falling pulse, this rising pulse stretcher and falling pulse expander promptly kept the final extended amplitude of this rising pulse and falling pulse respectively.

9. the acceptable deviation of maximum jitter calibrating installation of phase-locked loop as claimed in claim 6, wherein this desired value is meant this minimum net current.

10. the acceptable deviation of maximum jitter calibrating installation of phase-locked loop as claimed in claim 6, wherein this desired value is meant that this minimum net current adds a side-play amount.

11. the acceptable deviation of maximum jitter calibrating installation of phase-locked loop as claimed in claim 6, wherein the frequency of this first correction signal is the average frequency of an input signal of this phase-locked loop of input.

12. the acceptable deviation of maximum jitter calibrating installation of phase-locked loop as claimed in claim 6, wherein the frequency of this second correction signal is the operating frequency of the clock signal of this phase-locked loop.

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