CN100403522C - Method for forming nonvolatile memory with embedded floating grid - Google Patents

Abstract

The invention discloses a method for forming a nonvolatile memory with a mosaic floating grid. Includes providing a substrate having a pad dielectric layer thereon and a first dielectric layer on the pad dielectric layer. Then, a buried diffusion region pattern is transferred into the first dielectric layer to expose the pad dielectric layer. A buried diffusion region is then formed in the substrate. Then, a second dielectric layer is formed on the substrate. Then etch back the second dielectric layer and the pad dielectric layer to expose the buried diffusion region and the first dielectric layer. The exposed buried diffusion region is then etched to form a trench. Shallow trench isolation is then formed in the trench. Then transferring a floating gate pattern to the first dielectric layer and the second dielectric layer, and removing the first dielectric layer to expose part of the pad dielectric layer. The exposed pad dielectric layer is then removed to expose the substrate. Then, a tunnel oxide layer is formed on the exposed part of the substrate. Then, a first conductor layer is formed on the tunnel oxide layer and the substrate. The first conductive layer is then planarized to expose the shallow trench isolation. Then, an inter-gate dielectric layer is formed on the first conductive layer and the shallow trench isolation. Finally, a second conductor layer is formed on the inter-gate dielectric layer.

Description

Method of forming nonvolatile memory with damascene floating gate

【Technical field】

The present invention relates to a method of forming a nonvolatile memory, in particular to a method of forming a nonvolatile memory with a mosaic floating gate.

【Background technique】

Non-volatile memory such as Electrical Erasable Programmable Read Only Memory (Electrical Erasable Programmable Read Only Memory) and flash memory can be electrically erased and rewritten. These devices can store data even after the power is cut off. Likewise, EPL ICs also utilize non-volatile memories to implement programmable logic functions. However, the lifespan of non-volatile memory and erasable programmable logic integrated circuits is limited by the stress associated with program data writing and erasing cycles. The lifetime of these components is the number of data write and erase cycles.

The important part of the non-volatile memory is the floating gate in the field effect transistor, and the floating gate is usually placed on a channel region connecting the source and the drain. A control gate is placed on the floating gate and isolated by a dielectric layer. Another type of control gate may consist of an adjacent diffusion region isolated from the floating gate. The floating gate is thus surrounded by an insulating dielectric material.

The threshold voltage is the minimum voltage applied to the control gate in order to turn on the transistor and make the source and drain conduct. The threshold voltage is a function of the amount of charge in the floating gate. The control gates serve as word lines to enable read and write operations for selected memory cells in a two-dimensional memory array.

Writing data into a memory cell requires maintaining the control gate and source and drain at an appropriate voltage to allow charge to travel from the substrate through the tunnel oxide to the floating gate. If enough electrons accumulate in the floating gate, the channel conductivity of the field effect transistor of the memory cell changes. By measuring the conductivity of the memory cell, it can be determined whether the stored data is "1" or "0". Since the floating gate is completely isolated, the memory cell is non-volatile and will hold charge indefinitely without applying any power.

The non-volatile memory unit also has erasable function. When erasing data, the control gate and the source and drain maintain an appropriate voltage to allow electrons to pass through the tunnel oxide layer to the substrate or the source region of the substrate. This operation reverses the effect of a write operation.

Reliability assurance is a costly, time-consuming, difficult but important task for the development and production of integrated circuits. This is especially true for non-volatile memory. In addition to the failure tests of common integrated circuit components such as packaging failure, electrostatic damage and oxide layer failure, non-volatile memory must also face more reliability requirements. For example, non-volatile memory must be able to effectively retain data for a long time and maintain normal operation during repeated write and erase operations.

Charge leakage in the floating gate of non-volatile memory is usually caused by positive ions in the oxide layer surrounding the floating gate. These positive ions tend to combine with electrons in the floating gate and cause charge loss in the floating gate and impair the data retention capability of the non-volatile memory.

Charge leakage in the floating gate of non-volatile memory is more often caused by damage to the tunnel oxide. The tunnel oxide layer may be damaged by subsequent manufacturing processes after the tunnel oxide layer is formed. Especially the etching manufacturing process, especially the etching manufacturing process of the floating gate, makes the tunnel oxide layer damaged and loses reliability. Therefore, damage to the tunnel oxide layer caused by the etching process of the floating gate may further cause charge loss during repeated write and erase operations, and thus must be resolved. In addition, when the thickness of the tunnel oxide layer is thinner, the above-mentioned problems will become more serious, and the failure of the tunnel oxide layer will result in poor data storage capability.

Therefore, it is very necessary to propose a novel method for forming a non-volatile memory, so that the above-mentioned problems caused by the traditional manufacturing process can be solved. This is the purpose proposed by the present invention.

【Content of invention】

An object of providing embodiments according to the present invention is to provide a method for forming a non-volatile memory having a damascene floating gate and a tunnel dielectric layer formed just before the formation of the damascene floating gate, so that the tunnel dielectric The electrical layer will not be damaged during the manufacturing process.

Another object of the embodiments according to the present invention is to provide a novel non-volatile memory structure, which can avoid any device failure caused by the floating gate etching process.

Another object of embodiments according to the present invention is to provide a method of forming a reliable non-volatile memory structure having a damascene floating gate and forming the floating gate without etching manufacturing process.

In order to achieve the above object, the present invention proposes a method for forming a nonvolatile memory with a damascene floating gate, the method at least includes the following steps. First, a substrate is provided, and the substrate has a pad dielectric layer thereon and a first dielectric layer on the pad dielectric layer. A buried diffusion pattern is then transferred into the first dielectric layer to expose the pad dielectric layer. A buried diffusion region is then formed in the substrate. Then a second dielectric layer is formed on the substrate. The second dielectric layer and the pad dielectric layer are then etched back to expose the buried diffusion region and the first dielectric layer. The exposed buried diffusion region is then etched to form a trench. A shallow trench is then formed to isolate the trench. A floating gate pattern is then transferred to the first dielectric layer and the second dielectric layer, and the first dielectric layer is removed to expose a portion of the pad dielectric layer. The exposed pad dielectric layer is then removed to expose the substrate. A tunnel oxide layer is then formed on the exposed portion of the substrate. Then a first conductor layer is formed on the tunnel oxide layer and the substrate. The first conductor layer is then planarized to expose the shallow trench isolation. Then an inter-gate dielectric layer is formed on the first conductor layer and the shallow trench isolation. Finally, a second conductor layer is formed on the inter-gate dielectric layer.

The foregoing brief description of the invention and the following detailed description are exemplary only and not limiting. Other equivalent changes or modifications that do not depart from the spirit of the present invention shall be included within the patent scope of the present invention.

【Description of drawings】

In order to make the above-mentioned other purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and is described in detail as follows in conjunction with the accompanying drawings:

Figure 1A shows a substrate with a pad dielectric layer and a dielectric layer thereon;

FIG. 1B shows the result that the dielectric layer is then etched to expose the pad dielectric layer and form buried diffusion regions in the substrate;

Figure 1C shows the result of forming a dielectric layer on the substrate followed by etching back to expose the buried diffusion region;

Figure 1D shows the result of etching the exposed buried diffusion region to form a trench;

FIG. 1E shows the result of filling the trench with an oxide layer to form a shallow trench isolation in the substrate and performing chemical mechanical polishing on the oxide layer of the shallow trench isolation to expose the dielectric layer;

FIG. 1F shows the result of etching the dielectric layer to form a floating gate pattern;

FIG. 1G shows the result of removing the dielectric layer and the pad dielectric layer to expose the substrate;

FIG. 1H shows the result of sequentially forming a tunnel dielectric layer and a conductor layer on the exposed substrate followed by planarization by chemical mechanical polishing to expose the dielectric layer and shallow trench isolation; and

FIG. 1I shows the result of sequentially forming an inter-gate dielectric layer and a conductive layer in the structure shown in FIG. 1H .

【Detailed ways】

It must be noted here that the manufacturing process steps and structures described below do not include a complete manufacturing process. The present invention can be implemented by various integrated circuit manufacturing process technologies, and only the manufacturing process technologies required for understanding the present invention are mentioned here.

Hereinafter, the present invention will be described in detail according to the accompanying drawings. Please note that the drawings are in simple form and not drawn to scale, and the dimensions are exaggerated to facilitate understanding of the present invention.

The method of forming a nonvolatile memory with a damascene floating gate according to the present invention is described in detail below. Referring to FIG. 1A , a substrate 100 having a pad dielectric layer 104 and a dielectric layer 106 thereon is shown. The substrate 100 includes a silicon substrate with a <100> lattice orientation, but is not limited to a silicon substrate. A pad dielectric layer 104 is first formed on the substrate 100 . The pad dielectric layer 104 can be formed by conventional oxidation methods. The dielectric layer 106 includes a silicon nitride layer deposited on the pad dielectric layer 104 . Referring to FIG. 1B , the display dielectric layer 106 is then etched by a photolithography and etching process to expose the pad dielectric layer 104 . Finally, the buried diffusion region 102 is formed in the substrate 100 by photolithography, etching, ion implantation and rapid thermal annealing (Rapid Thermal Processing) manufacturing processes.

Referring to FIG. 1C, a dielectric layer 110 comprising a silicon dioxide layer is shown formed on the structure shown in FIG. 1B, and then the dielectric layer 110 and the pad dielectric layer 104 are etched back by conventional etching methods to expose the buried diffusion. District 102. Referring to FIG. 1D , the exposed buried diffusion region 102 is shown etched to form a trench. Referring to FIG. 1E , it is shown that the trench is filled with an oxide layer to form a shallow trench isolation 112 in the substrate 100, and the shallow trench isolation oxide layer is planarized by chemical mechanical polishing to expose the dielectric layer 106 and the dielectric layer. Layer 110. The oxide layer includes a high density plasma oxide layer (High Density Plasma).

Referring to FIG. 1F , the display dielectric layers 106 and 110 are etched by photolithography and etching processes to form a floating gate pattern. The formation of the floating gate pattern is to first form a photoresist layer on the shallow trench isolation 112, the dielectric layer 106 and the dielectric layer 110, and then transfer the floating gate pattern to the photoresist layer through a photolithography manufacturing process, Then the shallow trench isolation 112, the dielectric layer 106 and the dielectric layer 110 are etched to form a floating gate pattern.

Referring to FIG. 1G , the result of removing the dielectric layer 106 and the pad dielectric layer 104 to expose the substrate 100 is shown. Referring next to FIG. 1H , it is shown that a tunnel dielectric layer 105 is formed on the exposed substrate 100 after removing the pad dielectric layer 104, and a conductor layer 116 comprising a polysilicon layer is then formed on the tunnel dielectric layer 105 and The result of planarization by chemical mechanical polishing to expose the dielectric layer 110 and the shallow trench isolation 112 .

Referring to FIG. 1I , there is shown the result of forming an inter-gate dielectric layer 118 on the structure shown in FIG. 1H and then forming a conductive layer 120 on the inter-gate dielectric layer 118 . The inter-gate dielectric layer 118 includes an oxide-nitride-oxide layer (Oxide-Nitride-Oxide). The conductive layer 120 includes a polysilicon layer.

The method for forming a nonvolatile memory with a mosaic floating gate provided by the present invention is to form a tunnel dielectric layer before forming a mosaic floating gate, so that the tunnel dielectric layer will not be damaged during the manufacturing process. Any component failures caused by the floating gate etch manufacturing process can be avoided.

The foregoing detailed description of the invention is exemplary only and not limiting. Other equivalent changes or modifications that do not depart from the spirit of the present invention shall be included within the patent scope of the present invention.

Claims (10)

1. a formation has the method for the nonvolatile memory of inlaid floated grating pole, and this method comprises the following step at least:

One substrate is provided, this substrate have one the pad dielectric layer thereon with one first dielectric layer on this pad dielectric layer;

Transfer one is buried the diffusion region pattern and is entered this first dielectric layer to expose this pad dielectric layer;

Form one and bury the diffusion region in this substrate;

Form one second dielectric layer on this substrate;

This second dielectric layer of etch-back and this pad dielectric layer bury diffusion region and this first dielectric layer to expose this;

This exposure of etching bury the diffusion region to form irrigation canals and ditches;

Form shallow trench isolation in these irrigation canals and ditches;

Shift a floating grid pattern to this first dielectric layer and this second dielectric layer;

Remove this first dielectric layer with this pad dielectric layer of expose portion;

The pad dielectric layer that removes this exposure is to expose this substrate;

Form the part that a tunnel oxidation layer exposes in this substrate;

Form one first conductor layer on this tunnel oxidation layer and this substrate;

This first conductor layer of planarization is to expose this shallow trench isolation;

Form between a lock dielectric layer on this first conductor layer and this shallow trench isolation; And

Form one second conductor layer on dielectric layer between this lock.

2. formation according to claim 1 has the method for the nonvolatile memory of inlaid floated grating pole, it is characterized in that, described first conductor layer comprises a polysilicon layer.

3. formation according to claim 1 has the method for the nonvolatile memory of inlaid floated grating pole, it is characterized in that, described first dielectric layer comprises a silicon nitride layer.

4. formation according to claim 1 has the method for the nonvolatile memory of inlaid floated grating pole, it is characterized in that, described second dielectric layer comprises a silicon dioxide layer.

5. formation according to claim 1 has the method for the nonvolatile memory of inlaid floated grating pole, it is characterized in that, the described diffusion fauna that buries injects and the formation of thermal annealing manufacturing process with ion.

6. formation according to claim 1 has the method for the nonvolatile memory of inlaid floated grating pole, it is characterized in that, described shallow trench isolation is to form in these irrigation canals and ditches by inserting a high-density plasma oxide layer.

7. formation according to claim 1 has the method for the nonvolatile memory of inlaid floated grating pole, it is characterized in that, the described first conductor series of strata are with the chemical mechanical milling method planarization.

8. formation according to claim 1 has the method for the nonvolatile memory of inlaid floated grating pole, it is characterized in that, described first conductor layer and this second conductor layer comprise a polysilicon layer respectively.

9. a formation has the method for the nonvolatile memory of inlaid floated grating pole, and this method comprises the following step at least:

One substrate is provided, this substrate have one the pad dielectric layer thereon with one first dielectric layer on this pad dielectric layer;

Transfer one is buried the diffusion region pattern and is entered this first dielectric layer to expose this pad dielectric layer;

Form one and bury the diffusion region in this substrate;

Form one second dielectric layer on this substrate;

This second dielectric layer of etch-back and this pad dielectric layer bury diffusion region and this first dielectric layer to expose this;

This exposure of etching bury the diffusion region to form irrigation canals and ditches;

Form the monoxide layer in these irrigation canals and ditches with this substrate on;

This oxide skin(coating) of planarization is to expose this first dielectric layer and this second dielectric layer;

Shift a floating grid pattern to this first dielectric layer and this second dielectric layer;

Remove this first dielectric layer with this pad dielectric layer of expose portion;

The pad dielectric layer that removes this exposure is to expose this substrate;

Form the part that a tunnel oxidation layer exposes in this substrate;

Form one first conductor layer on this tunnel oxidation layer and this substrate;

This first conductor layer of planarization is to expose this shallow trench isolation;

Form between a lock dielectric layer on this first conductor layer and this shallow trench isolation; And

Form one second conductor layer on dielectric layer between this lock.

10. a formation has the method for the nonvolatile memory of inlaid floated grating pole, and this method comprises the following step at least:

One silicon substrate is provided, this silicon substrate have one the pad dielectric layer thereon with one first dielectric layer on this pad dielectric layer;

Transfer one is buried the diffusion region pattern and is entered this first dielectric layer to expose this pad dielectric layer;

Form one with ion injection and rapid thermal annealing manufacturing process and bury the diffusion region in this silicon substrate;

Form one second dielectric layer on this silicon substrate;

This second dielectric layer of etch-back and this pad dielectric layer bury diffusion region and this first dielectric layer to expose this;

This exposure of etching bury the diffusion region to form irrigation canals and ditches;

Form the monoxide layer in these irrigation canals and ditches with this silicon substrate on;

This oxide skin(coating) of planarization is to expose this first dielectric layer and this second dielectric layer;

Shift a floating grid pattern to this first dielectric layer and this second dielectric layer;

Remove this first dielectric layer with this pad dielectric layer of expose portion;

The pad dielectric layer that removes this exposure is to expose this silicon substrate;

Form the part that a tunnel oxidation layer exposes in this silicon substrate;

Form one first conductor layer on this tunnel oxidation layer and this silicon substrate;

This first conductor layer of planarization is to expose this shallow trench isolation;

Form monoxide-nitride-oxide skin(coating) on this first conductor layer and this shallow trench isolation; And

Form one second conductor layer on this oxide-nitride-oxide layer.

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