CN100401466C - Thin film transistor array substrate and its metal layer manufacturing method - Google Patents

Abstract

A method for manufacturing a thin film transistor array substrate and its metal layer, comprising: first providing a substrate, and forming a patterned first metal layer on the substrate by electroplating; then forming a gate insulating layer on the substrate , and the gate insulating layer will cover the first metal layer; then a semiconductor layer is formed on the gate insulating layer above the first metal layer; and a patterned second metal layer is formed on the semiconductor layer. Wherein, the first metal layer, the second metal layer and the semiconductor layer form a plurality of thin film transistors on the substrate and a plurality of scanning wirings and a plurality of data wirings coupled to those thin film transistors.

Description

Thin film transistor array substrate and its metal layer manufacturing method

technical field

The present invention relates to a method for manufacturing a thin film transistor array (Thin Film Transistor Array, TFT Array) substrate and its metal layer, and in particular to a method for manufacturing a thin film transistor array substrate and its metal layer by plating .

current technology

The cathode ray tube (Cathode Ray Tube, CRT) has been monopolizing the display market in recent years because of its excellent display quality and economy. However, for an environment where individuals operate most terminal/display devices on a desk, or from the viewpoint of environmental protection and energy saving, there are still many problems in space utilization and energy consumption of cathode ray tubes. Therefore, thin film transistor liquid crystal displays (Thin Film Transistor Liquid Crystal Display, TFT LCD) with superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream of the market.

Conventional thin film transistor liquid crystal displays mostly use aluminum as the metal circuit material of the thin film transistor array substrate. However, under the current market trend of large-scale TFT-LCDs, it is necessary to increase the length of metal lines inside the TFT-LCDs. Along with this, the impedance of the metal circuit increases, which causes the signal delay in the TFT-LCD, which further causes problems such as poor display images of the TFT-LCD.

Contents of the invention

In view of this, the object of the present invention is to provide a method for manufacturing a thin film transistor array substrate by electroplating, so as to improve the signal delay phenomenon in large-scale thin film transistor liquid crystal displays.

Another object of the present invention is to provide a method for forming the metal layer in the thin film transistor array substrate by electroplating, so that the material of the metal layer in the thin film transistor array substrate has various selectivity.

Based on the above or other purposes, the present invention proposes a method for manufacturing a thin film transistor array substrate, the steps of which are as follows: firstly, a substrate is provided, and a patterned first metal layer is formed on the substrate by electroplating; A gate insulating layer is formed on the bottom, and the gate insulating layer will cover the first metal layer; then a semiconductor layer is formed on the gate insulating layer above the first metal layer; and a patterned second metal layer is formed on the semiconductor layer layer. Wherein, the first metal layer, the second metal layer and the semiconductor layer form a plurality of thin film transistors and a plurality of scanning wirings and a plurality of data wirings coupled to the thin film transistors on the substrate.

In a preferred embodiment of the present invention, the method for forming a patterned first metal layer on a substrate, for example, includes the following steps: first, using, for example, physical vapor deposition or chemical vapor deposition on the substrate to form a first A conductive material layer, and a patterning step is performed on the first conductive material layer to form a patterned first electroplating seed layer. The step of patterning the first conductive material layer is, for example, performing a photolithography process and an etching process on the first conductive material layer. Then, using the first electroplating seed layer as an electrode, the first metal layer is formed by electroplating.

In addition, after the patterned first electroplating seed layer is formed on the substrate, and before the first metal layer is formed by electroplating, an insulating material layer can be formed on the substrate comprehensively by using, for example, chemical vapor deposition. Then, the insulating material layer is patterned. The patterning step is, for example, first forming a photoresist layer on the insulating material layer, and then using the first electroplating seed layer as a mask to back-expose the photoresist layer from the other side of the substrate. Afterwards, the photoresist layer is developed, and the insulating material layer is etched using the photoresist layer as a mask, and then the photoresist layer is removed to expose the insulating material layer to the first electroplating seed layer.

In a preferred embodiment of the present invention, the method for forming the patterned first electroplating seed layer on the substrate, for example, includes the following steps: first, an insulating material layer is formed on the substrate by chemical vapor deposition; Forming a patterned photoresist layer on the material layer; then using the photoresist layer as a mask, after the steps of exposure and development, etching the insulating material layer, so that the insulating material layer exposes part of the substrate; and then using For example, a physical vapor deposition method is used to comprehensively form a first conductive material layer on the substrate; finally, the photoresist layer and the first conductive layer located on the photoresist layer are removed by using, for example, a photoresist stripping method (Lift Off). material layer to form the first electroplating seed layer.

In a preferred embodiment of the present invention, the method for forming the first metal layer on the substrate includes the following steps: first, a first electroplating layer is formed on the substrate comprehensively by using, for example, physical vapor deposition or chemical vapor deposition. seed layer. Then, using the first electroplating seed layer as an electrode, a first metal material layer is formed by electroplating. Afterwards, a mask layer is formed on the first metal material layer using, for example, a chemical vapor deposition method, and a photolithography process and an etching process are performed on the mask layer to pattern the mask layer. Finally, the first metal material layer and the first electroplating seed layer are etched by means of the mask layer to form the first metal layer. In addition, the material of the mask layer is, for example, silicon nitride or silicon oxide.

In a preferred embodiment of the present invention, the method for forming the semiconductor layer is, for example, first forming a channel layer on the gate insulating layer, and then forming an ohmic contact layer on the channel layer. In addition, the material of the first metal layer is, for example, copper.

In a preferred embodiment of the present invention, the method for forming a patterned second metal layer on the semiconductor layer includes: firstly forming a layer of second conductive material on the semiconductor layer by using, for example, physical vapor deposition or chemical vapor deposition layer, and then perform a photolithography process and an etching process on the second conductive material layer to pattern the second conductive material layer to form a second electroplating seed layer. Afterwards, the second metal layer is formed by electroplating with the second electroplating seed layer as an electrode. In one embodiment, the material of the second metal layer is copper, for example.

The present invention also proposes a method for forming a metal layer in a thin film transistor array substrate, which includes the following steps: firstly providing a substrate; then forming an electroplating seed layer on the substrate; then using the electroplating seed layer as an electrode, electroplating A metal layer is formed.

In a preferred embodiment of the present invention, the method for forming the electroplating seed layer on the substrate is, for example, firstly forming a conductive material layer on the substrate; then patterning the conductive material layer to form the electroplating seed layer. After the electroplating seed layer is formed on the substrate, and before the metal layer is formed by electroplating, for example, an insulating material layer is comprehensively formed on the substrate by physical vapor deposition or chemical vapor deposition, and the insulating material is patterned. layer so that the layer of insulating material exposes the plating seed layer.

In addition, the method for patterning the insulating material layer includes the following steps, for example: firstly forming a photoresist layer on the insulating material layer; then using the electroplating seed layer as a mask, backing the photoresist layer from the other side of the substrate exposure; then develop the photoresist layer; then use the photoresist layer as a mask to etch the insulating material layer and remove the photoresist layer.

In a preferred embodiment of the present invention, the method for forming an electroplating seed layer on a substrate includes: first forming an insulating material layer on the substrate by, for example, chemical vapor deposition; Resist layer; then use the photoresist layer as a mask to etch the insulating material layer, so that the insulating material layer exposes a part of the substrate; then use, for example, physical vapor deposition to comprehensively form the first conductive material on the substrate layer; and removing the photoresist layer and the first conductive material layer on the photoresist layer by using, for example, a photoresist stripping method to form a first electroplating seed layer.

In a preferred embodiment of the present invention, the electroplating seed layer is comprehensively formed on the substrate, and after the metal layer is formed by electroplating, photolithography and etching processes are further included on the metal layer and the electroplating seed layer. In addition, the method of forming the plating seed layer is, for example, physical vapor deposition or chemical vapor deposition.

In a preferred embodiment of the invention, the material of the metal layer is copper, for example.

Based on the above, the present invention applies the electroplating method to the process of the thin film transistor array substrate and its metal layer. Different from the conventional technology, the electroplating method is used to manufacture the thin film transistor array substrate, which increases the material selectivity of the metal layer in the thin film transistor array substrate. Therefore, when fabricating the thin film transistor array substrate, copper or other metal materials with low impedance can be selected to improve the electrical properties of the thin film transistors, scanning wiring and data wiring on the thin film transistor array substrate, thereby improving the large-scale The phenomenon of signal delay in the liquid crystal display, and improve the image quality of the liquid crystal display.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings.

Description of drawings

Fig. 1 shows a flow chart of forming a thin film transistor array substrate in a preferred embodiment of the present invention;

2A to 2H sequentially show a schematic view of a thin film transistor array substrate according to the first embodiment of the present invention;

3A to 3G sequentially show a schematic diagram of a thin film transistor array substrate according to the second embodiment of the present invention;

4A to 4G sequentially show a schematic diagram of a thin film transistor array substrate according to the third embodiment of the present invention;

5A to 5G respectively show a schematic diagram of a substrate for manufacturing a thin film transistor array according to the fourth embodiment of the present invention.

Implementation

FIG. 1 shows a flow chart of forming a thin film transistor array substrate in a preferred embodiment of the present invention. Please refer to FIG. 1 , the method for manufacturing a thin film transistor array substrate of the present invention mainly includes the following steps: firstly, a substrate is provided, such as step S100 , the substrate is, for example, a transparent substrate. And because the electroplating method needs to form an electrode on the object to be plated before electroplating, it is necessary to deposit a layer of metal on the substrate by physical vapor deposition (such as sputtering) or chemical vapor deposition to form an electroplating seed layer. , as in step S110. After that, the electroplating seed layer is used as an electrode, and the first metal layer is formed on the substrate by electroplating, as in step S120. Then, a gate insulating layer covering the first metal layer is formed on the substrate by chemical vapor deposition, as in step S130. Afterwards, a semiconductor layer is formed on the gate insulating layer above the first metal layer, as in step S140. Finally, a second metal layer is formed on the semiconductor layer, as in step S150.

In order to describe the features of the present invention in detail, the method for fabricating a thin film transistor array substrate of the present invention will be described in detail below with reference to multiple different embodiments.

first embodiment

2A to 2G sequentially show a schematic view of a substrate for manufacturing a thin film transistor array according to the first embodiment of the present invention. First, as shown in FIG. 2A , a substrate 100 is provided, such as a transparent substrate. Next, as shown in FIG. 2B, an electroplating seed layer 114 is formed on the substrate. Then, as shown in FIG. 2C , a photolithography process and an etching process are performed on the electroplating seed layer 114 to pattern the electroplating seed layer 114 . Afterwards, as shown in FIG. 2D , using the patterned electroplating seed layer 114 as an electrode, a patterned metal layer 110 is formed on the substrate 100 by electroplating. Wherein, the material of the metal layer 110 is copper, for example. Moreover, as shown in FIG. 2E, a gate insulating layer 120 is formed on the substrate 100 by chemical vapor deposition, for example, the material of the gate insulating layer 120 is silicon nitride (silicon nitride) or silicon oxide (silicon oxide), And the gate insulating layer 120 will cover the metal layer 110 . Then, as shown in FIG. 2F, a channel layer 132 is first formed on the gate insulating layer 120 above the patterned metal layer 110, and then an ohmic contact layer 134 is formed on the channel layer 132, wherein the channel layer 132 and the ohmic contact layer 134 A semiconductor layer 130 is formed. In addition, the material of the channel layer 132 is, for example, amorphous silicon, and the material of the ohmic contact layer 134 is, for example, n+ doped amorphous silicon. In another preferred embodiment of the present invention, the material of the channel layer 132 can also be, for example, polysilicon. Then, as shown in FIG. 2G , a patterned electroplating seed layer 142 is firstly formed on the semiconductor layer 130 . Then, as shown in FIG. 2H , a metal layer 140 is formed on the electroplating seed layer 142 by electroplating.

After the above manufacturing steps, the metal layers 110, 140 and semiconductor layer 130 formed on the substrate 100 can form a plurality of thin film transistors, a plurality of scanning wiring lines and a plurality of data wiring lines on the substrate 100, so as to form a thin film transistor Array substrate.

second embodiment

3A to 3G sequentially show a schematic diagram of a substrate for manufacturing a thin film transistor array according to the second embodiment of the present invention. First, as shown in FIG. 3A , a conductive material layer 112 is completely formed on the substrate 100 by using, for example, a physical deposition method or a chemical deposition method. Then, as shown in FIG. 3B , the conductive material layer 112 is subjected to a photolithography process and an etching process to pattern the conductive material layer 112 , and the patterned conductive material layer 112 is the electroplating seed layer 114 . Afterwards, a layer of insulating material 116 is deposited on the substrate 100 by chemical vapor deposition, such as silicon oxide or silicon nitride, and a photoresist layer 118 is coated on the insulating material layer 116, Then, using the electroplating seed layer 114 as a mask, the photoresist layer 118 is exposed from the other side of the substrate 100 . Then, as shown in FIG. 3C , the photoresist layer 118 is developed, and the insulating material layer 116 is etched using the photoresist layer 118 as a mask to expose the electroplating seed layer 114 . Afterwards, as shown in FIG. 3D , the photoresist layer 118 is removed, and metal is deposited on the electroplating seed layer 114 by electroplating to form the metal layer 110 .

It should be noted that the difference between this embodiment and the first embodiment is that after the electroplating seed layer 114 is formed, an insulating material layer 116 is first formed on the substrate 100 in this embodiment, and the insulating material layer 116 will cover the electroplating seed layer 114 . Afterwards, a photolithography process and an etching process are performed on the insulating material layer 116 to expose the electroplating seed layer 114 , and an electroplating method is used to form the metal layer 110 . In the first embodiment, the patterned conductive material layer 112 is directly used as the electroplating seed layer 114, and the metal layer 110 is formed on the electroplating seed layer 114 by electroplating, and no insulating material is deposited on the substrate 100. Layer 116.

Next, as shown in FIG. 3E , a gate insulating layer 120 is formed on the substrate 100 by chemical vapor deposition, for example, the material of the gate insulating layer 120 is silicon nitride or silicon oxide, and the gate insulating layer 120 will The metal layer 110 and the insulating material layer 116 cover it. Then, as shown in FIG. 3F, a channel layer 132 is first formed on the gate insulating layer 120 above the patterned metal layer 110, and then an ohmic contact layer 134 is formed on the channel layer 132, wherein the channel layer 132 and the ohmic contact layer 134 A semiconductor layer 130 is formed. In addition, the material of the channel layer 132 is, for example, amorphous silicon, and the material of the ohmic contact layer 134 is, for example, n+ doped amorphous silicon. In another preferred embodiment of the present invention, the material of the channel layer 132 can also be, for example, polysilicon. Afterwards, as shown in FIG. 3G , a patterned electroplating seed layer 142 is first formed on the semiconductor layer 130 , and then a patterned metal layer 140 is formed by electroplating with the electroplating seed layer 142 .

After the above manufacturing steps, the metal layers 110, 140 and semiconductor layer 130 formed on the substrate 100 can form a plurality of thin film transistors, a plurality of scanning wiring lines and a plurality of data wiring lines on the substrate 100, so as to form a thin film transistor Array substrate.

third embodiment

4A to 4G sequentially show a schematic view of a substrate for manufacturing a thin film transistor array according to a third embodiment of the present invention. First, as shown in FIG. 4A, an insulating material layer 116 is first formed on the substrate 100 by, for example, chemical vapor deposition, and then a photoresist layer 118 is first coated on the insulating material layer 116, and a photolithographic process and an etching process are used to form an insulating material layer 116. to pattern the photoresist layer 118 . Then, as shown in FIG. 4B , the insulating material layer 116 is etched using the photoresist layer 118 as a mask, and a part of the substrate 100 is exposed from the insulating material layer 116 . Afterwards, as shown in FIG. 4C , a conductive material layer 112 is formed on the substrate 100 using, for example, a physical vapor deposition method, and a photoresist layer 118 and above the photoresist layer 118 are formed using, for example, a photoresist lift-off method. The conductive material layer 112 is removed, and the unremoved conductive material layer 112 is the electroplating seed layer 114 . Then, as shown in FIG. 4D , the metal layer 110 is deposited on the electroplating seed layer 114 by electroplating.

Next, as shown in FIG. 4E, a gate insulating layer 120 is formed on the substrate 100 by chemical vapor deposition, for example, the material of the gate insulating layer 120 is silicon nitride or silicon oxide, and the gate insulating layer 120 will The metal layer 110 and the insulating material layer 116 cover it. Then, as shown in FIG. 4F, a channel layer 132 is first formed on the gate insulating layer 120 above the patterned metal layer 110, and then an ohmic contact layer 134 is formed on the channel layer 132, wherein the channel layer 132 and the ohmic contact layer 134 A semiconductor layer 130 is formed. In addition, the material of the channel layer 132 is, for example, amorphous silicon, and the material of the ohmic contact layer 134 is, for example, n+ doped amorphous silicon. In another preferred embodiment of the present invention, the material of the channel layer 132 can also be, for example, polysilicon. Afterwards, as shown in FIG. 4G , a patterned electroplating seed layer 142 is first formed on the semiconductor layer 130 , and then a patterned metal layer 140 is formed by electroplating with the electroplating seed layer 142 .

After the above manufacturing steps, the metal layers 110, 140 and semiconductor layer 130 formed on the substrate 100 can form a plurality of thin film transistors, a plurality of scanning wiring lines and a plurality of data wiring lines on the substrate 100, so as to form a thin film transistor Array substrate.

Fourth embodiment

5A to 5G respectively show a schematic diagram of a substrate for manufacturing a thin film transistor array according to the fourth embodiment of the present invention. First, as shown in FIG. 5A , an electroplating seed layer 114 is formed on the substrate 100 by physical vapor deposition or chemical vapor deposition, and the metal material layer 212 is formed by electroplating with the electroplating seed layer 114 as an electrode. Then, as shown in FIG. 5B, a mask layer 119 is formed on the metal material layer 212 by chemical deposition. The material of the mask layer 119 is, for example, silicon nitride or silicon oxide, and the mask layer 119 is photoetched. process and etching process to pattern the mask layer 119 . After that, as shown in FIG. 5C , the metal material layer 212 and the electroplating seed layer 114 are etched through the mask layer 119 , and the mask layer 119 is removed. Finally, as shown in FIG. 5D , the remaining metal material layer 212 and the plating seed layer 114 constitute the metal layer 110 .

Next, as shown in FIG. 5E, a gate insulating layer 120 is formed on the substrate 100 by chemical vapor deposition, for example, the material of the gate insulating layer 120 is silicon nitride or silicon oxide, and the gate insulating layer 120 will The metal layer 110 covers it. Then, as shown in FIG. 5F, a channel layer 132 is first formed on the gate insulating layer 120 above the patterned metal layer 110, and then an ohmic contact layer 134 is formed on the channel layer 132, wherein the channel layer 132 and the ohmic contact layer 134 A semiconductor layer 130 is formed. In addition, the material of the channel layer 132 is, for example, amorphous silicon, and the material of the ohmic contact layer 134 is, for example, n+ doped amorphous silicon. In another preferred embodiment of the present invention, the material of the channel layer 132 can also be, for example, polysilicon. Afterwards, as shown in FIG. 5G , a patterned electroplating seed layer 142 is first formed on the semiconductor layer 130 , and then a patterned metal layer 140 is formed by electroplating with the electroplating seed layer 142 .

After the above manufacturing steps, the metal layers 110, 140 and semiconductor layer 130 formed on the substrate 100 can form a plurality of thin film transistors, a plurality of scanning wiring lines and a plurality of data wiring lines on the substrate 100, so as to form a thin film transistor Array substrate.

To sum up, the present invention applies the electroplating method to the process of manufacturing the thin film transistor array substrate and its metal layer. In addition to the advantages of fast metal deposition and relatively low cost, the electroplating method is different from the conventional technology in that the electroplating method is used to make the thin film transistor array substrate, which increases the material selection of the metal layer in the thin film transistor array substrate. sex. Therefore, when fabricating the thin film transistor array substrate, copper or other metal materials with low impedance can be selected to improve the electrical properties of the thin film transistors, scanning wiring and data wiring in the thin film transistor array substrate, thereby improving the performance of large-size liquid crystals. The phenomenon of signal delay in the display, and improve its image quality.

Although the present invention has been disclosed as described above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art should be able to make various changes and modifications without departing from the spirit and scope of the present invention , so the protection scope of the present invention shall prevail as defined by the appended claims.

Claims (25)

1. A method for manufacturing a thin film transistor array substrate, comprising: provide a substrate; forming a patterned first electroplating seed layer on the substrate; forming a layer of insulating material on the substrate to cover the first electroplating seed layer; forming a photoresist layer on the insulating material layer; Using the first electroplating seed layer as a mask, back-exposing the photoresist layer from the other side of the substrate; developing the photoresist layer; Using the photoresist layer as a mask, etching the insulating material layer to expose the patterned first electroplating seed layer; forming a patterned first metal layer on the substrate by electroplating; removing the photoresist layer; forming a gate insulating layer on the substrate, and the gate insulating layer covers the first metal layer; forming a semiconductor layer on the gate insulating layer above the first metal layer; and A patterned second metal layer is formed on the semiconductor layer, wherein the first metal layer, the second metal layer and the semiconductor layer form a plurality of thin film transistors on the substrate and electrodes coupled to the thin film transistors Multiple scan wires and multiple data wires. 2. The manufacturing method of the thin film transistor array substrate as claimed in claim 1, wherein the method for forming the patterned first metal layer on the substrate comprises: The first metal layer is formed by electroplating with the first electroplating seed layer as an electrode. 3. The manufacturing method of the thin film transistor array substrate as claimed in claim 1, wherein the method for forming the patterned first electroplating seed layer on the substrate comprises: forming a first conductive material layer on the substrate; and The first conductive material layer is patterned to form the first electroplating seed layer. 4. The manufacturing method of the thin film transistor array substrate as claimed in claim 3, wherein the method of forming the first conductive material layer on the substrate comprises a physical vapor deposition method or a chemical vapor deposition method. 5. The manufacturing method of the thin film transistor array substrate as claimed in claim 1, wherein the method of forming the insulating material layer on the substrate completely comprises a chemical vapor deposition method. 6. The manufacturing method of the thin film transistor array substrate as claimed in claim 1, wherein the method for forming the patterned first electroplating seed layer on the substrate comprises: forming a layer of insulating material on the substrate; forming a patterned photoresist layer on the insulating material layer; using the photoresist layer as a mask, etching the insulating material layer, so that the insulating material layer exposes part of the substrate; forming a first conductive material layer over the substrate; and The photoresist layer and the first conductive material layer on the photoresist layer are removed to form the first electroplating seed layer. 7. The manufacturing method of the thin film transistor array substrate as claimed in claim 6, wherein the method of forming the insulating material layer on the substrate comprises a chemical vapor deposition method. 8. The manufacturing method of the thin film transistor array substrate as claimed in claim 6, wherein the method of forming the first conductive material layer on the substrate comprehensively comprises a physical vapor deposition method. 9. The manufacturing method of the TFT array substrate as claimed in claim 6, wherein the method for removing the photoresist layer and the first conductive material layer on the photoresist layer comprises a photoresist stripping method. 10. The manufacturing method of the thin film transistor array substrate as claimed in claim 1, wherein the method for forming the patterned second metal layer on the semiconductor layer comprises: forming a patterned second electroplating seed layer on the semiconductor layer; and The second metal layer is formed by electroplating with the second electroplating seed layer as an electrode. 11. The manufacturing method of thin film transistor array substrate as claimed in claim 10, wherein the method for forming the patterned second electroplating seed layer on the semiconductor layer comprises: forming a second conductive material layer on the semiconductor layer; and The second conductive material layer is patterned to form the second electroplating seed layer. 12. The method for fabricating a TFT array substrate as claimed in claim 11, wherein the method of forming the second conductive material layer on the semiconductor layer comprises physical vapor deposition or chemical vapor deposition. 13. The method for fabricating a thin film transistor array substrate as claimed in claim 10, wherein the material of the second metal layer comprises copper. 14. The manufacturing method of the thin film transistor array substrate as claimed in claim 1, wherein the method for forming the semiconductor layer comprises: form a channel layer; and An ohmic contact layer is formed on the channel layer. 15. The method for fabricating a thin film transistor array substrate as claimed in claim 1, wherein the material of the first metal layer comprises copper. 16. A method of forming a metal layer within a thin film transistor array substrate, comprising: provide a substrate; forming a patterned first electroplating seed layer on the substrate; forming a layer of insulating material on the substrate to cover the first electroplating seed layer; forming a photoresist layer on the insulating material layer; Using the first electroplating seed layer as a mask, back-exposing the photoresist layer from the other side of the substrate; developing the photoresist layer; Using the photoresist layer as a mask, etching the insulating material layer to expose the patterned first electroplating seed layer; Using the electroplating seed layer as an electrode, electroplating to form a metal layer; and The photoresist layer is removed. 17. The method for forming the metal layer in the thin film transistor array substrate as claimed in claim 16, wherein the method for forming the electroplating seed layer on the substrate comprises: forming a layer of conductive material on the substrate; and The conductive material layer is patterned to form the electroplating seed layer. 18. The method for forming a metal layer in a TFT array substrate as claimed in claim 17, wherein the method for forming the conductive material layer on the substrate comprises physical vapor deposition or chemical vapor deposition. 19. The method for forming the metal layer in the thin film transistor array substrate as claimed in claim 16, the method for forming the electroplating seed layer on the substrate comprises: forming a layer of insulating material on the substrate; forming a patterned photoresist layer on the insulating material layer; using the photoresist layer as a mask, etching the insulating material layer, so that the insulating material layer exposes part of the substrate; forming a first conductive material layer over the substrate; and The photoresist layer and the first conductive material layer on the photoresist layer are removed to form the first electroplating seed layer. 20. The method for fabricating a TFT array substrate as claimed in claim 19, wherein the method for forming the insulating material layer on the substrate comprises chemical vapor deposition. 21. The method for fabricating a thin film transistor array substrate as claimed in claim 19, wherein the method for forming the first conductive material layer comprises a physical vapor deposition method. 22. The manufacturing method of the TFT array substrate as claimed in claim 19, wherein the method for removing the photoresist layer and the first conductive material layer on the photoresist layer comprises a photoresist stripping method. 23. The method for forming a metal layer in a thin film transistor array substrate as claimed in claim 16, forming the electroplating seed layer comprehensively on the substrate, and after forming the metal layer by electroplating, further comprising The layer and the electroplating seed layer are subjected to a photolithography process and an etching process. 24. The method for forming a metal layer in a TFT array substrate as claimed in claim 23, wherein the method for forming the plating seed layer comprises physical vapor deposition or chemical vapor deposition. 25. The method of forming a metal layer in a thin film transistor array substrate as claimed in claim 16, wherein a material of the metal layer comprises copper.

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