CN100401361C - Clock signal amplifying method and driving unit of liquid crystal display driving circuit - Google Patents

Abstract

A clock signal amplifying method and a driving unit of a liquid crystal display driving circuit are provided, the driving unit includes a clock input terminal, a level shifter and an output buffer. First, the clock input terminal receives a clock signal oscillating between a high original potential and a low original potential. Then, the level shifter amplifies the pulse signal into a relay signal with the high target potential and the low target potential as the operation potential, and the relay signal oscillates between the high relay potential and the low relay potential. Finally, the output buffer amplifies the relay signal into a target signal by taking the high target potential and the low target potential as operation potentials, and the target signal oscillates between the high target potential and the low target potential.

Description

Clock signal amplification method and drive unit of liquid crystal display drive circuit

technical field

The present invention relates to a clock signal amplifying method and a driving unit device of a liquid crystal display driving circuit, and in particular to a clock signal amplifying method and a driving unit of a liquid crystal display driving circuit capable of maintaining a stable state with low energy consumption .

Background technique

In order to match the modern life style, the design of video or image devices is moving towards the trend of light, thin and small. Although the traditional cathode ray display (CRT) has its unique advantages, due to the structure of the internal electron gun, the volume of the cathode ray display is too large in the current view, and the space requirement is also high. In addition, the radiation generated Therefore, flat panel displays developed in conjunction with optoelectronic technology and semiconductor manufacturing technology, such as liquid crystal displays (Liquid Crystal Display, LCD), organic light-emitting displays (OLED) or plasma displays (Plasma Display Panel) , PDP), has gradually become the mainstream of display products.

Among them, the picture displayed by the liquid crystal display is composed of many pixels (Pixel) arranged in an array, and the brightness displayed by each pixel is determined by the brightness of the backlight module and the gray scale (Gray Scale) controlled by the pixel. decided together. Nowadays, in the driving method of liquid crystal display, the most commonly used method is to maintain the brightness of the backlight module at a fixed brightness, and drive the liquid crystal in each pixel to rotate with different bias voltages according to the input image information. And the light transmittance of the pixel is determined by the rotation angle of the liquid crystal, so as to achieve the purpose of grayscale display.

A thin film transistor (Thin Film Transistor, TFT) is an element widely used in turning on or blocking a pixel of a liquid crystal display. The driving circuit composed of it sequentially receives an image data (Image Data), and within a horizontal period (Horizontal Period), holds (Hold) the sampled image data corresponding to each pixel electrode of the liquid crystal display. Next, the driving circuit outputs all image signals at a time at the beginning or midway of the next horizontal period. The driving circuit continuously outputs the voltage of the image signal (Image Signal) within a time interval, and this time interval is called an output cycle. Generally speaking, the time length of this output period is about the same as the time length of a horizontal period.

Please refer to the circuit block diagram of the driving unit of the known liquid crystal display driving circuit shown in Figure 1, each driving unit includes a shift register (Shift Register) 105, a potential shifter (Level Shifter) ) 110, and an output buffer (OutputBuffer) 115. Wherein, the level shifter 110 is electrically connected between the shift register 105 and the output buffer 115 . The swing range of the clock signal input to the shift register 105 is between VDD and GND. Since the shift register 105 uses VDD and GND as operating potentials, the level shifter 110 and the output buffer 115 use VDD and VSS as operating potentials, wherein VSS is a potential less than zero. This known drive unit is rather energy-intensive.

Please refer to the circuit block diagram of the driving unit of another known liquid crystal display driving circuit shown in FIG. 2A, the driving unit includes a first potentiometer 203, a shift register 206, a second potentiometer 209, and an output buffer 212. Wherein, the shift register 206 is electrically connected between the first potentiometer 203 and the second potentiometer 209 , and the output buffer 212 is electrically connected to the second potentiometer 209 . The swing range of the clock signal input into the first potentiometer 203 is within a small range, for example, between 5V and GND. Please refer to FIG. 2B , which shows a schematic diagram of potential displacement of a driving unit of a known liquid crystal display driving circuit. In this known technology, the first potential shifter 203 and the shift register 206 use VDD and GND as The operating potential is a first potential shift circuit, which is used to shift the potential of 3V to the required VDD. The second potential shifter 209 and the output buffer 212 use VDD and VSS as operating potentials, and are a second potential shifting circuit for shifting the potential of GND to VSS. From the formula of dynamic power consumption: P=fcV 2, it can be known that the energy is proportional to the square of the voltage, where P represents the power consumed, f represents the operating frequency, c represents the load capacitance, and V represents the signal amplitude. Therefore, this known circuit consumes less energy than the above-mentioned known technique.

Contents of the invention

One of the objectives of the present invention is to provide a driving unit and a driving method of a display driving circuit of a flat panel display that can save power consumption. The driving unit and the driving method can save more energy than the known technology.

The present invention proposes a clock signal amplification method for a liquid crystal display drive circuit, which is suitable for amplifying a clock signal periodically oscillating between a high original potential and a low original potential to be between a high target potential and a low target potential An oscillating target signal, and the high target potential is higher than the high original potential, and the low target potential is lower than the low original potential, characterized in that the clock signal amplification method of the liquid crystal display drive circuit includes:

amplifying the clock signal into a relay signal oscillating between a high relay potential and a low relay potential; and

amplifying the relay signal into the target signal;

Wherein, the high relay potential is between the high original potential and the high target potential, and the low relay potential is between the low original potential and the low target potential.

It also includes: receiving the clock signal only within a predetermined period.

The present invention proposes a driving unit of a liquid crystal display driving circuit. The driving unit forms a part of the liquid crystal display driving circuit in a plurality of series connections. It is characterized in that the driving unit of the liquid crystal display driving circuit includes:

a clock input terminal for receiving a clock signal with a high original potential and a low original potential;

A level shifter, electrically coupled to the clock input terminal, receives the clock signal from the clock input terminal, and uses a high target potential and a low target potential as operating potentials to amplify the clock signal is a relay signal having a high relay potential and a low relay potential; and

An output buffer, electrically coupled to the level shifter, receives the relay signal from the level shifter, and uses the high target potential and the low target potential as operating potentials to amplify the relay signal to a target signal having the high target potential and the low target potential;

Wherein, the high relay potential is between the high original potential and the high target potential, and the low relay potential is between the low original potential and the low target potential.

Wherein the output buffer includes an odd number of inverters.

Wherein the output buffer is composed of CMOS.

Wherein the potential shifter includes an inverter composed of complementary metal oxide semiconductors.

Wherein the inverter in the potential shifter includes a metal oxide semiconductor connected to its own source/drain and gate.

It also includes a dynamic register, which is electrically coupled between the clock input terminal and the level shifter, and determines whether to connect the clock input terminal to the level shifter according to a control signal group. Electrical channel of potentiometer.

Wherein the dynamic register includes:

a register output terminal electrically coupled to the potentiometer;

A first control signal input circuit receives a previous driving signal output by the previous driving unit of the driving unit, and determines whether to conduct the electrical connection between the clock input terminal and the temporary storage according to the previous driving signal. the electrical path between the output terminals of the device; and

A second control signal input circuit, which receives a subsequent driving signal output by the subsequent driving unit of the driving unit, and determines whether to conduct the register output terminal and the low target potential according to the subsequent driving signal electrical channels between them.

Wherein the dynamic register includes:

a register output terminal electrically coupled to the potentiometer;

A first control signal input circuit receives a previous drive signal output by the previous drive unit of the drive unit, and determines whether to conduct the clock input terminal and the temporary register output according to the previous drive signal electrical pathways between terminals; and

a second control signal input circuit, which receives the previous driving signal and the output of the level shifter, and determines whether to conduct the electrical channel between the driving unit and the low target potential;

Wherein, the output of the potentiometer is opposite to the target signal output by the driving unit.

It also includes:

A potential clamper, electrically coupled between the high target potential and the output terminal of the register, and determines whether to conduct the electrical connection between the output terminal of the register and the high target potential according to the previous driving signal aisle.

Wherein the potential clamper includes a P-type metal oxide semiconductor.

Since the prior art needs to use 2 potentiometers and 3 voltage sources, including GND, VDD and VSS, it is more complicated and consumes more energy. Therefore, in the clock signal amplifying method and the driving unit of the liquid crystal display driving circuit proposed in the present invention, since the driving unit only includes a potential shifter and only uses two voltage sources VDD and VSS, and because complementary metal Oxide semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) structure is realized, that is, N-channel metal-oxide conductors and P-channel metal oxide conductors act in a complementary manner in the circuit, so N-channel and P-channel metal oxide conductors can be used The conduction status is different, so that there is only a leakage current between the voltage source and the ground at any time, so that the energy consumption is quite low, which is approximately equal to the product of the voltage source and the ground leakage current. Therefore, the present invention is simpler and consumes less energy than the known techniques.

Description of drawings

In order to make the above and other purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, together with the accompanying drawings, and described in detail as follows, wherein:

FIG. 1 is a circuit block diagram illustrating a driving unit of a known liquid crystal display driving circuit.

FIG. 2A is a circuit block diagram of a driving unit of a known liquid crystal display driving circuit.

FIG. 2B is a schematic diagram illustrating potential shifts of a driving unit of a known liquid crystal display driving circuit.

FIG. 3 is a diagram illustrating the implementation steps of a method for amplifying a clock signal of a liquid crystal display driving circuit according to a preferred embodiment of the present invention.

FIG. 4 is a circuit block diagram illustrating a driving unit of a liquid crystal display driving circuit according to a first preferred embodiment of the present invention.

5A is a circuit block diagram illustrating a driving unit of a liquid crystal display driving circuit according to a second preferred embodiment of the present invention.

FIG. 5B is a schematic diagram illustrating the potential shift of the driving unit of the liquid crystal display driving circuit according to the second preferred embodiment of the present invention.

FIG. 6A is a circuit block diagram of the first preferred embodiment of the dynamic register according to the present invention.

FIG. 6B is a diagram illustrating the implementation of components of the first preferred embodiment of the dynamic register according to the present invention.

FIG. 6C is a diagram illustrating the realization of components of the potentiometer applicable to the first preferred embodiment of the dynamic register.

FIG. 6D is an implementation diagram of the components of the potentiometer applicable to the first preferred embodiment of the dynamic register.

FIG. 7A is a circuit block diagram illustrating a second preferred embodiment of the dynamic register according to the present invention.

FIG. 7B is a diagram illustrating the realization of components of the second preferred embodiment of the dynamic register according to the present invention.

FIG. 7C is an implementation diagram of the components of the potentiometer applicable to the second preferred embodiment of the dynamic register.

Detailed ways:

For thin film liquid crystal display (TFT-LCD), the function of the gate driver (Gate Driver) included is to continuously provide pulsed signal (Pulsed Signal) to each horizontal scan line (Horizontal Scan Line) electrical connection the gate terminal. The gate terminal is a terminal responsible for controlling a thin film transistor switch of a certain pixel in the active matrix. The pulse signal usually swings between the negative potential VSS and the positive potential VDD, usually between 5V and 9V. The driving unit of the driving circuit of the present invention is used to amplify a low-voltage clock signal CLKin into a pulse wave signal. The low voltage is usually 3V, and the clock signal CLKin is periodic between 3V and 0V. Signal.

Please refer to FIG. 3 , which is a diagram illustrating the implementation steps of the method for amplifying the clock signal CLKin of the liquid crystal display driving circuit according to a preferred embodiment of the present invention. This embodiment is used to amplify the clock signal CLKin originally oscillating between a high original potential (for example, 3V) and a low original potential (for example, 0V) to oscillate between a high target potential (for example, 9V) and a low target potential ( For example, the target signal between -5V). Firstly, the clock signal CLKin is amplified into a relay signal oscillating between a high relay potential and a low relay potential (such as step S303 ). Next, the relay signal is amplified into the target signal again (such as step S306). Wherein, the size of the high relay potential is between the high original potential (for example, 3V) and the high target potential (for example, 9V), and the size of the low relay potential is between the low original potential (for example, 0V) and between low target potentials (eg -5V). In an embodiment of the present invention, the clock signal CLKin may be received within a specific period.

Please refer to FIG. 4 , which shows a circuit block diagram of a driving unit of a liquid crystal display driving circuit according to a first preferred embodiment of the present invention. In this embodiment, the driving unit of the liquid crystal display driving circuit includes a clock input terminal 403 , a potentiometer 406 and an output buffer 409 . Wherein, the clock input terminal 403 is responsible for receiving the clock signal CLKin oscillating between a high original potential (for example, 3V) and a low original potential (for example, 0V). The level shifter 406 is electrically connected to the clock input terminal 403, receives the clock signal CLKin from the clock input terminal 403, and uses a high target potential (for example, 9V) and a low target potential (for example, -5V) for operation. potential, thereby amplifying the clock signal CLKin into a relay signal oscillating between the high relay potential and the low relay potential. The output buffer 409 is electrically connected to the level shifter 406, receives the relay signal from the level shifter 406, and uses the high target potential and the low target potential as operating potentials to amplify the relay signal to be at the high target potential The target signal oscillates between low and low target potentials. Wherein, the above-mentioned potentials are arranged from high to low, and the order is high target potential, high relay potential, high original potential, low original potential, low intermediate potential, and finally low target potential. Wherein, the high target potential can be 9V, the high original potential can be 3V; the low target potential can be 5V, and the low original potential can be 0V.

Next, please refer to FIG. 5A , which shows a circuit block diagram of a driving unit of a liquid crystal display driving circuit according to a second preferred embodiment of the present invention. In this embodiment, the driving unit of the liquid crystal display driving circuit is compared with the embodiment shown in FIG. Between the potentiometer 509 , it is used to determine whether to conduct between the clock input terminal 503 and the potentiometer 509 according to a control signal group 515 . Please refer to FIG. 5B , which is a schematic diagram of potential displacement of the driving unit of the liquid crystal display driving circuit according to the second preferred embodiment of the present invention. It can be seen from P=fcV2 that the energy is proportional to the square of the voltage, that is to say, when the potential becomes twice the original one, the energy consumed can ideally be reduced to one quarter of the original one, so this implementation For example, less power is consumed than known drive units.

Please refer to FIG. 6A , which shows a circuit block diagram of the first preferred embodiment of the dynamic register according to the present invention. The dynamic register 506 includes a register output terminal 606 , a first control signal input circuit 603 and a second control signal input circuit 609 . Wherein, the register output terminal 606 is electrically connected to the level shifter 509 . The first control signal input circuit 603 is used to receive the front-stage drive signal (N-1)th output by the previous-stage drive unit of the drive unit, and determine whether to Connect the clock input terminal 503 to the register output terminal 606 . In addition, the second control signal input circuit 609 is used to receive the rear-stage driving signal (N+1)th output by the subsequent-stage driving unit of the driving unit, and according to the rear-stage driving signal (N+1)th to Determine whether to conduct the register output terminal 606 with the low target potential (eg -5V).

Please refer to FIG. 6B , which shows an implementation diagram of components of the first preferred embodiment of the dynamic register according to the present invention. Wherein, the transistors Q1 and Q2 form a dual-gate configuration (Dual-Gate Configuration), and its function is similar to an input switch device. When the double-gate structure is turned on, it is used to receive the previous driving signal (N-1)th to charge the terminal 612 to a positive potential, and make its potential higher than the clock input terminal, showing a high potential state. When the double gate structure cuts off the current, the terminal 612 maintains a high potential state. It can be seen from the figure that the transistors Q6, Q7 and Q8 are connected in series to form a triple-gate configuration (Triple-Gate Configuration). A discharge effect is generated, and finally the potential of the terminal 621 reaches a negative potential. The reason for using the multi-gate configuration (Multi-Gate Configuration) here is to reduce the leakage current when the signal at the terminal 612 is in the holding time. The detailed operation details of the signal are described as follows:

1. When the terminal 612 is in the charging time (Charging Time), the potential of the complement signal (N-1)th* of the front-stage driving signal (N-1)th is -5V, and the transistor Q4 is cut off, and at this time the front-stage The potential of the drive signal (N-1)th is 9V to turn on the transistor Q5. Therefore, the terminal 618, which is the output terminal of the dynamic register and connected to the input terminal of the potentiometer, is maintained at -5V.

2. When the terminal 612 is at the sustaining time, the potential of the front-stage drive signal (N-1)th is -5V and the transistor Q5 can be cut off. At this time, the complement signal (N-1)th of the front-stage drive signal (N-1)th -1) The potential of th* is 9V to turn on the transistor Q4 , so that the clock signal CLKin oscillating between 0V and 3V is coupled to the terminal 618 . In other words, the terminal 618 is turned on at the same time when the transistors Q3 and Q4 are turned on, receives the clock signal CLKin, and outputs it to the level shifter.

3. When the terminal 612 is in the discharge time (Discharging Time), the potential of the subsequent driving signal (N+1)th is 9V, which turns on the transistors Q6, Q7, Q8 and Q9. When the terminal 612 is discharged to -5V, the transistor Q3 will be cut off. At this time, the dynamic register has a very large input impedance to the clock signal CLKin. At this time, the potential of the terminal 618 is -5V, and remains at this potential until the next trigger pulse signal arrives.

Please refer to FIG. 6C and FIG. 6D , which are diagrams illustrating the implementation diagrams of components of two different level shifters applicable to the first preferred embodiment of the dynamic register. Those skilled in the art will know that the potentiometer includes an inverter composed of CMOS. It further includes a metal oxide semiconductor connecting its own source and gate or drain and gate.

Please refer to the circuit block diagram of the second preferred embodiment of the dynamic register according to the present invention shown in FIG. 7A . The dynamic register includes a register output terminal 706 , a first control signal input circuit 703 and a second control signal input circuit 712 , but the actions performed by the second control signal input circuit are slightly different. In this embodiment, the second control signal input circuit 712 is used to receive the driving signal (N-1)th of the previous stage and the output signal 709 of the level shifter of this stage, and decide whether to drive the unit according to the result Conduction with a low target potential (eg -5V). Wherein, the output signal 709 of the level shifter and the target signal output by the driving unit are opposite phases of each other.

Please refer to FIG. 7B , which shows an implementation diagram of components of the second preferred embodiment of the dynamic register according to the present invention. During the charging process, the dynamic register is similar to the dynamic register in the first preferred embodiment. When the terminal 714 is in a high potential state, the transistors Q3 and Q4 are turned on, and the transistor Q5 is cut off, and a set of complementary clock signals CLKin are sent to the level shifter through the transistors Q3 and Q4 . In this embodiment, the level shifter 509 is composed of two inverting circuits connected in parallel, and its output signal 709 is a pulse signal amplified by the complement signal CLKin* of the clock signal CLKin in one time period . The pulse signal oscillates between a high relay potential and a low relay potential. The high relay potential is between 3V and 9V, and the low relay potential is between GND and -5V.

Please refer to FIG. 7C , which is an implementation diagram of components applicable to the potentiometer of the second preferred embodiment of the dynamic register. The potentiometer can be divided into two stages, which are the first stage composed of transistors Q11, Q12, Q13, and Q14, and the second stage composed of transistors Q15, Q16, Q17, and Q18. The first stage is connected to the transistor Q3 for receiving the clock signal CLKin, and the second stage is connected to the transistor Q4 for receiving the complement signal CLKin* of the clock signal CLKin.

The output terminals of the dynamic register 506 and the level shifter 509 also include a feedback wiring. The completion of the feedback wiring enables the dynamic register to have a self-discharging function (Self Discharging Function). When the front-stage driving signal (N−1)th is transmitted to the common terminal 716 of the discharge transistors Q6 , Q7 and Q8 , the feedback signal is transmitted to the transistor Q9 . Under normal conditions, when the potential of the front stage driving signal (N-1)th is -5V, the transistors Q3, Q4 and Q10 are cut off, and the transistors Q5 and Q9 are turned on. When the potential of the terminal 722 is 9V, then The feedback signal will pass through the transistor Q9 and the common terminal 716, and turn on the transistors Q6, Q7, and Q8, and the potential of the terminal 714 and the terminal 718 will be maintained at -5V. This feedback wiring can maintain the drive unit in a steady state. teach.

In another preferred embodiment, the driving unit of the liquid crystal display driving circuit further includes a potential clamper, such as the transistor Q5 shown in FIG. 7B, and the potential clamper is electrically connected to a high target potential (such as 9V) and the output terminal of the register, it will be determined whether to conduct the output terminal of the register with a high target potential (for example, 9V) according to the driving signal (N-1)th of the previous stage. The potential clamper can be realized by PMOS.

In the first and second preferred embodiments of the driving unit of the liquid crystal display driving circuit, only one potential shifter and two voltage sources VDD and VSS are used, which is different from the need to use two potential shifters in the known technology. Compared with the drive unit of GND, VDD and VSS, the drive unit in the embodiment consumes less energy. In the second preferred embodiment of the dynamic register, the driving unit can maintain a steady-state feedback due to the feedback wiring.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention shall be as defined by the scope of the appended patent application.

Claims (12)

1. A method for amplifying a clock signal of a liquid crystal display driving circuit, which is suitable for amplifying a clock signal that periodically oscillates between a high original potential and a low original potential to oscillate between a high target potential and a low target potential A target signal, and the high target potential is higher than the high original potential, and the low target potential is lower than the low original potential. It is characterized in that the clock signal amplification method of the liquid crystal display drive circuit includes: amplifying the clock signal into a relay signal oscillating between a high relay potential and a low relay potential; and amplifying the relay signal into the target signal; Wherein, the high relay potential is between the high original potential and the high target potential, and the low relay potential is between the low original potential and the low target potential. 2. The clock signal amplifying method of liquid crystal display drive circuit as claimed in claim 1, is characterized in that, wherein also comprises: The clock signal is only received within a predetermined period. 3. A driving unit of a liquid crystal display driving circuit, the driving unit forms a part of the liquid crystal display driving circuit in a plurality of series connection, it is characterized in that, the driving unit of the liquid crystal display driving circuit comprises: a clock input terminal for receiving a clock signal with a high original potential and a low original potential; A level shifter, electrically coupled to the clock input terminal, receives the clock signal from the clock input terminal, and uses a high target potential and a low target potential as operating potentials to amplify the clock signal is a relay signal having a high relay potential and a low relay potential; and An output buffer, electrically coupled to the level shifter, receives the relay signal from the level shifter, and uses the high target potential and the low target potential as operating potentials to amplify the relay signal to a target signal having the high target potential and the low target potential; Wherein, the high relay potential is between the high original potential and the high target potential, and the low relay potential is between the low original potential and the low target potential. 4. The driving unit of the liquid crystal display driving circuit as claimed in claim 3, wherein the output buffer comprises an odd number of inverters. 5. The driving unit of the liquid crystal display driving circuit as claimed in claim 3, wherein the output buffer is composed of CMOS. 6 . The driving unit of the liquid crystal display driving circuit as claimed in claim 3 , wherein the potential shifter comprises an inverter composed of complementary metal oxide semiconductors. 7 . 7. The driving unit of the liquid crystal display driving circuit as claimed in claim 6, wherein the inverter in the potential shifter comprises a metal oxide semiconductor connected to its own source/drain and gate. 8. The driving unit of the liquid crystal display driving circuit according to claim 3, further comprising a dynamic register electrically coupled to the clock input terminal and the potential shifter. Between the devices, and according to a control signal group, it is determined whether to conduct the electrical channel from the clock input terminal to the level shifter. 9. The driving unit of the liquid crystal display driving circuit according to claim 8, wherein the dynamic register comprises: a register output terminal electrically coupled to the potentiometer; A first control signal input circuit receives a previous driving signal output by the previous driving unit of the driving unit, and determines whether to conduct the electrical connection between the clock input terminal and the temporary storage according to the previous driving signal. electrical path between the output terminals of the device; and A second control signal input circuit, which receives a subsequent driving signal output by the subsequent driving unit of the driving unit, and determines whether to conduct the register output terminal and the low target potential according to the subsequent driving signal electrical channels between them. 10. The driving unit of the liquid crystal display driving circuit according to claim 8, wherein the dynamic register comprises: a register output terminal electrically coupled to the potentiometer; A first control signal input circuit receives a previous drive signal output by the previous drive unit of the drive unit, and determines whether to conduct the clock input terminal and the temporary register output according to the previous drive signal electrical pathways between terminals; and a second control signal input circuit, which receives the previous driving signal and the output of the level shifter, and determines whether to conduct the electrical channel between the driving unit and the low target potential; Wherein, the output of the potentiometer is opposite to the target signal output by the driving unit. 11. The driving unit of the liquid crystal display driving circuit according to claim 10, further comprising: A potential clamper, electrically coupled between the high target potential and the output terminal of the register, and determines whether to conduct the electrical connection between the output terminal of the register and the high target potential according to the previous driving signal aisle. 12. The driving unit of the liquid crystal display driving circuit as claimed in claim 11, wherein the potential clamper comprises a P-type metal oxide semiconductor.

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