CN100399379C - Display panel, related electronic device and driving method, and image display device - Google Patents

Abstract

A display panel comprises a first signal line, a first data signal line, a first scanning line and a second scanning line, wherein the first signal line, the first data signal line and the first scanning line are staggered; the first pixel unit is coupled with the first data signal line and the first scanning line; the first switch element has a first end coupled to the first data signal line; the first storage capacitor is coupled between the second end of the first switch element and a grounding end; and a second switch element coupled between the first storage capacitor and the first signal line.

Description

Display panel and related electronic device and driving method, image display device

technical field

The present invention relates to a display panel, in particular to a display panel capable of temporarily storing display data from a data driver.

Background technique

FIG. 1A is a schematic diagram of a conventional display panel, and FIG. 1B is a driving sequence diagram of the conventional display panel. As shown in FIG. 1A, a general conventional display panel has K scanning signal lines G1-GK, N data signal lines DL1-DLN, a plurality of pixel units P11-PNK, a scanning driver and a data driver. The scan driver sequentially drives the scan signal lines G1 -GK, so that the pixel units P11 -PNK can be driven according to the display data output by the data driver on the data signal lines. For example, when the scan signal line G1 is activated by the scan driver, the display data output from the data driver to the data signal lines DL1 -DLN will drive the pixel units P11 -PN1 connected to the scan signal line G1 . Similarly, when the scan signal line G2 is activated by the scan driver, the display data output from the data driver to the data signal lines DL1-DLN will drive the pixel units P12-PN2 connected to the scan signal line G2. By analogy, when the scan signal line GK is activated by the scan driver, the display data output from the data driver to the data signal lines DL1-DLN will drive the pixel units P1K-PNK connected to the scan signal line GK.

Generally, the data driver includes a plurality of driving integrated circuits (ICs) corresponding to the data signal lines DL1˜DLN, and each driving IC is used to drive a predetermined number of signal lines. When the number of data signal lines is larger, the number of required driving ICs increases and the number of flexible printed circuit boards (FPCs) required for driving ICs also increases. Therefore, during the manufacturing process, the man-hours for bonding the driver IC and the man-hours for welding the flexible printed circuit board to the panel will both increase.

Contents of the invention

In view of this, one of the objectives of the present invention is to store display data or precharge data from the data driver, so as to reduce the number of driving ICs required in the data driver.

To achieve the above object, the present invention provides a display panel, comprising a first signal line, a first data signal line, a first scan line intersecting with the first data signal line; a first pixel unit is coupled to the first data a signal line and the first scan line; a first switch element having a first end coupled to the first data signal line; a first storage capacitor coupled between a second end of the first switch element and a ground end; and The second switch element is coupled between the first storage capacitor and the first signal line.

According to the above purpose, the present invention also provides a driving method of a display panel, which includes firstly pre-storing the first set of data in the N first storage capacitors during the M-1th cycle during the Mth cycle, and using N The data signal lines are transmitted to the N corresponding first pixel units, thereby driving the N corresponding first pixel units, and at the same time storing the second set of data from the data driver on the second signal line to the corresponding N In the second storage capacitor. And in the M+1th cycle, the second group of data stored in the N second storage capacitors is transmitted to the corresponding N second pixel units through the N data signal lines, and driven The corresponding N second pixel units simultaneously store the third group of data from the data driver on the first signal line into the corresponding N first storage capacitors.

Description of drawings

FIG. 1A is a conventional display panel.

FIG. 1B is a control sequence diagram of a conventional display panel.

2A and 2B are display panels according to embodiments of the present invention.

FIG. 3 is a control sequence diagram of the display panel of the present invention.

FIG. 4 is another control sequence diagram of the display panel of the present invention.

FIG. 5 is another control sequence diagram of the display panel of the present invention.

FIG. 6 is an electronic device according to an embodiment of the present invention.

Label description

100: display panel; 110: scan driver;

120: data driver; 130: pixel array;

200: electronic device; 210: shell;

220: power supply;

G1～GK: scanning signal line; SL1～SLN: signal line;

DL1～DL6: data signal line; P11～PNK: pixel unit;

C11～C62: capacitors; M11～M64: switching elements;

SWC1～SWC12: signal control circuit;

Godd, Geven, Gr, Gg, Gb: control signals;

D10r～D18r, D10g～D18g, D10b～D18b, D20r～D28r, D20g～D28g, D20b～D28b: display data;

D11r～D18r, D11g～D18g, D11b～D18b, D21r～D28r, D21g～D28g, D21b～D28b: Precharge data.

Detailed ways

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and in conjunction with the attached drawings, the detailed description is as follows:

2A and 2B are schematic diagrams showing the display panel of the present invention. In this figure, the commonly used pixel arrays, such as 1024×768 pixel arrays or 800×600 pixel arrays, are not used to illustrate; only simplified pixel arrays, such as the 6×4 pixel arrays in Figures 2A and 2B A pixel array of , to illustrate the listing. As shown in the figure, the display panel 100 includes a scan driver 110 , a data driver 120 , a pixel array 130 and a plurality of signal control circuits SWC1 - SWC12 .

The scan driver 110 is used for scanning the pixel array 130 according to a control signal of a timing controller (not shown), that is, sequentially activates the scan signal lines G1 - G4 of the pixel array 130 . In this embodiment, the scan driver 110 activates only one of the scan signal lines G1 - G4 of the pixel array 130 in a scan period. The data driver 120 also outputs data to the pixel array 130 through the signal lines SL1 - SL4 according to the control signal of the timing controller (not shown).

The pixel array 130 includes data signal lines DL1 - DL6 , scan signal lines G1 - G4 and a plurality of pixel units P11 - P64 . Each pixel unit includes a switching transistor, a storage capacitor, and a liquid crystal capacitor, wherein the switching transistor has a control terminal coupled to a corresponding scanning signal line, a first terminal coupled to a corresponding data signal line, and a second terminal coupled to a corresponding storage capacitors and liquid crystal capacitors. Each pixel unit is coupled to the corresponding data signal line and the corresponding scanning signal line. For example, the pixel unit P11 is coupled to the data signal line DL1 and the scanning signal line G1, and the pixel unit P21 is coupled to the data signal line DL2 and the scanning signal line. The signal line G1, and the pixel unit P31 are coupled to the data signal line DL3 and the scanning signal line G1, and the rest of the pixel units P14-P64 are deduced by analogy, which will not be repeated here.

Each signal control circuit (SWC1˜SWC12) includes a first switch element, a second switch element and a capacitor, and each signal control circuit is arranged between a signal line of the data driver and a data signal line. For example, the signal control circuit SWC1 is disposed between the data signal line DL1 and the signal line SL1, the signal control circuit SWC2 is disposed between the data signal line DL1 and the signal line SL2, and the signal control circuit SWC3 is disposed between the data signal line Between DL2 and the signal line SL1, the signal control circuit SWC4 is disposed between the data signal line DL2 and the signal line SL2, and the rest of the signal control circuits SWC5-SWC12 are deduced in the same way, which will not be repeated here. It should be noted that the first switching elements M11, M21, M31, M41, M51 and M61 of the signal control circuits SWC1, SWC3, SWC5, SWC7, SWC9 and SWC11 are coupled to the control signal Godd, and the signal control circuits SWC2, SWC4 The first switching elements M13 , M23 , M33 , M43 , M53 and M63 of SWC6 , SWC8 , SWC10 and SWC12 are coupled to the control signal Geven. In addition, the second switch elements M12, M14, M42, M44 of the signal control circuits SWC1, SWC2, SWC7, and SWC8 are coupled to the control signal Gr, and the second switch elements M22, M24 of the signal control circuits SWC3, SWC4, SWC9, and SWC10 , M52, M54 are coupled to the control signal Gg, and the second switching elements M32, M34, M62, M64 of the signal control circuits SWC5, SWC6, SWC11 and SWC12 are coupled to the control signal Gb.

In an embodiment of the present invention, the switching element used can be formed by low temperature polysilicon (LTPS) technology or amorphous silicon technology, and the data driver is on at least one of the signal lines during the scanning period, Send three batches of data sequentially. In the present invention, through the operation of the signal control circuit, the data driver can use two signal lines to transmit the display data required by the three data signal lines in the pixel array.

first embodiment

FIG. 3 is a control sequence diagram of the display panel of the present invention. The driving method of the display panel of the present invention, please refer to FIGS. 2A and 2B and FIG. 3 , is described as follows.

During the period PD1, the scan driver 110 activates the scan signal line G1, the switch elements M11, M21, M31, M41, M51 and M61 are turned on according to the control signal Godd, but the switch elements M13, M23, M33, M43, M53 and M63 are not conducted according to the control of the control signal Geven. Since the switching elements M11, M21, M31, M41, M51, and M61 are turned on according to the control signal Godd, the display data stored in the capacitors C11, C21, C31, C41, C51, and C61 in the previous cycle will be passed through The switching elements M11 - M61 are respectively output to the data signal lines DL1 - DL6 for driving the pixel units P11 - P61 connected to the scanning signal line G1 .

On the other hand, the data driver 120 cooperates with the control signals Gr, Gg and Gb to sequentially output the display data D10r, D10g, D10b, D20r, D20g and D20b on the data signal lines SL2 and SL4, so that the display data D10r, D10g, D10b, D20r, D20g and D20b are respectively stored in capacitors C12, C22, C32, C42, C52 and C62. Specifically, when the data driver 120 outputs the display data D10r and D20r on the signal lines SL2 and SL4 respectively, the switching elements M14 and M44 are turned on by the control signal Gr, so that the display data D10r on the signal lines SL2 and SL4 and D20r are stored in capacitors C12 and C42 respectively. When the data driver 120 outputs the display data D10g and D20g on the signal lines SL2 and SL4 respectively, the switching elements M24 and M54 will be turned on due to the control signal Gg, so that the display data D10r and D20r on the signal lines SL2 and SL4 will be respectively It is stored in capacitors C22 and C52. When the data driver 120 outputs the display data D10b and D20b on the signal lines SL2 and SL4 respectively, the switching elements M34 and M64 will be turned on by the control signal Gb, so that the display data D10b and D20b on the signal lines SL2 and SL4 will be respectively It is stored in capacitors C32 and C62. Since the switching elements M13, M23, M33, M43, M53 and M63 are not turned on according to the control signal Geven, the display data D10r, D10g, D10b, D20r, D20g and D20b are not output to the data signal lines DL1˜DL6.

During the period PD2, the scanning driver 110 starts the scanning signal line G2, the switching elements M11, M21, M31, M41, M51 and M61 are not turned on according to the control of the control signal Godd, and the switching elements M13, M23, M33, M43, M53 and M63 are turned on according to the control of the control signal Geven. Since the switching elements M13, M23, M33, M43, M53 and M63 are turned on according to the control signal Geven, the display data D10r, D10g, D10b, D20r, D20g and D20b are respectively output to the data signal lines DL1-DL6 through the switching elements M13-M63 for driving the pixel units P12-P62 connected to the scanning signal line G2.

On the other hand, the data driver 120 cooperates with the control signals Gr, Gg and Gb to sequentially output the display data D11r, D11g, D11b, D21r, D21g and D21b on the data signal lines SL1 and SL3, so that the display data D11r, D11g, D11b, D21r, D21g and D21b are respectively stored in capacitors C11, C21, C31, C41, C51 and C61. Specifically, when the data driver 120 outputs the display data D11r and D21r on the signal lines SL1 and SL3 respectively, the switching elements M12 and M42 are turned on by the control signal Gr, so that the display data D11r on the signal lines SL1 and SL3 and D21r are stored in capacitors C11 and C41 respectively. When the data driver 120 outputs the display data D11g and D21g on the signal lines SL1 and SL3 respectively, the switch elements M22 and M52 will be turned on by the control signal Gg, so that the display data D11g and D21g on the signal lines SL1 and SL3 will be respectively It is stored in capacitors C21 and C51. When the data driver 120 outputs the display data D11b and D21b on the signal lines SL1 and SL3 respectively, the switching elements M32 and M62 will be turned on by the control signal Gb, so that the display data D11b and D21b on the signal lines SL1 and SL3 will be respectively It is stored in capacitors C31 and C61. Since the switch elements M11, M21, M31, M41, M51 and M61 are not turned on according to the control of the control signal Godd at this time, the display data D11r and D11g stored in the capacitors C11, C21, C31, C41, C51 and C61 , D11b, D21r, D21g and D21b are not output to the data signal lines DL1˜DL6.

By analogy, during the period PD3, the display data D11r, D11g, D11b, D21r, D21g and D21b stored in the capacitors C11, C21, C31, C41, C51 and C61 during the period PD2 will pass through the switching elements M11-M61 , respectively output to the data signal lines DL1-DL6 for driving the pixel units P13-P63 connected to the scanning signal line G3, and the data driver 120 sequentially outputs the display data D12r, D12g, D12b, D22r, D22g and D22b in the data The signal lines SL2 and SL4 are respectively stored in capacitors C12, C22, C32, C42, C52 and C62.

During the period PD4, the display data D12r, D12g, D12b, D22r, D22g and D22b stored in the capacitors C12, C22, C32, C42, C52 and C62 during the period PD3 are respectively output to the The data signal lines DL1-DL6 are used to drive the pixel units P14-P64 connected to the scanning signal line G4, and the data driver 120 sequentially outputs display data D13r, D13g, D13b, D23r, D23g and D23b to the data signal lines SL1 and Above SL3, they are respectively stored in capacitors C11, C21, C31, C41, C51 and C61. The operation of the display panel 100 in the periods PD5 - PD8 is similar to that of the periods PD1 - PD4 , and will not be repeated here.

In this embodiment, the data driver stores the display data in the capacitor of the signal control circuit through one signal line in the same cycle, and stores the display data in the capacitor of the signal control circuit through another signal line in the previous cycle. The display data in the capacitor is output to the corresponding data signal line in the pixel array. Therefore, the display panel in the present invention can use two signal lines to transmit the display data required by the three data signal lines in the pixel array. In other words, the number of signal lines connected to the data driver can be reduced, and the number of driving ICs in the data driver can also be reduced.

second embodiment

FIG. 4 is another control sequence diagram of the display panel of the present invention. The driving method of the display panel of the present invention is described as follows with reference to FIGS. 2A and 2B and FIG. 4 .

During the period PD1, the scan driver 110 starts the scan signal line G1, the switch elements M11, M21, M31, M41, M51 and M61 are turned on according to the control signal Godd, but the switch elements M13, M23, M33, M43, M53 and M63 are not conducted according to the control of the control signal Geven. The data driver 120 cooperates with the control signals Gr, Gg, and Gb to sequentially output display data D10r, D10g, and D10b to the signal line SL1, display data D11r, D11g, and D11b to the signal line SL2, and display data D20r, D20g, and D20b. to the signal line SL3, and display data D21r, D21g and D21b to the signal line SL4.

When the data driver 120 respectively outputs the display data D10r, D11r, D20r and D21r on the signal lines SL1, SL2, SL3 and SL4, the switching elements M12 and M42 will be turned on by the control signal Gr, so the pixel unit P11 will be based on the previous The display data stored in the capacitor C11 and the display data D10r on the signal line SL1 are driven periodically; and the pixel unit P41 is driven according to the display data stored in the capacitor C41 and the display data D20r on the signal line SL3 in the previous cycle. At the same time, the switch elements M14 and M44 are also turned on by the control signal Gr, so that the display data D11r and D21r on the signal lines SL2 and SL4 are stored in the capacitors C12 and C42 respectively.

When the data driver 120 respectively outputs the display data D10g, D11g, D20g and D21g on the signal lines SL1, SL2, SL3 and SL4, the switching elements M22 and M52 will be turned on by the control signal Gg, so the pixel unit P21 will be according to the previous The display data stored in the capacitor C21 and the display data D10g on the signal line SL1 are driven periodically; and the pixel unit P51 is driven according to the display data stored in the capacitor C51 and the display data D20g on the signal line SL3 in the previous period. At the same time, the switch elements M24 and M54 are also turned on by the control signal Gg, so that the display data D11g and D21g on the signal lines SL2 and SL4 are stored in the capacitors C22 and C52 respectively.

When the data driver 120 respectively outputs the display data D10b, D11b, D20b and D21b on the signal lines SL1, SL2, SL3 and SL4, the switching elements M32 and M62 will be turned on by the control signal Gb, so the pixel unit P31 will be according to the previous The display data stored in the capacitor C31 and the display data D10b on the signal line SL1 are driven periodically; and the pixel unit P61 is driven according to the display data stored in the capacitor C61 and the display data D20b on the signal line SL3 in the previous period. At the same time, the switch elements M34 and M64 are also turned on by the control signal Gb, so that the display data D11b and D21b on the signal lines SL2 and SL4 are stored in the capacitors C32 and C62 respectively.

During the period PD2, the scanning driver 110 starts the scanning signal line G2, the switching elements M11, M21, M31, M41, M51 and M61 are not turned on according to the control of the control signal Godd, and the switching elements M13, M23, M33, M43, M53 and M63 are turned on according to the control signal Geven. The data driver 120 cooperates with the control signals Gr, Gg, and Gb to sequentially output the display data D12r, D12g, and D12b to the signal line SL1, the display data D11r, D11g, and D11b to the signal line SL2, and the display data D22r, D22g, and D22b is on the signal line SL3, and the display data D21r, D21g and D21b are on the signal line SL4.

When the data driver 120 respectively outputs the display data D12r, D11r, D22r and D21r on the signal lines SL1, SL2, SL3 and SL4, the switching elements M14 and M44 will be turned on due to the control signal Gr, so the pixel unit P12 will be turned on according to the period The display data D11r stored in the capacitor C12 by PD1 and the display data D11r on the signal line SL2 are driven; and the pixel unit P42 is driven by the display data D21r stored in the capacitor C42 and the display data D21r on the signal line SL4 according to the period PD1. At the same time, the switch elements M12 and M42 are also turned on by the control signal Gr, so that the display data D12r and D22r on the signal lines SL1 and SL3 are stored in the capacitors C11 and C41 respectively.

When the data driver 120 respectively outputs the display data D12g, D11g, D22g and D21g on the signal lines SL1, SL2, SL3 and SL4, the switch elements M24 and M54 will be turned on due to the control signal Gg, so the pixel unit P22 will The display data D11g stored in the capacitor C22 by PD1 and the display data D11g on the signal line SL2 are driven; and the pixel unit P52 is driven by the display data D21g stored in the capacitor C52 and the display data D21g on the signal line SL4 according to the period PD1. At the same time, the switch elements M22 and M52 are also turned on by the control signal Gg, so that the display data D12g and D22g on the signal lines SL1 and SL3 are stored in the capacitors C21 and C51 respectively.

When the data driver 120 outputs the display data D12b, D11b, D22b and D21b respectively on the signal lines SL1, SL2, SL3 and SL4, the switch elements M34 and M64 will be turned on due to the control signal Gb, so the pixel unit P32 will The display data D11b stored in the capacitor C32 by PD1 and the display data D11b on the signal line SL2 are driven; and the pixel unit P62 is driven by the display data D21b stored in the capacitor C62 and the display data D21b on the signal line SL4 according to the period PD1. At the same time, the switch elements M32 and M62 are also turned on by the control signal Gb, so that the display data D12b and D22b on the signal lines SL1 and SL3 are stored in the capacitors C31 and C61 respectively.

By analogy, during the period PD3, the data driver 120 stores the display data D12r, D12g, D12b, D22r, D22g, and D22b on the signal lines SL1 and SL3 in the capacitors C11, C21, C31, C41, and C51 during the period PD2. With the display data D12r, D12g, D12b, D22r, D22g and D22b in C61, the pixel units P13-P63 connected to the scanning signal line G3 are driven by the data signal lines DL1-DL6. The data driver 120 further sequentially outputs the display data D13r, D13g, D13b, D23r, D23g and D23b on the data signal lines SL2 and SL4, and stores them in the capacitors C12, C22, C32, C42, C52 and C62 respectively.

During the period PD4, the data driver 120 stores the display data D13r, D13g, D13b, D23r, D23g and D23b on the signal lines SL2 and SL4 in the capacitors C12, C22, C32, C42, C52 and C62 during the period PD3. The display data D13r, D13g, D13b, D23r, D23g, and D23b of the display data drive the pixel units P14-P64 connected to the scanning signal line G4 through the data signal lines DL1-DL6. The data driver 120 further sequentially outputs the display data D14r, D14g, D14b, D24r, D24g and D24b on the data signal lines SL1 and SL3, and stores them in the capacitors C11, C21, C31, C41, C51 and C61 respectively. The actions of the display panel in the periods PD5 - PD8 are similar to those of the periods PD1 - PD4 , and will not be repeated here.

In this embodiment, the data driver sequentially generates the same data on the same signal line in two consecutive cycles, so that the display panel can increase the charging of the capacitor in the signal control circuit in addition to the advantages of the first embodiment. times to avoid voltage distortion.

third embodiment

FIG. 5 is another control sequence diagram of the display panel of the present invention. The driving method of the display panel of the present invention is described as follows with reference to FIGS. 2A and 2B and FIG. 5 .

In the period PD1, the scan driver 110 starts the scan signal line G1, the switch elements M11, M21, M31, M41, M51 and M61 are turned on according to the control of the control signal Godd, but the switch elements M13, M23, M33, M43, M53 and M63 are not conducted according to the control of the control signal Geven. The data driver 120 cooperates with the control signals Gr, Gg, and Gb to sequentially output display data D10r, D10g, and D10b to the signal line SL1, pre-fill data D11r, D11g, D11b to the signal line SL2, and display data D20r, D20g. and D20b onto the signal line SL3, and pre-charge data D21r, D21g and D21b onto the signal line SL4.

When the data driver 120 outputs the data D10r, D11r, D20r and D21r respectively on the signal lines SL1, SL2, SL3 and SL4, the switching elements M12 and M42 will be turned on due to the control signal Gr, so the pixel unit P11 will be turned on according to the previous cycle. The precharge data stored in the capacitor C11 and the display data D10r on the signal line SL1 are driven; and the pixel unit P41 is driven according to the precharge data stored in the capacitor C41 and the display data D20r on the signal line SL3 in the previous period. At the same time, the switch elements M14 and M44 are also turned on by the control signal Gr, so that the precharge data D11r and D21r on the signal lines SL2 and SL4 are stored in the capacitors C12 and C42 respectively.

When the data driver 120 respectively outputs the data D10g, D11g, D20g and D21g on the signal lines SL1, SL2, SL3 and SL4, the switching elements M22 and M52 will be turned on due to the control signal Gg, so the pixel unit P21 will be based on the previous cycle. The precharge data stored in the capacitor C21 and the display data D10g on the signal line SL1 are driven; and the pixel unit P51 is driven according to the precharge data stored in the capacitor C51 and the display data D20g on the signal line SL3 in a previous period. At the same time, the switch elements M24 and M54 are also turned on by the control signal Gg, so that the precharge data D11g and D21g on the signal lines SL2 and SL4 are stored in the capacitors C22 and C52 respectively.

When the data driver 120 respectively outputs the display data D10b, D11b, D20b and D21b on the signal lines SL1, SL2, SL3 and SL4, the switching elements M32 and M62 will be turned on by the control signal Gb, so the pixel unit P31 will be according to the previous The precharge data stored in the capacitor C31 and the display data D10b on the signal line SL1 are driven periodically; and the pixel unit P61 is driven according to the precharge data stored in the capacitor C61 and the display data D20b on the signal line SL3 in the previous cycle. At the same time, the switch elements M34 and M64 are also turned on by the control signal Gb, so that the precharge data D11b and D21b on the signal lines SL2 and SL4 are stored in the capacitors C32 and C62 respectively.

During the period PD2, the scanning driver 110 starts the scanning signal line G2, the switching elements M11, M21, M31, M41, M51 and M61 are not turned on according to the control of the control signal Godd, and the switching elements M13, M23, M33, M43, M53 and M63 are turned on according to the control signal Geven. The data driver 120 cooperates with the control signals Gr, Gg and Gb to sequentially output the data D12r, D12g and D12b to the signal line SL1, the display data D11r, D11g, D11b to the signal line SL2, the pre-fill data D22r, D22g and D22b is on the signal line SL3, and the display data D21r, D21g and D21b are on the signal line SL4.

When the data driver 120 outputs the data D12r, D11r, D22r and D21r respectively on the signal lines SL1, SL2, SL3 and SL4, the switching elements M14 and M44 will be turned on due to the control signal Gr, so the pixel unit P12 will be based on the period PD1 The precharge data D11r stored in the capacitor C12 and the display data D11r on the signal line SL2 are driven; and the pixel unit P42 is driven by the precharge data D21r stored in the capacitor C42 and the display data D21r on the signal line SL4 according to the period PD1. At the same time, the switch elements M12 and M42 are also turned on by the control signal Gr, so that the precharge data D12r and D22r on the signal lines SL1 and SL3 are stored in the capacitors C11 and C41 respectively.

When the data driver 120 respectively outputs the display data D12g, D11g, D22g and D21g on the signal lines SL1, SL2, SL3 and SL4, the switch elements M24 and M54 will be turned on due to the control signal Gg, so the pixel unit P22 will The precharge data D11g stored in the capacitor C22 and the display data D11g on the signal line SL2 are driven by PD1; and the pixel unit P52 is driven according to the cycle PD1. The precharge data D21g stored in the capacitor C52 and the display data D21g on the signal line SL4 . At the same time, the switch elements M22 and M52 are also turned on by the control signal Gg, so that the precharge data D12g and D22g on the signal lines SL1 and SL3 are stored in the capacitors C21 and C51 respectively.

When the data driver 120 respectively outputs the data D12b, D11b, D22b and D21b on the signal lines SL1, SL2, SL3 and SL4, the switching elements M34 and M64 will be turned on due to the control signal Gb, so the pixel unit P32 will be according to the cycle PD1 The precharge data D11b stored in the capacitor C32 and the display data D11b on the signal line SL2 are driven; and the pixel unit P62 is driven according to the period PD1 from the precharge data D21b stored in the capacitor C62 and the display data D21b on the signal line SL4. At the same time, the switch elements M32 and M62 are also turned on by the control signal Gb, so that the precharge data D12b and D22b on the signal lines SL1 and SL3 are stored in the capacitors C31 and C61 respectively.

By analogy, during the period PD3, the data driver 120 stores the display data D12r, D12g, D12b, D22r, D22g, and D22b on the signal lines SL1 and SL3 in the capacitors C11, C21, C31, C41, and C51 during the period PD2. With the pre-fill data D12r, D12g, D12b, D22r, D22g and D22b in C61, the pixel units P13-P63 connected to the scan signal line G3 are driven through the data signal lines DL1-DL6. The data driver 120 further sequentially outputs the precharge data D13r, D13g, D13b, D23r, D23g and D23b on the data signal lines SL2 and SL4, and stores them in the capacitors C12, C22, C32, C42, C52 and C62 respectively.

During the period PD4, the data driver 120 stores in the capacitors C12, C22, C32, C42, C52 and C62 during the period PD3 according to the display data D13r, D13g, D13b, D23r, D23g and D23b on the signal lines SL2 and SL4. The pre-charge data D13r, D13g, D13b, D23r, D23g and D23b drive the pixel units P14-P64 connected to the scanning signal line G4 through the data signal lines DL1-DL6. The data driver 120 further sequentially outputs the precharge data D14r, D14g, D14b, D24r, D24g and D24b on the data signal lines SL1 and SL3, and stores them in the capacitors C11, C21, C31, C41, C51 and C61 respectively. . The actions of the display panel in the periods PD5-PD8 are similar to those in the periods PD1-PD4, and will not be repeated here.

In this embodiment, the data driver stores the precharge data corresponding to the required display data in the next cycle into the capacitor of the signal control circuit in one cycle, and outputs the required display data in the next cycle To the data signal line, it is used to drive the display unit in accordance with the stored pre-charge data. The precharge data system can be an overdrive voltage signal corresponding to required display data. For example, when the display data is a 3V voltage signal, the overdrive voltage signal can be a voltage signal multiplied by a predetermined multiple, such as 3.3V and so on. Therefore, in addition to the advantages of the first and second embodiments, this embodiment can avoid insufficient charging time by increasing the voltage of the pre-charged data.

In the display panel of the present invention, every two signal lines in the data driver can drive three data signal lines in the pixel array, so the number of required driving ICs in the data driver can be reduced. Therefore, the flexible printed circuit board required for the driver IC can also be reduced, and in the manufacturing process, the man-hours of welding the driver IC and the man-hour of welding the flexible printed circuit board to the panel will be reduced.

In the above three embodiments, two signal lines are used to cooperate with three control signals Gr, Gg, and Gb to achieve the effect of actuating the three data signal lines to achieve display; but the present invention is not limited to only using two signal lines to control 3 data signal lines, for example, use two signal lines with four control signals to achieve the effect of controlling the movement of four data signal lines to achieve the display effect; similarly, you can also use two signal lines with five control signals to achieve control The five data signal lines are actuated to achieve the display effect; of course, two signal lines can also be used in conjunction with six control signals to control the six data signal lines to actuate to achieve the display effect. In other words, 2 signals can be used in conjunction with N control signal lines to control the operation of N data signal lines to achieve the display effect. In an A×B pixel array, N can be any positive integer greater than 2 but less than or equal to A/2, such as 3, 4, 5 . . . .

In the above-mentioned three embodiments, the output signal of the signal line is used to cooperate with the three control signals Gr, Gg, and Gb to capture the signal during the active period; that is, one signal line is used in the embodiment, but in the One cycle contains 3 signals for illustration, but the present invention is not limited to only sending 3 signals in one cycle, and it can also be (3×M) times signals, where M=1, 2, 3, 4, 5 , 6, 7, 8, 9... In other words, the scanning frequency within one cycle can be increased.

FIG. 6 is an electronic device according to an embodiment of the present invention. The electronic device 200 uses the aforementioned display panel, and the display panel 100 may be a liquid crystal display panel, but is not limited thereto. The electronic device 200 can be a portable device, such as a personal digital assistant (PDA), a notebook computer, a tablet computer, a mobile phone, or a display...etc. In general, the electronic device 200 has a casing 210 , a display panel 100 and a power supply 220 , the power supply 220 is used to provide power voltage to the display panel 100 , and the display panel is used to display images.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the appended claims.

Claims (27)

1. display panel comprises:

First signal wire;

First data signal line;

First sweep trace is staggered with this first data signal line;

First pixel cell couples this first data signal line and this first sweep trace;

First on-off element has first end and couple this first data signal line, and a control end receives one first control signal;

First storage capacitors is coupled between second end and earth terminal of this first on-off element; And

The second switch element is coupled between this first storage capacitors and this first signal wire, and has a control end and receive one second control signal;

The secondary signal line;

The 3rd on-off element has that first end couples this first data signal line and a control end receives one the 3rd control signal;

Second storage capacitors is coupled between second end and this earth terminal of the 3rd on-off element; And

The 4th on-off element is coupled between this second storage capacitors and this secondary signal line, and has a control end and receive this second control signal, and

Other N-1 bar data signal line, this N-1 bar data signal line is connected with the secondary signal line with first signal wire with same connected mode, wherein N 〉=3.

2. display panel according to claim 1, wherein this first pixel cell comprises pixel cell on-off element, pixel cell storage capacitors and liquid crystal capacitance, wherein this pixel cell on-off element has first end and couples this first data signal line, second end couples this pixel cell storage capacitors and this liquid crystal capacitance, and control end couples this first sweep trace.

3. display panel according to claim 1 wherein also comprises:

Second data signal line;

Second pixel cell is to couple this second data signal line and this first sweep trace;

The 5th on-off element has first end and couple this second data signal line, and a control end couples this first control signal;

The 3rd storage capacitors is coupled between second end and this earth terminal of the 5th on-off element; And

The 6th on-off element is coupled between the 3rd storage capacitors and this first signal wire, and has a control end and couple the 4th control signal.

4. display panel according to claim 3 also comprises:

Minion is closed element, have first end and couple this second data signal line, and a control end couples the 3rd control signal;

The 4th storage capacitors is coupled to this minion and closes between second end and this earth terminal of element; And

Octavo is closed element, is coupled between the 4th storage capacitors and this secondary signal line, and has a control end and couple the 4th control signal.

5. display panel according to claim 4 wherein also comprises:

The 3rd data signal line;

The 3rd pixel cell is to couple the 3rd data signal line and this first sweep trace;

The 9th on-off element has first end and couples the 3rd data signal line, and a control end couples this first control signal;

The 5th storage capacitors is coupled between second end and this earth terminal of the 9th on-off element; And

The tenth on-off element is coupled between the 5th storage capacitors and this first signal wire, and has a control end and couple the 5th control signal.

6. display panel according to claim 5 also comprises:

The 11 on-off element has first end and couple the 3rd data signal line, and a control end couples the 3rd control signal;

The 6th storage capacitors is coupled between second end and this earth terminal of the 11 on-off element; And

Twelvemo is closed element, is coupled between the 6th storage capacitors and this secondary signal line, and has a control end and couple the 5th control signal.

7. display panel according to claim 6 comprises that also the one scan driver couples this first sweep trace.

8. display panel according to claim 6, also comprise a data driver couple this first, this second with the 3rd data signal line.

9. display panel according to claim 6, wherein this first to the 5th control signal is provided by driver.

10. display panel according to claim 7, wherein this first to the 5th control signal is provided by this scanner driver.

11. display panel according to claim 1, wherein this display panel is a display panels.

12. display panel according to claim 1, wherein this display panel is an organic LED display panel.

13. an electronic installation comprises:

Display panel as claimed in claim 1; And

Power-supply unit is used to supply power to above-mentioned display panel.

14. electronic installation according to claim 13, wherein above-mentioned display panel are display, notebook computer device, mobile phone, flat computer or personal digital assistant.

15. a driving method is applied to display panel, comprises the following steps:

At M during the cycle, M-1 is stored in N first group of data in first storage capacitors in advance during the cycle, by N bar data signal line, be sent to N the first corresponding pixel cell, and use and drive this N the first corresponding pixel cell, simultaneously with on the secondary signal line from second group of data storing of data driver to individual second storage capacitors of corresponding N; And

At M+1 during the cycle, with these stored second group of data in this N second storage capacitors, by this N bar data signal line, be sent to corresponding N second pixel cell, and use and drive this corresponding N second pixel cell, simultaneously with on first signal wire from the 3rd group of data storing of this data driver to this corresponding N first storage capacitors.

16. driving method according to claim 15, wherein these the second group of data on this secondary signal line are to be stored in order in N second storage capacitors of this correspondence, and the 3rd group of data on this first signal wire are to be stored in order in this corresponding N first storage capacitors.

17. driving method according to claim 15, wherein N is an integer and greater than 2.

18. driving method according to claim 16, wherein these first group of data, second group of data, the 3rd group of data are video data.

19. driving method according to claim 16, also be included in this M in the cycle, with on this first signal wire from the 4th group of data of this data driver, by this N bar data signal line, be sent to this N the first corresponding pixel cell, make that this N the first corresponding pixel cell driven by a N batch data and the 4th group of data.

20. driving method according to claim 19, also be included in this M+1 in the cycle, with on this secondary signal line from the 5th group of data of this data driver, by this N bar data signal line, be sent to this N the second corresponding pixel cell, make that this N the second corresponding pixel cell driven by these second group of data and the 5th group of data.

21. driving method according to claim 20, wherein at this M in the cycle, the 4th group of data on this first signal wire are to be sent to this N the first corresponding pixel cell in order, and in the cycle, the 5th group of data on this secondary signal line are to be sent to this N the second corresponding pixel cell in order at this M+1.

22. driving method according to claim 21, wherein these first group of data is identical video data with the 4th group of data, and these second group of data is identical video data with the 5th group of data.

23. driving method according to claim 21, wherein the 4th group of data and the 5th group of data are video data, and these first group of data is the overdrive voltage signal corresponding to the 4th group of data, and these second group of data is the overdrive voltage signal corresponding to the 5th group of data.

24. an image display device comprises:

Data driver;

N bar data signal line; And

One group of signal control circuit is coupled between this data driver and this N bar data signal line, in order in horizontal scanning period, by the video data of K signal line reception from this data driver, and input to this N bar data signal line, wherein K and N are all positive integer, N＞K and

Be not integer, and $\frac{N}{K}=\frac{3}{2},$

Wherein this group signal control circuit is during the cycle, with first group of data that M-1 prestored during the cycle, to input to this N bar data signal line in M, stores on this K signal line second group of data from this data driver simultaneously.

25. image display device according to claim 24, wherein this group signal control circuit is according to one group of external signal, stores this second group of data in order, and simultaneously these first group of data is inputed to this N bar data signal line.

26. image display device according to claim 24, wherein this group signal control circuit comprises two on-off elements and a storage capacitors.

27. image display device according to claim 24, wherein this group signal control circuit is formed by low temperature polycrystalline silicon or amorphous silicon technology.

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