CN100396828C - Semi-insulating GaAs wafer and manufacturing method thereof - Google Patents

Abstract

The present invention limits the in-plane dislocation density (EPD value) and residual stress value of the wafer to a certain range through the GaAs crystal obtained by the LEC method or the vertical melt method (VB method, VGF method), and can manufacture a Semi-insulating GaAs wafers that do not generate slip dislocations during heat treatment such as activation annealing after ion implantation. The present invention can obtain the dislocation density (EPD) in the wafer plane in the range of 3×10 ⁴ /cm ² ≤ EPD ≤ 1×10 ⁵ /cm ² , and the residual stress value in the wafer plane obtained by photoelasticity measurement (|Sr-St|) in the range of 1.8×10 ^-5 or less and a semi-insulating GaAs wafer having a diameter of 15.24 cm (6 inches) or more.

Description

Semi-insulating GaAs wafer and manufacturing method thereof

technical field

The present invention relates to a semi-insulating GaAs wafer and a manufacturing method thereof, and more particularly to ion implantation (ion A semi-insulating GaAs wafer that does not generate slip dislocations in heat treatment such as activation annealing after implantation, and a method for manufacturing the same.

Background technique

As a method for manufacturing semi-insulating GaAs wafers, the usual methods include the LEC method (liquid-enclosed Czochralski method) and the vertical melt method (vertical Bridgman method (VB method), vertical temperature gradient solidification method (VGF method) ) of the two. Next, each method will be described.

A method for producing a GaAs single crystal by the LEC method will be described with reference to FIG. 1 .

A GaAs single crystal production apparatus 1 by the LEC method has a chamber 2 as a furnace body, a Czochralski shaft 3 for Czochralski crystallization, a crucible 5 as a raw material container, and a crucible shaft 4 for receiving the crucible.

In the manufacturing method of the GaAs single crystal adopting the LEC method, first in the crucible 5 (the material of the crucible is usually PBN) as the raw material container, add Ga and As and boron trioxide 6 as the anti-volatile material of As, and put it Place in chamber 2. And, at the front end of the straight pull shaft 3, a seed crystal 7 which will be the base of crystallization is installed. The seed crystal 7 usually has a (100) plane that is in contact with the GaAs melt.

After placing the raw materials in the chamber 2, vacuum the chamber 2 and fill it with inert gas. Then, the resistance heating heater 8 provided in the chamber 2 is energized to raise the temperature in the chamber 2 to synthesize Ga and As to produce GaAs. Then, the temperature is further increased to turn GaAs into a melt, and GaAs melt 9 is produced. Then, rotate the straight pull shaft 3 and the crucible shaft 4 so that the two directions of rotation are opposite. In this state, the seed crystal 7 mounted on the front end of the Czochralski shaft 3 is lowered to contact the GaAs melt 9 . Next, the Czochralski shaft 3 is raised at a given speed while slowly lowering the set temperature of the resistance heating heater 8, so that the crystal diameter gradually becomes thicker from the seed crystal 7 to form a crystal shoulder. After the crystal shoulder is formed, when the target crystal outer diameter is reached, the GaAs single crystal 10 is manufactured under the condition that the outer diameter is kept constant by controlling the shape.

Next, a method for producing a GaAs single crystal by the vertical melt method will be described with reference to FIG. 2 .

A GaAs single crystal manufacturing apparatus 21 of the vertical melt method (VB method, VGF method) has a structure including a chamber 22 serving as a furnace body and a crucible shaft 24 for receiving a crucible 25 serving as a raw material container.

In the method of manufacturing GaAs single crystals using the VB method (or VGF method), first, in the crucible 25 (the crucible is usually made of PBN) as a raw material container, GaAs polycrystals and trioxide as an anti-volatile material for As are added. Boron 26. In addition, a seed crystal 27 to be a base of crystallization is installed in the small-diameter portion at the front end of the crucible 25 . The seed crystal 27 usually has a (100) plane that is in contact with the GaAs melt. They are placed into cavity 22 .

Next, the chamber 22 is evacuated and filled with an inert gas. Then, the resistance heating heater 28 provided in the chamber 22 is energized, and the temperature in the chamber 22 is raised in a state where the temperature gradient is increased from the lower part to the upper part, and the GaAs polycrystal is turned into a molten liquid to form a GaAs molten liquid 29. . Further, the temperature in the furnace is raised until the seed crystal 27 provided at the front end of the crucible 25 comes into contact with the GaAs melt 29 to perform seeding.

Next, in the case of the VB method, the crucible shaft 24 is lowered at a predetermined speed from this state with the set value of the resistance heating heater 28 fixed, and the GaAs melt 29 is solidified from the seed crystal 27 to produce a GaAs single crystal. In the case of the VGF method, the GaAs single crystal is produced by solidifying the GaAs melt 29 from the seed crystal 27 without moving the crucible shaft 24 after seeding, but by lowering the set value of the resistance heating heater 28 at a predetermined rate.

The above-mentioned LEC method and the vertical melt method (VB method, VGF method) each have advantages and disadvantages.

In the case of the LEC method, crystal growth is performed under conditions of a sharp temperature gradient. Therefore, the crystal is easily cooled, which is suitable for high-speed crystal growth and is very advantageous in terms of throughput. However, since it is a crystal grown under a sharp temperature gradient, the in-plane dislocation density of the wafer is higher than that of the VB and VGF methods (the in-plane dislocation density of a wafer with a diameter of Φ15.24 cm (6 inches) is 50,000 ~100,000 pieces/cm ² ). If you add a note, the influence of the dislocation density of the semi-insulating GaAs wafer on the characteristics of electronic devices is still in the research stage, and it cannot be simply concluded that the lower the dislocation density, the better.

On the other hand, in the case of the VB and VGF methods, crystal growth is carried out under mild temperature gradient conditions. Therefore, contrary to the LEC method, it is not suitable for realizing high-speed crystal growth, and is disadvantageous in terms of throughput. However, it is very advantageous for the low dislocation density of the wafer (the in-plane dislocation density of a wafer with a diameter of Φ15.24 cm (6 inches) is about 10,000 dislocations/cm ² ).

However, semi-insulating GaAs wafers are used as substrate materials for electronic devices requiring high-speed operation and low power consumption. The semi-insulating GaAs wafer supplied to electronic device manufacturers as the electronic device substrate is subjected to an annealing treatment (heat treatment) typified by activation annealing after ion implantation in the electronic device manufacturing process.

Ion implantation (ion implantation) is to inject Si ions into the surface of a GaAs wafer, for the purpose of improving the conductivity of the wafer. However, in the ion implantation process, the arrangement of crystal lattices is disturbed, resulting in an insufficient improvement in electrical conductivity. Therefore, activation annealing is performed in order to neatly rearrange the crystal lattice.

This annealing treatment is performed by each electronic device manufacturer under its own conditions, but basically, a method of rapidly raising the temperature to about 500 to 900° C. and then rapidly cooling is generally used.

Regarding the annealing treatment technology, in the past, the LEC method and the vertical melt method (VB method, VGF method) were compared and studied, focusing on the fact that the GaAs crystal wafer manufactured by the vertical melt method has lower dislocation density and lower dislocation density than the LEC method. In view of the fact of residual stress, studies have been conducted on its application to substrates for ion implantation (see JP-A-11-268997). However, in practice, if crystals obtained by the vertical melt method are used at the level of mass production, stable characteristics cannot be obtained compared with conventional GaAs crystals (LEC crystals) obtained by the LEC method. In addition, in the case of GaAs crystals obtained by the vertical melt method, if the same heat treatment as that performed for GaAs crystals (LEC crystals) by the conventional LEC method is performed, especially for diameters greater than or equal to 7.62 cm (3 inches) For large-diameter crystals, the dislocation density and residual stress will increase, and the homogenization mechanism may also be different from that of LEC crystals. Therefore, in Japanese Patent Laid-Open No. 11-268997, by limiting the manufacturing conditions and crystal characteristics of GaAs crystals that can obtain more stable and uniform electrical characteristics, high-quality GaAs wafers that can be used in actual production have been realized, and the optimal heat treatment conditions.

Contents of the invention

The problem of the prior art is that in the manufacturing process of electronic devices using the GaAs crystal obtained by the LEC method or the vertical melt method (VB method, VGF method) described in the prior art as a substrate, the activity after ion implantation In the annealing process, the GaAs wafer after the annealing process will have slip dislocations, which may cause it to be unusable as a product.

The biggest cause of slip dislocations is temperature unevenness in the wafer surface during annealing. At this point, various electronic device manufacturers are improving the annealing method.

However, in recent years, the larger diameter of wafers has been increasing, and the mainstream of GaAs wafers has also developed from the previous size of 10.16 cm (4 inches) in diameter to 15.24 cm (6 inches) in diameter. The control of the temperature uniformity in the wafer surface is required to be more stringent, and has become a bigger problem than before.

From the above-mentioned JP-A-11-268997, the longitudinal melt method (VB method, VGF method) can obtain GaAs crystals with lower dislocation density and lower residual stress than the LEC method, and this is used as a substrate for ion implantation. tried it out.

However, compared with the GaAs crystal (LEC crystal) obtained by the LEC method, the vertical melt method (VB method, VGF method) cannot obtain stable characteristics, and the same heat treatment as the LEC crystal cannot be performed, and it is necessary to re- Study the optimum heat treatment conditions.

Furthermore, the most important point is that "the vertical melt method (VB method, VGF method) has lower crystal residual stress" does not mean that the occurrence of slip dislocations is less immediately. As a result of intensive research efforts by the inventors of the present invention, it has been found that the occurrence of slip dislocations after activation annealing is not due to residual stress alone.

Even in the conventional LEC method, as long as the characteristics of GaAs crystals with a low occurrence rate of slip dislocations can be limited, such as the in-plane dislocation density (EPD value) or residual stress value, ion implantation that can be used in actual production can be realized. Use high quality GaAs wafers as substrates.

Therefore, it is an object of the present invention to solve the above-mentioned problems. For GaAs crystals obtained by the LEC method or the vertical melt method (VB method, VGF method), the in-plane dislocation density of the wafer (EPD value) and residual stress value are limited to a certain range, and a semi-insulating GaAs wafer and a manufacturing method thereof are provided in which slip dislocation does not occur during heat treatment such as activation annealing after ion implantation.

In order to achieve the above object, the semi-insulating GaAs wafer of the present invention is a semi-insulating GaAs wafer with a diameter greater than or equal to 10.16 cm (4 inches), characterized in that the dislocation density (EPD) in the wafer plane is 30,000 pieces/cm ² ~100,000 pieces/cm ² .

Here, it is preferable that the wafer in-plane residual stress value (|Sr-St|) measured by the photoelastic phenomenon of deflection plane rotation according to the magnitude of stress is in the range of 1.8×10 ^-5 or less.

In addition, in order to achieve the above object, the manufacturing method of the semi-insulating GaAs wafer of the present invention, by making the temperature gradient in the crystal during GaAs single crystal growth is 20°C/cm to 150°C/cm, dislocations in the wafer plane The density (EPD) is 30,000 pieces/cm ² to 100,000 pieces/cm ² .

After growing the GaAs single crystal, it is preferable to further anneal the GaAs single crystal.

By setting the maximum attained temperature during the annealing to be 900°C to 1150°C, and to set the temperature gradient in the GaAs single crystal to be 0°C/cm to 12.5°C/cm, the in-plane residual stress value of the wafer (|Sr- St|) is in the range of less than or equal to 1.8×10 ^-5 .

According to the present invention, in the manufacturing process of an electronic device using a semi-insulating GaAs wafer as a substrate, it is possible to significantly reduce product defects caused by sliding dislocations that occur in wafer heat treatment typified by activation annealing after ion implantation In the case of electronic devices, the yield rate in the manufacture of electronic devices is improved.

Description of drawings

FIG. 1 is a schematic diagram of an apparatus for explaining a method of manufacturing a GaAs single crystal by the LEC method.

FIG. 2 is a schematic diagram of an apparatus for explaining a method for producing a GaAs single crystal by a vertical melt method (VB method, VGF method).

Fig. 3 is a schematic diagram showing an experimental furnace for wafer annealing.

Fig. 4 is a graph showing the correlation between the temperature gradient in the crystal and the EPD during crystal growth.

5 is a graph showing the results of measurement of residual stress in the wafer surface when crystals were grown with temperature gradient setting conditions set at 20° C./cm to 150° C./cm without annealing.

In the figure, 1 is the GaAs single crystal manufacturing device by the LEC method; 2 is the cavity; 3 is the Czochralski shaft; 4 is the crucible shaft; 5 is the PBN crucible; 6 is boron trioxide; 9 is GaAs molten liquid; 10 is GaAs single crystal; 14 is wafer annealing experimental furnace; 15 is chamber; 22 is a chamber; 24 is a crucible shaft; 25 is a PBN crucible; 26 is boron trioxide; 27 is a seed crystal; 28 is a resistance heating heater; 29 is GaAs melt.

Detailed ways

In the past, the influence of the dislocation density of semi-insulating GaAs wafers on the characteristics of electronic devices is still in the research stage, and it cannot be simply concluded that the lower the dislocation density, the better.

On this point, as a result of intensive studies, the present inventors have found that, if the residual stress is the same, the more dislocation-rich GaAs crystals are, the more difficult it is for slip dislocations to occur after activation annealing. In other words, if the residual stress is the same, slip dislocations are less likely to occur in crystallized wafers obtained by the LEC method with many dislocations than in crystallized wafers obtained by the vertical melt method (VB method, VGF method).

Therefore, the present invention succeeded in manufacturing a high-quality GaAs wafer that can be practically used for production of ion implantation substrates despite the LEC method by limiting the characteristics of GaAs crystals with a low slip dislocation occurrence rate as described below. That is, on the one hand, the dislocation density in the wafer plane (hereinafter referred to as EPD), which is in the range of 3×10 ⁴ /cm ² ≤ EPD ≤ 1×10 ⁵ /cm ² , and on the other hand, the The residual stress value (|Sr-St|) in the wafer plane obtained by elastic measurement is in the range of 1.8×10 ⁻⁵ or less.

In JP-A-11-268997, the average in-plane dislocation density is 1×10 ⁴ /cm ² or less, and the average residual stress (|Sr-St|) obtained by photoelastic measurement is less than 1×10 ^-5 , and therefore the comparison centering on the dislocation density (EPD) in the wafer plane deviates from the scope of the present invention.

Next, numerical limitations of the present invention will be described in detail.

(Range of EPD in the wafer plane)

In the present invention, the reason why the EPD in the wafer plane is in the range of 3×10 ⁴ pieces/cm ² to 1×10 ⁵ pieces/cm ² is that, as a phenomenon common to all metals, there are dislocations, dislocations The generated portion causes plastic deformation, and the plastic deformation entangles dislocations complexly to cause work hardening. Thereby, resistance to thermal stress applied during annealing becomes stronger, and occurrence of slip dislocations can be reduced. With regard to this work hardening, it has been concluded that an EPD value equal to or greater than 3×10 ⁴ particles/cm ² can be obtained from verification tests. In addition, the reason why the EPD value is 1×10 ⁵ pieces/cm ² or less is that, although work hardening occurs and has the effect of reducing slip dislocations, if the EPD exceeds 1×10 ⁵ pieces/cm ² , the crystallization will be subgrained. Possibilities increase in the world and cannot be used as a product.

(Range of residual stress value (|Sr-St|) in the wafer plane)

In the present invention, the reason why the residual stress value (|Sr-St|) in the wafer plane is less than or equal to 1.8×10 ^-5 is that the inventors have determined the relationship between the residual stress value in the wafer plane and the occurrence of slip dislocations through research in recent years. There is a correlation between them, and it is found that the higher the residual stress value is, the higher the occurrence rate of slip dislocations tends to be. It was also confirmed that when the residual stress value in the wafer surface exceeds a certain value, there is a critical point at which the occurrence rate of slip dislocations immediately increases during annealing. Since this critical point is around |Sr-St|=1.8×10 ^-5 , the residual stress value is set within the above range.

(Measurement method of residual stress value (|Sr-St|) in the wafer surface)

The evaluation method of the residual stress is, for example, the measurement method utilizing the photoelastic phenomenon described in Rev. Sci. Instrum., Vol. To briefly introduce the measurement principle, the wafer is irradiated with infrared light, and the rotation angle of the deflection surface of the transmitted light is detected. Since the rotation angle of the deflection surface is determined by the residual stress of the wafer, it can be measured by detecting the rotation angle. Chip residual stress.

(Definition of residual stress value (|Sr-St|))

Next, the definition of |Sr-St| will be described. The residual stress of the wafer can be calculated from the absolute value |Sr-St| of the difference between the stress Sr in the radial direction and the stress Sr in the tangential direction of the cylinder in cylindrical coordinates. Here, |Sr-St| is defined by the following relational expression.

[Formula 1]

$<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Sr</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; St.</span>}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&lambda;\&delta;</span>}}{\mathrm{<span\; class="notranslate">\; \&pi;</span>}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="dn"\; filenames="C20061000226800191.png,C20061000226800201.png"\; state="\{\{state\}\}">dn</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}^{\mathrm{<span\; class="notranslate">\; 3</span>}}}{<span\; class="notranslate">\; (</span>{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="cos"\; filenames="C20061000226800161.png,C20061000226800171.png"\; state="\{\{state\}\}">cos</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&psi;</span>}}{{\mathrm{<span\; class="notranslate">\; p</span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; p</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="sin"\; filenames="C20061000226800161.png,C20061000226800171.png"\; state="\{\{state\}\}">sin</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&psi;</span>}}{{\mathrm{<span\; class="notranslate">\; p</span>}}_{\mathrm{<span\; class="notranslate">\; 44</span>}}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}$

λ: wavelength of light source

d: Thickness of wafer

n: Refractive index

δ: phase difference caused by the birefringence of the sample

ψ: principal vibration direction angle

p ₁₁ , P ₁₂ , P ₄₄ : Photoelastic constants

By measuring δ and ψ from the above formula, the residual stress |Sr-St| of the wafer can be calculated.

(Range of temperature gradient in crystal when GaAs single crystal is grown)

In the present invention, the temperature gradient in the crystal when growing a GaAs single crystal is set within a range of 20° C./cm to 150° C./cm for the following reasons.

Dislocations generated in crystallization are, on the one hand, affected by thermal stress during crystal growth. It is considered that when the crystal is in a state of thermal stress, that is, when the crystal is in a state with a certain temperature gradient, dislocations will be generated in a direction that can relax the stress. Therefore, the inventors of the present invention controlled the EPD by setting a predetermined temperature gradient in the crystal during crystal growth so that the value of EPD would be within the range of 3×10 ⁴ particles/cm ² to 1×10 ⁵ particles/cm ² described above. value.

Therefore, when determining the optimum range of the temperature gradient in crystallization, two methods of LEC method and VB method (or VGF method) are used to grow GaAs single crystal. In this crystal growth, the setting of temperature gradient in crystallization is changed, Experiments were performed regarding the EPD value at this time.

Fig. 4 shows the correlation between the temperature gradient in the crystallization and the EPD of the obtained crystal.

It can be seen from the figure that when the temperature gradient in the crystal during crystal growth is in the range of 20°C/cm to 150°C/cm, the reproducibility is good, and the EPD satisfies the range of 30,000 pieces/cm ² to 100,000 pieces/cm ² .

Therefore, in the present invention, the temperature gradient range in crystallization when growing a GaAs single crystal for obtaining a semi-insulating GaAs wafer is set at 20° C./cm to 150° C./cm.

(Appropriate range of annealing conditions)

In the present invention, after the crystal growth is carried out according to the temperature gradient during the above-mentioned GaAs single crystal growth, when degeneration is performed, as the annealing condition, the maximum reaching temperature is preferably 900° C. to 1150° C., and the temperature gradient in the crystal during annealing is made The reason is as follows at 0°C/cm to 12.5°C/cm.

As described above, by setting the temperature gradient range in the crystal during GaAs single crystal growth to 20°C/cm to 150°C/cm, the EPD value can be controlled to the above-mentioned 3×10 ⁴ cells/cm ² to 1× 10 ⁵ particles/cm ² , but on the other hand, since thermal stress is applied to the crystal, residual stress occurs in the crystal.

Regarding this point, the inventors of the present invention selected only the number of batches in which the setting conditions of the temperature gradient were set at 20° C./cm to 150° C./cm for the crystals subjected to the experiment shown in FIG. 4 . The wafer in-plane residual stress |Sr-St|

Fig. 5 shows the relationship between the measured wafer in-plane residual stress and the number of batches.

As a result, the average value of |Sr-St| was 1.93×10 ^-5 , and it was difficult to control |Sr-St| ≤ 1.8×10 ^-5 with good reproducibility.

Therefore, as a result of intensive research by the present inventors, it has been found that even for crystals grown by setting the temperature gradient setting conditions at 20°C/cm to 150°C/cm, by performing the above-mentioned annealing after the crystal growth The treatment can also effectively remove the residual stress in the crystal caused by thermal stress, and as a result, the residual stress value in the wafer surface can be controlled within the range of 1.8×10 ^-5 or less.

Regarding the optimization of annealing conditions, referring ^to the measurement results of residual ^{stress in} Fig. 5, prepared For the three samples, the maximum attained temperature during annealing and the temperature gradient in crystallization were used as parameters to measure the change of residual stress in order to grasp the optimal conditions.

Tables 1, 2, and 3 show the values of residual stress |Sr-St| of each sample after annealing.

[Table 1] Changes in residual stress in the wafer plane according to annealing (1)

Sample wafer residual stress value: |Sr-St|=1.9×10 ^-5 case (×10 ^-5 )

Note: The values in the table represent residual stress values |Sr-St|.

[Table 2] Changes in residual stress in the wafer plane according to annealing (2)

Sample wafer residual stress value: |Sr-St|=2.3×10 ^-5 case (×10 ^-5 )

Note: The values in the table represent residual stress values |Sr-St|.

[Table 3] Changes in residual stress in the wafer plane according to annealing (3)

Sample wafer residual stress value: |Sr-St|=1.5×10 ^-5 (×10 ^-5 )

Note: The values in the table represent residual stress values |Sr-St|.

In Tables 1 to 3, gridded columns indicate the annealing conditions under which a reduction in the residual stress value before annealing can be confirmed and |Sr-St| reaches a value equal to or less than 1.8×10 ^-5 . In addition, "unable to measure" in the table means that the temperature of the crystal surface was raised to the melting point of GaAs due to the rapid heating of the furnace used for annealing, and the crystal surface melted, so the measurement was impossible.

From the results in Tables 1 to 3, for all the samples, the relative residual stress value before annealing can be confirmed to be reduced, and the annealing conditions where |Sr-St| can reach a value less than or equal to 1.8×10 ^-5 are 900°C to 1150°C, and the temperature gradient in the crystallization during annealing was 0°C/cm to 12.5°C/cm. Based on the above results, the optimal annealing conditions were determined.

The method of manufacturing a semi-insulating GaAs wafer according to the present invention is characterized in that it is possible to obtain a semi-insulating GaAs wafer in which slip dislocation does not occur during activation annealing after ion implantation, even from a GaAs single crystal produced by the LEC method. Of course, from the GaAs single crystal produced by the vertical melt method (VB method, VGF method), the dislocation density (EPD) in the wafer plane and the residual stress value in the wafer plane (|Sr-St|) can also be obtained at Semi-insulating GaAs wafers within the range specified above. Moreover, the size of the wafer does not necessarily need to be greater than or equal to 15.24 cm (6 inches) in diameter, and a semi-insulating GaAs wafer with a diameter greater than or equal to 10.16 cm (4 inches) is also applicable.

Example

Using a semi-insulating GaAs wafer with a diameter of 15.24 cm (6 inches), two parameters of EPD and residual stress were used to prepare wafers, and an annealing experiment was carried out using these wafers to study the occurrence rate of slip. According to the EPD value, wafers manufactured by the LEC method were used in the range of 30,000 wafers/cm ² to 100,000 wafers/cm ² , and wafers manufactured by the VGF method were used in the range of less than 30,000 wafers/cm ² . In addition, when manufacturing a wafer with an EPD value of 30,000 pieces/cm ² to 100,000 pieces/cm ² by the LEC method, the EPD is adjusted by adjusting the temperature gradient in the crystal during crystal growth to 20°C/cm to 150°C/cm value. And when manufacturing a wafer with an EPD value of less than 30,000 crystals/cm ² by the VGF method, the EPD value is adjusted by adjusting the temperature gradient in the crystal during crystal growth to be less than 20°C/cm. Furthermore, regarding the residual stress value in the wafer surface, according to the residual stress value required for the experiment, after crystal growth, annealing in the above range was performed or annealing was not performed to prepare a wafer sample for the experiment.

Next, the method for producing the GaAs crystal used in the experiment will be described.

First, a GaAs single crystal manufacturing method using the LEC method will be described with reference to FIG. 1 .

A crucible made of PBN was used as the raw material container crucible 5 , and Ga, As, and boron trioxide 6 serving as an anti-volatile material for As were placed in the crucible 5 , and placed in the chamber 2 . The charge weight is Ga: 15,000g, As: 16,500g, boron trioxide 6: 2,000g. And, at the front end of the straight pull shaft 3, a seed crystal 7 which will be the base of crystallization is installed.

After these raw materials are placed in the cavity 2, the cavity 2 is evacuated and filled with inert gas. Then, the resistance heating heater 8 provided in the chamber 2 is energized to raise the temperature in the chamber 2 to synthesize Ga and As to produce GaAs. Then, the temperature is further increased to turn GaAs into a melt, and GaAs melt 9 is produced. Next, rotate the straight pull shaft 3 and the crucible shaft 4 so that the rotation directions are opposite. In this state, the seed crystal 7 mounted on the front end of the straight pull shaft 3 descends until it comes into contact with the GaAs melt 9 . Next, the straight pull shaft 3 is raised at a given speed while slowly lowering the set temperature of the resistance heating heater 8, thereby gradually increasing the crystal diameter from the seed crystal 7 to form a crystal shoulder. After forming the crystal shoulder, when the target crystal outer diameter is reached, the GaAs single crystal 10 is produced under the condition that the outer diameter is kept constant by controlling the shape. Here, in the process of crystal growth from the seed crystal, the GaAs single crystal 10 during crystal growth is adjusted by adjusting the temperature setting value or shape of the resistance heating heater 8, and further by adjusting the structure of parts in the furnace in the chamber 2, and the like. The temperature gradient in the crystallization.

Next, a method for producing a GaAs single crystal by the vertical melt method will be described with reference to FIG. 2 .

A crucible made of PBN was used as the raw material container crucible 25, and in this crucible 25, boron trioxide 26 serving as a GaAs polycrystal and an anti-volatile material of As was charged. Wherein, the charging weight is, GaAs polycrystalline: 20,000g, boron trioxide 26: 2,000g. In addition, at the front end of the crucible 25, a seed crystal 27 to be a base of crystallization is installed. These are placed into cavity 22 . Next, the chamber 22 is evacuated and filled with an inert gas. Then, the resistance heating heater 28 provided in the chamber 22 is energized, and the temperature in the chamber 22 is raised in a state where the temperature rises from the lower part to the upper part so that the temperature gradient is set, and the GaAs polycrystal is turned into a molten liquid to form a GaAs molten liquid. 29. However, in this experiment, the temperature gradient in the furnace was set to be equal to or less than 20° C./cm to carry out crystal growth. Next, the temperature in the furnace is raised until the seed crystal 27 placed at the front end of the crucible 25 comes into contact with the GaAs melt 29 to perform seeding. Next, the GaAs melt 29 is solidified from the seed crystal 27 by lowering the set value of the resistance heating heater 28 at a predetermined rate, thereby producing a GaAs single crystal.

GaAs single crystals obtained by the above two crystal production methods were sliced, edged, and polished to prepare GaAs wafers.

Next, the annealing experiment was carried out using the wafer annealing experimental furnace 14 shown in FIG. 3 . The experimental wafer annealing furnace 14 has a wafer arrangement plate 16 in a chamber 15, and a GaAs wafer 18 is arranged thereon. In addition, a three-zone structure heater 17 having three heating zones in the lateral direction is disposed below the wafer arrangement plate 16 . Each region of the three-region structure heater 17 is arranged so as to be located at both ends and the center of the GaAs wafer 18, and the temperature distribution in the wafer surface can be freely adjusted by adjusting the set temperature of the heater in these three regions.

In this experiment, the temperature of the wafer annealing experimental furnace 14 was set to be 850° C. at the center of the wafer and 830° C. at both ends of the wafer, so that the temperature difference between the center and both ends of the wafer surface was 20° C. . And, the time to reach the temperature set point was set at 30 minutes, kept for 5 minutes after the temperature was reached, and then cooled to normal temperature over 1 hour.

Under this temperature condition, take the EPD and the residual stress value as parameters, and prepare the combined wafers for the experiment. Specifically, the in-plane EPD value of the prepared wafer is 0.8, 1, 3, 5, 8, 10 (×10 ⁴ pieces/cm ² ), and the residual stress value (|Sr-St|) in the wafer plane is 0.9-2.0 (× 10 ^-5 ) A wafer of this combination was used for experiments. In this experiment, 10 wafers were prepared for each combination of EPD and residual stress value, and experiments were performed to study the occurrence rate of slip dislocations at this time. The results are shown in Table 4.

[Table 4] Slip occurrence rate according to annealing

Notes: ① The numerical values in the table are the values of the occurrence rate of slippage (%).

②The residual stress value in the wafer plane is the |Sr-St| value obtained from the photoelastic measurement.

From the above results in Table 4, it can be clearly known that when the EPD value in the wafer plane is in the range of 30,000 pieces/cm ² to 100,000 pieces/cm ² , and the residual stress value |Sr-St| in the wafer plane is less than or equal to 1.8 In the range of ×10 ^-5 (the area with grids in Table 4), the occurrence rate of slip dislocations is only 20% at most, and the results show the effectiveness of the present invention.

Claims (1)

1. A method of manufacturing a semi-insulating GaAs wafer, characterized in that the dislocation density in the wafer plane is set to 30,000 by setting the temperature gradient in the crystal during GaAs single crystal growth to 20°C/cm to 150°C/cm /cm ² to 100,000 pieces/cm ² , after growing the GaAs single crystal, annealing is further performed on the GaAs single crystal. When the temperature gradient in the GaAs single crystal is 0°C/cm to 12.5°C/cm, the residual stress value in the wafer plane is less than or equal to the range of 1.8×10 ^-5 .

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