CN100395887C - Integrated circuit packaging structure and manufacturing method thereof - Google Patents
Integrated circuit packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN100395887C CN100395887C CNB2004100511573A CN200410051157A CN100395887C CN 100395887 C CN100395887 C CN 100395887C CN B2004100511573 A CNB2004100511573 A CN B2004100511573A CN 200410051157 A CN200410051157 A CN 200410051157A CN 100395887 C CN100395887 C CN 100395887C
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- heat sink
- integrated
- carbon nanotube
- nanotube array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【技术领域】 【Technical field】
本发明涉及一种集成电路封装结构及其制造方法,尤其涉及一种应用碳纳米管阵列导热的集成电路封装结构及其制造方法。The invention relates to an integrated circuit packaging structure and a manufacturing method thereof, in particular to an integrated circuit packaging structure using a carbon nanotube array for heat conduction and a manufacturing method thereof.
【背景技术】 【Background technique】
在半导体集成电路的封装领域,随着半导体集成电路不断在改进、发展,其在功能上不断提高的同时体积不断减小,密集程度不断增加,封装尺寸亦在不断变小。由于集成电路芯片工作时是在如此小的空间内进行运算处理,必将产生相当大的热量。所产生的热量必须通过适当的方式散出,以避免集成电路芯片因过热导致运算处理错误,严重时会造成硬件电路的损毁。因此,封装中的散热问题就越发关键。In the field of packaging of semiconductor integrated circuits, with the continuous improvement and development of semiconductor integrated circuits, their functions continue to increase while their volumes continue to decrease, their density continues to increase, and their packaging sizes continue to decrease. Since the integrated circuit chip performs calculation and processing in such a small space when it is working, it will inevitably generate a considerable amount of heat. The generated heat must be dissipated in an appropriate way to avoid calculation and processing errors due to overheating of the integrated circuit chip, and in severe cases, damage to the hardware circuit will be caused. Therefore, the heat dissipation problem in the package becomes more and more critical.
传统的封装方式由于塑封料的导热系数不高,集成电路芯片产生的热量不能实时散发出去,导致芯片温度容易过高,降低了芯片能够支持的功率。为了解决该问题,请参阅图1所示,最初的方法是在基板3上粘结一散热片5,然后再用塑封胶7将芯片2、金线4、散热片5等塑封起来。散热片5位于芯片2上方,其上表面暴露于空气中,用于将芯片2产生的热量进行发散,防止芯片2温度过高。然而,其芯片2产生的热量需通过塑封胶体7的传导方能到达散热片5,再将热能散发掉。但由于塑封胶体7为不良导热体,致使其散热效果有限。In the traditional packaging method, due to the low thermal conductivity of the plastic packaging compound, the heat generated by the integrated circuit chip cannot be dissipated in real time, resulting in excessively high chip temperature and reducing the power that the chip can support. In order to solve this problem, as shown in FIG. 1 , the initial method is to bond a
随着热界面材料的出现以及半导体封装工艺的发展,人们将热界面材料与半导体封装工艺相结合得到了更好的散热效果。请参阅图2,热界面材料6置于芯片2顶面与散热片5内部表面之间。集成电路工作时,芯片2所产生的热量可由直接与其相接触的热界面材料6传递至散热片5内部表面,被散热片5吸收,并藉由散热片5外部的其它散热装置将热量散发掉。然而,该种应用热界面材料的半导体集成电路封装方法受到热界面材料本身热传导能力的制约。With the emergence of thermal interface materials and the development of semiconductor packaging technology, people combine thermal interface materials with semiconductor packaging technology to obtain better heat dissipation effects. Referring to FIG. 2 , the thermal interface material 6 is placed between the top surface of the
为改善热界面材料的性能,提高其热传导系数,各种材料被广泛试验。Savas Berber等人于2000年在美国物理学会上发表一篇名为“Unusually HighThermal Conductivity of Carbon Nanotubes”的文章指出,“Z”形(10,10)碳纳米管于室温下导热系数可达6600W/mK,具体内容可参阅文献Phys.Rev.Lett(2000),Vol.84,P.4613。研究如何将碳纳米管用于热界面材料并充分发挥其优良的导热性成为提高热界面材料性能的一个重要方向。In order to improve the performance of thermal interface materials and increase their thermal conductivity, various materials have been extensively tested. Savas Berber and others published an article titled "Unusually High Thermal Conductivity of Carbon Nanotubes" on the American Physical Society in 2000, pointing out that the thermal conductivity of "Z"-shaped (10,10) carbon nanotubes at room temperature can reach 6600W/ mK, for details, please refer to the literature Phys. Rev. Lett (2000), Vol.84, P.4613. Research on how to use carbon nanotubes in thermal interface materials and give full play to their excellent thermal conductivity has become an important direction to improve the performance of thermal interface materials.
美国专利第6,407,922号揭示一种利用碳纳米管导热的热界面材料,其将碳纳米管掺到银胶基体结成一体,通过注模方式制得热界面材料。该热界面材料的两导热表面的面积不等,其中与散热器接触一面的面积大于与热源接触一面的面积,该热界面材料应用于半导体封装能够提高其散热能力。但是,该方法制得的热界面材料有不足之处,其一,注模方式制得热界面材料厚度较大,虽该热界面材料的导热系数较高,但该热界面材料体积的增加,与器件向小型化方向发展的趋势不相适应,且该热界面材料缺乏柔韧性;其二,碳纳米管在基体材料中未有序排列,其在基体中分布的均匀性较难确保,因而热传导的均匀性亦受到影响,碳纳米管纵向导热的优势未充分利用,影响热界面材料的热传导系数。US Patent No. 6,407,922 discloses a thermal interface material utilizing carbon nanotubes for heat conduction, which incorporates carbon nanotubes into a silver colloidal matrix and integrates the thermal interface material by injection molding. The two heat conduction surfaces of the thermal interface material have different areas, and the area of the side contacting the heat sink is greater than the area of the side contacting the heat source. The application of the thermal interface material to the semiconductor package can improve its heat dissipation capability. However, the thermal interface material produced by this method has disadvantages. First, the thickness of the thermal interface material produced by injection molding is relatively large. Although the thermal conductivity of the thermal interface material is high, the volume of the thermal interface material increases. It is not compatible with the trend of device miniaturization, and the thermal interface material lacks flexibility; secondly, the carbon nanotubes are not arranged in an orderly manner in the matrix material, and it is difficult to ensure the uniformity of their distribution in the matrix, so The uniformity of heat conduction is also affected, and the advantage of longitudinal heat conduction of carbon nanotubes is not fully utilized, which affects the thermal conductivity of thermal interface materials.
2004年1月8日公开的美国专利申请第20040005736号揭示一种基于碳纳米管阵列的热界面材料,以及包括该热界面材料的半导体封装结构,其将热界面材料在封装时置于集成散热片(Integrated Heat Spreader,IHS)与集成电路芯片(DIE)之间,或者置于集成电路芯片与散热器(Heat Sink)之间。其中,该热界面材料是包括混合有聚合物基体材料的碳纳米管阵列,碳纳米管于聚合物基体材料中均匀分布有序排列,能够避免由于碳纳米管的无序排列而影响热界面材料的导热性,同时,碳纳米管阵列基本垂直于并延伸出热界面材料的接触表面,确保碳纳米管能直接与集成电路芯片或散热器件相接触。但是,基于该热界面材料的半导体封装结构有不足之处,其一,由于聚合物基体材料的导热性能不佳,因此,将碳纳米管与聚合物基体混合形成的热界面材料不能充分发挥碳纳米管的导热性能,且该热界面材料于应用时会由于芯片的不均匀发热导致热传导的不均匀性,进而影响整个热界面材料的热传导效率以及热传导的稳定性,更进一步地影响该封装结构的散热效果;其二,上述半导体封装结构中混合碳纳米管阵列于聚合物基体的热界面材料是形成于集成电路芯片(DIE)上,由于集成电路芯片不能承受形成碳纳米管阵列所需的高温,故需要预先形成该碳纳米管阵列热界面材料于基板上,再于该基板上制作集成电路芯片,制作与封装过程较为复杂,不利于推广应用。U.S. Patent Application No. 20040005736 published on January 8, 2004 discloses a thermal interface material based on carbon nanotube arrays, and a semiconductor package structure including the thermal interface material, which puts the thermal interface material in the integrated heat dissipation during packaging Between the integrated heat spreader (Integrated Heat Spreader, IHS) and the integrated circuit chip (DIE), or between the integrated circuit chip and the heat sink (Heat Sink). Wherein, the thermal interface material is a carbon nanotube array mixed with a polymer matrix material, and the carbon nanotubes are uniformly distributed and arranged in the polymer matrix material, which can avoid affecting the thermal interface material due to the disordered arrangement of the carbon nanotubes. At the same time, the carbon nanotube array is basically perpendicular to and extends out of the contact surface of the thermal interface material, ensuring that the carbon nanotubes can directly contact the integrated circuit chip or heat dissipation device. However, the semiconductor packaging structure based on this thermal interface material has disadvantages. First, due to the poor thermal conductivity of the polymer matrix material, the thermal interface material formed by mixing carbon nanotubes with the polymer matrix cannot fully utilize the carbon nanotubes. The thermal conductivity of nanotubes, and the thermal interface material will cause uneven heat conduction due to the uneven heating of the chip during application, which will affect the thermal conduction efficiency and stability of the entire thermal interface material, and further affect the packaging structure. second, the thermal interface material that mixes the carbon nanotube array in the polymer matrix in the above-mentioned semiconductor packaging structure is formed on the integrated circuit chip (DIE), because the integrated circuit chip cannot withstand the required heat for forming the carbon nanotube array. Due to the high temperature, it is necessary to form the carbon nanotube array thermal interface material on the substrate in advance, and then fabricate the integrated circuit chip on the substrate. The manufacturing and packaging process is relatively complicated, which is not conducive to popularization and application.
因此,提供一种能充分发挥碳纳米管的热传导性能,散热效果好,制作简单的集成电路封装结构及其该封装结构的制造方法十分必要。Therefore, it is very necessary to provide an integrated circuit packaging structure that can fully utilize the thermal conductivity of carbon nanotubes, has a good heat dissipation effect, and is easy to manufacture, and a manufacturing method of the packaging structure.
【发明内容】 【Content of invention】
为解决现有技术的技术问题,本发明的目的是提供一种能充分发挥碳纳米管的热传导性能,散热效果好,制作简单的集成电路封装结构。。In order to solve the technical problems of the prior art, the purpose of the present invention is to provide an integrated circuit packaging structure that can fully utilize the heat conduction performance of carbon nanotubes, has good heat dissipation effect, and is easy to manufacture. .
本发明的另一目的是提供此种集成电路封装结构的制造方法。Another object of the present invention is to provide a method for manufacturing such an integrated circuit package structure.
为实现本发明的目的,本发明提供一种集成电路封装结构,其包括:一基板;一集成电路芯片设置于基板上;一集成散热片置于集成电路芯片上方,其边缘下端固定于基板上,该集成散热片包括一内表面及一外表面;及一碳纳米管阵列设置于上述集成电路芯片与散热器件之间;其中,该碳纳米管阵列是形成于集成散热片的内表面,其两端分别与集成散热片及集成电路芯片垂直接触。In order to achieve the purpose of the present invention, the present invention provides an integrated circuit packaging structure, which includes: a substrate; an integrated circuit chip is arranged on the substrate; an integrated heat sink is placed above the integrated circuit chip, and the lower end of its edge is fixed on the substrate , the integrated heat sink includes an inner surface and an outer surface; and a carbon nanotube array is arranged between the above-mentioned integrated circuit chip and the heat dissipation device; wherein, the carbon nanotube array is formed on the inner surface of the integrated heat sink, its The two ends are in vertical contact with the integrated heat sink and the integrated circuit chip respectively.
本发明的集成电路封装结构中,该碳纳米管中填充有高热传导系数的纳米金属材料。In the integrated circuit packaging structure of the present invention, the carbon nanotubes are filled with nano metal materials with high thermal conductivity.
该集成电路封装结构可进一步包括一碳纳米管阵列形成于集成散热片的外表面,应用时,该碳纳米管两端分别与集成散热片及外接散热装置垂直接触。该碳纳米管阵列同样可为管中填充有高热传导系数的纳米金属材料的碳纳米管阵列。The integrated circuit packaging structure may further include a carbon nanotube array formed on the outer surface of the integrated heat sink. When applied, the two ends of the carbon nanotube are in vertical contact with the integrated heat sink and the external heat sink respectively. The carbon nanotube array can also be a carbon nanotube array filled with nano metal materials with high thermal conductivity in the tube.
为实现本发明的另一目的,本发明还提供此种集成电路封装结构的制造方法,包括以下步骤:To achieve another object of the present invention, the present invention also provides a method for manufacturing such an integrated circuit packaging structure, comprising the following steps:
提供一基板,其包括两相对表面;providing a substrate comprising two opposing surfaces;
提供一集成电路芯片并将该芯片粘接于基板的一表面上,再通过金线将集成电路芯片与基板上的电路进行电性连接;Provide an integrated circuit chip and bond the chip on a surface of the substrate, and then electrically connect the integrated circuit chip and the circuit on the substrate through gold wires;
提供一集成散热片,其包括一内表面与一相对的外表面;providing an integrated heat sink including an inner surface and an opposite outer surface;
通过化学方法在集成散热片的内表面生长碳纳米管阵列;Growing carbon nanotube arrays on the inner surface of the integrated heat sink by chemical methods;
将集成散热片固定于基板上,使碳纳米管阵列位于集成散热片与集成电路芯片之间,并与集成电路芯片直接垂直接触;Fixing the integrated heat sink on the substrate, so that the carbon nanotube array is located between the integrated heat sink and the integrated circuit chip, and is in direct vertical contact with the integrated circuit chip;
在基板、集成电路芯片、集成散热片上做封胶材料的设置;Set the sealing material on the substrate, integrated circuit chip, and integrated heat sink;
在基板相对于芯片的另一表面上焊贴锡球。Solder balls on the other surface of the substrate opposite to the chip.
其中,本发明中碳纳米管阵列的生长方法包括以下步骤:Wherein, the growth method of carbon nanotube array in the present invention comprises the following steps:
抛光欲生长碳纳米管阵列的集成散热片的表面;Polishing the surface of the integrated heat sink where the carbon nanotube array is to be grown;
在该集成散热片表面沉积催化剂;Depositing a catalyst on the surface of the integrated heat sink;
通入碳源气,在集成散热片的表面生长碳纳米管阵列。The carbon source gas is introduced, and the carbon nanotube array is grown on the surface of the integrated heat sink.
本发明的集成电路封装结构的制造方法中,该碳纳米管阵列进一步包括管中填充有高热传导系数的纳米金属材料的碳纳米管阵列。In the manufacturing method of the integrated circuit packaging structure of the present invention, the carbon nanotube array further includes a carbon nanotube array filled with nano-metal materials with high thermal conductivity.
本发明填充有纳米金属材料的碳纳米管阵列的形成方法包括以下步骤:The forming method of the carbon nanotube array filled with nano metal material of the present invention comprises the following steps:
在需生长碳纳米管阵列的散热片表面布上一规则图案化的催化剂层;A regularly patterned catalyst layer is spread on the surface of the heat sink where the carbon nanotube array needs to be grown;
以激光蒸发法(Laser Ablation)将含金属元素的石墨棒以高能激光瞬间气化;Using laser evaporation (Laser Ablation) to instantly gasify graphite rods containing metal elements with high-energy lasers;
在500Torr的氩气气氛下以流动的氩气将气化的碳基金属蒸气传送至已布有催化剂的散热片表面;Under the argon atmosphere of 500 Torr, the vaporized carbon-based metal vapor is transferred to the surface of the heat sink with the catalyst distributed by flowing argon;
冷却得到填充有纳米金属材料的碳纳米管阵列。After cooling, a carbon nanotube array filled with nano metal material is obtained.
与现有技术相比较,本发明基于碳纳米管阵列导热的集成电路封装结构具以下优点:其一,碳纳米管阵列是封装以前直接生长于集成散热片表面,方法简单,且可避免生长时对集成电路芯片的影响;其二,应用时该碳纳米管阵列能够直接与集成散热片及集成电路芯片接触,或与外接散热装置直接垂直相接触,形成多个导热信道,能够极好地发挥碳纳米管的优异导热性能;其三,碳纳米管中填充有纳米金属材料,在热源发热不均匀亦时能够提供均匀散热,因而能够有效地改善其热传导的效率以及热传导的稳定性。Compared with the prior art, the present invention has the following advantages based on the thermal conductivity of the carbon nanotube array integrated circuit packaging structure: First, the carbon nanotube array is directly grown on the surface of the integrated heat sink before packaging, the method is simple, and it can avoid the growth time. The impact on the integrated circuit chip; second, the carbon nanotube array can be directly in contact with the integrated heat sink and the integrated circuit chip during application, or directly and vertically contact with the external heat sink, forming multiple heat conduction channels, which can play an excellent role. The excellent thermal conductivity of carbon nanotubes; third, carbon nanotubes are filled with nano-metal materials, which can provide uniform heat dissipation when the heat source generates heat unevenly, thus effectively improving the efficiency and stability of heat conduction.
【附图说明】 【Description of drawings】
图1是现有技术的半导体集成电路封装结构的示意图。FIG. 1 is a schematic diagram of a semiconductor integrated circuit packaging structure in the prior art.
图2是现有技术的封装有散热片半导体集成电路封装结构的示意图。FIG. 2 is a schematic diagram of a package structure of a semiconductor integrated circuit packaged with a heat sink in the prior art.
图3是本发明集成电路封装结构的第一实施方式的示意图。FIG. 3 is a schematic diagram of the first embodiment of the integrated circuit packaging structure of the present invention.
图4是第三图的局部放大示意图。Fig. 4 is a partially enlarged schematic diagram of the third diagram.
图5是本发明集成电路封装结构的第二实施方式的示意图。FIG. 5 is a schematic diagram of a second embodiment of the integrated circuit packaging structure of the present invention.
图6是本发明集成电路封装结构的制造方法的流程示意图。FIG. 6 is a schematic flow chart of the manufacturing method of the integrated circuit packaging structure of the present invention.
【具体实施方式】 【Detailed ways】
下面将结合附图及具体实施例对本发明进行详细说明。The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.
请参阅图3与图4,本发明提供一种集成电路封装结构10,其包括:一基板11;一集成电路芯片(DIE)12粘结于基板11上,并通过金线121与基板电性连接;一集成散热片(Integrated Heat Spreader,IHS)13设置于集成电路芯片12上方,该集成散热片13包括一内表面及一外表面,其边缘下端131粘接于基板11之上,该集成散热片起到密封与保护集成电路芯片12的作用,同时,集成散热片13边缘下端131通过电路与基板11地极电性相连,起到静电屏蔽的作用;一碳纳米管阵列14形成于集成散热片13的内表面,该碳纳米管阵列14包括多个分布均匀且彼此平行的碳纳米管141,该碳纳米管141两端分别与集成电路芯片12及集成散热片13垂直接触,构成多个导热信道。其中,该碳纳米管阵列14是直接生长于集成散热片13上,相当于一层热界面材料。碳纳米管阵列14的高度可通过控制其生长时间来控制,本发明碳纳米管阵列14的高度为0.01~0.1毫米。优选地,本发明形成的碳纳米管141中皆填充有高热导率的纳米金属材料,应用时能够更好地提高其热传导的效率,显著改善热传导的稳定性,本发明的纳米金属材料包括纳米铜材料。另外,本发明基板11可通过连接器16与主机板17电性连接,从而可以完成与主机板17上其它电子组件连接的功能。Referring to Fig. 3 and Fig. 4, the present invention provides a kind of integrated
请参阅图5,为了取得更好地散热效果,在实际应用中,可以进一步在集成散热片13的外表面以同样的方法形成一碳纳米管阵列15,藉此将从集成电路芯片12传递至集成散热片13上的热量更好地传递给外接散热器18并迅速发散,从而有效地降低集成电路芯片12的工作温度。本实施方式的外接散热器18选自鳍片式散热器。Please refer to Fig. 5, in order to obtain better heat dissipation effect, in practical application, can further form a
请参阅图6,本发明集成电路封装结构的制造方法包括如下步骤:Please refer to FIG. 6, the manufacturing method of the integrated circuit packaging structure of the present invention includes the following steps:
步骤100是提供一基板,其包括两相对表面;Step 100 is providing a substrate comprising two opposite surfaces;
步骤200是提供一集成电路芯片并将该芯片粘接于基板的一表面上,再通过金线将集成电路芯片与基板上的电路形成电性连接;Step 200 is providing an integrated circuit chip and bonding the chip on a surface of the substrate, and then electrically connecting the integrated circuit chip and the circuit on the substrate through gold wires;
步骤300,提供一集成散热片,其包括一内表面与一相对的外表面,该散热片的材料包括金属铜;
步骤400,通过化学方法在集成散热片的内表面生长碳纳米管阵列,该碳纳米管阵列的厚度为0.01~0.1毫米;
步骤500,将集成散热片固定于基板上,使碳纳米管阵列位于集成散热片与集成电路芯片之间,并与集成电路芯片直接垂直接触,同时,该集成散热片与基板电性相连以起到静电屏蔽的作用;
步骤600,在基板、集成电路芯片、集成散热片上做封胶材料的设置,其中封胶设置的方法包括压模法(Transfer,Molding)、点胶(Dispensing)及真空印刷法(Vacuum Printing);
步骤700,在基板相对于芯片的另一表面上焊贴锡球,以连接连接器,并通过连接器与主机板电性相连。In
其中,本发明可进一步生长碳纳米管阵列于散热片的外表面,应用时,使得该碳纳米管阵列位于散热片与外接散热器之间,有利于热量更好地传递。Wherein, the present invention can further grow the carbon nanotube array on the outer surface of the heat sink. When applied, the carbon nanotube array is located between the heat sink and the external heat sink, which is conducive to better heat transfer.
优选地,本发明形成的碳纳米管阵列包括填充有高热导率纳米金属材料的碳纳米管阵列,本实施方式的纳米金属材料选自纳米铜材料。Preferably, the carbon nanotube array formed in the present invention includes a carbon nanotube array filled with a high thermal conductivity nano-metal material, and the nano-metal material in this embodiment is selected from nano-copper materials.
本发明生长碳纳米管阵列于散热片的方法包括以下步骤:The method for growing a carbon nanotube array on a heat sink of the present invention comprises the following steps:
首先,在散热片的表面作一化学机械研磨抛光处理(Chemical MechanicalPolish,CMP),使其表面粗糙度降低至5~10埃,并洗净该表面;First, do a chemical mechanical polishing (CMP) on the surface of the heat sink to reduce the surface roughness to 5-10 angstroms, and clean the surface;
其次,在已处理的散热片的表面沉积一催化剂层,催化剂层的厚度为5~30纳米,催化剂层沉积的方法可选用真空热蒸镀挥发法,亦可选用电子束蒸发法。催化剂的材料可选用铁、钴、镍或其合金,本实施方式选用铁作为催化剂材料,其沉积的厚度为10纳米;Secondly, a catalyst layer is deposited on the surface of the treated heat sink. The thickness of the catalyst layer is 5-30 nanometers. The method of deposition of the catalyst layer can be vacuum thermal evaporation evaporation method or electron beam evaporation method. The material of the catalyst can be iron, cobalt, nickel or their alloys. In this embodiment, iron is selected as the catalyst material, and the thickness of its deposition is 10 nanometers;
最后,将带有催化剂层的散热器置于空气中,在300℃下退火,以使催化剂层氧化、收缩成为纳米级的催化剂颗粒。待退火完毕,再将分布有催化剂颗粒的散热片的表面置于反应室内,通入碳源气乙炔,利用低温热化学气相沉积法,在上述催化剂颗粒上生长碳纳米管,形成碳纳米管薄膜,碳源气亦可选用其它含碳的气体,如乙烯等。当前,碳纳米管阵列的生长方法已较为成熟,具体可参阅文献Science,1999,283,512-414与文献J.Am.Chem.Soc,2001,123,11502-11503。本发明碳纳米管阵列的高度为0.01~0.1毫米,本实施方式生长的碳纳米管的直径为20纳米,高度为50微米,间距为100纳米。Finally, place the heat sink with the catalyst layer in the air and anneal at 300°C to oxidize and shrink the catalyst layer into nanoscale catalyst particles. After the annealing is completed, place the surface of the heat sink with the catalyst particles in the reaction chamber, pass through the carbon source gas acetylene, and use the low-temperature thermal chemical vapor deposition method to grow carbon nanotubes on the catalyst particles to form a carbon nanotube film , The carbon source gas can also choose other carbon-containing gases, such as ethylene. At present, the growth method of carbon nanotube arrays is relatively mature. For details, please refer to the literature Science, 1999, 283, 512-414 and the literature J.Am.Chem.Soc, 2001, 123, 11502-11503. The height of the carbon nanotube array of the present invention is 0.01-0.1 millimeters, and the diameter of the carbon nanotubes grown in this embodiment is 20 nanometers, the height is 50 micrometers, and the spacing is 100 nanometers.
本发明的优选方式中,生长填充有纳米金属铜材料的碳纳米管阵列的方法包括以下步骤:In a preferred mode of the present invention, the method for growing a carbon nanotube array filled with nano-metallic copper material comprises the following steps:
首先,在需生长碳纳米管阵列的散热片表面作一化学机械研磨抛光处理(Chemical Mechanical Polish,CMP),使其表面粗糙度降低至5~10埃,并于已处理的散热片的表面布上一规则图案化的催化剂层,具体方法为先按照预定图案依次通过软烘、曝光、显影布上光阻,再以真空溅镀或挥发镀膜法布上催化剂。催化剂的材料可选用铁、钴、镍或其合金,本实施方式选用铁作为催化剂材料,其沉积的厚度为10纳米;First, do a chemical mechanical polishing (Chemical Mechanical Polish, CMP) on the surface of the heat sink where the carbon nanotube array needs to be grown to reduce the surface roughness to 5-10 angstroms, and spread the surface of the treated heat sink The catalyst layer patterned by the previous rule, the specific method is to firstly spread the photoresist through soft drying, exposure and development according to the predetermined pattern, and then spread the catalyst by vacuum sputtering or volatilization coating method. The material of the catalyst can be iron, cobalt, nickel or their alloys. In this embodiment, iron is selected as the catalyst material, and the thickness of its deposition is 10 nanometers;
其次,以激光蒸发法(Laser Ablation)将含金属元素的石墨棒以高能激光瞬间气化,其中,高能激光选自掺钕钇铝石榴石激光(Nd YAG Laser),本实施方式的金属元素选自金属铜;Secondly, the graphite rod containing the metal element is vaporized instantly with a high-energy laser by laser evaporation method (Laser Ablation), wherein the high-energy laser is selected from the Nd YAG Laser (Nd YAG Laser), and the metal element selected in this embodiment from metallic copper;
再次,在500Torr的氩气气氛下以流动的氩气将气化的碳基金属蒸气传送至已布有催化剂的散热片表面,其中,金属元素的含量不少于1%;Thirdly, under the argon atmosphere of 500 Torr, the vaporized carbon-based metal vapor is transferred to the surface of the heat sink on which the catalyst has been distributed with flowing argon gas, wherein the content of the metal element is not less than 1%;
最后,冷却得到填充有金属材料的碳纳米管阵列。Finally, cooling yields carbon nanotube arrays filled with metallic materials.
本发明的集成电路封装结构于应用时,由于碳纳米管是与散热片及集成电路芯片直接接触,进一步地,当碳纳米管阵列设置于散热片与外接散热装置之间时,该碳纳米管与散热片及外接散热装置直接接触,因而能够充分发挥碳纳米管的优异导热性能,能够很好地将集成电路芯片散发出来的热量传递给集成散热片并通过外接散热装置迅速发散,具有优异的散热效果。另外,由于碳纳米管中填充有纳米金属材料,可进一步改善热传导效率以及热传导的稳定性。When the integrated circuit packaging structure of the present invention is applied, since the carbon nanotubes are in direct contact with the heat sink and the integrated circuit chip, further, when the carbon nanotube array is arranged between the heat sink and the external heat sink, the carbon nanotubes It is in direct contact with the heat sink and the external heat sink, so it can give full play to the excellent thermal conductivity of carbon nanotubes, and can well transfer the heat emitted by the integrated circuit chip to the integrated heat sink and quickly dissipate it through the external heat sink. heat radiation. In addition, since the carbon nanotubes are filled with nano-metal materials, the heat conduction efficiency and heat conduction stability can be further improved.
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2004100511573A CN100395887C (en) | 2004-08-14 | 2004-08-14 | Integrated circuit packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2004100511573A CN100395887C (en) | 2004-08-14 | 2004-08-14 | Integrated circuit packaging structure and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1734754A CN1734754A (en) | 2006-02-15 |
CN100395887C true CN100395887C (en) | 2008-06-18 |
Family
ID=36077054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100511573A Expired - Fee Related CN100395887C (en) | 2004-08-14 | 2004-08-14 | Integrated circuit packaging structure and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN100395887C (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102280418A (en) * | 2010-06-09 | 2011-12-14 | 海力士半导体有限公司 | Semiconductor package with heat dissipation devices |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101471329B (en) * | 2007-12-29 | 2012-06-20 | 清华大学 | Semiconductor encapsulation part |
WO2009107229A1 (en) * | 2008-02-29 | 2009-09-03 | 富士通株式会社 | Sheet structure, semiconductor device and method of growing carbon structure |
CN101668383B (en) * | 2008-09-03 | 2013-03-06 | 富葵精密组件(深圳)有限公司 | Circuit board and circuit board package structure |
KR101328353B1 (en) * | 2009-02-17 | 2013-11-11 | (주)엘지하우시스 | Heating sheet using carbon nano tube |
CN102446876A (en) * | 2010-10-11 | 2012-05-09 | 叶福霖 | Heat sink device |
TWI442014B (en) * | 2010-11-24 | 2014-06-21 | Ind Tech Res Inst | Heat dissipating component and heat dissipating component processing method |
CN103730310B (en) * | 2012-10-12 | 2015-11-25 | 上海联影医疗科技有限公司 | A kind of X-ray tube |
CN103117356A (en) * | 2013-02-28 | 2013-05-22 | 华北电力大学 | Carbon nanometer tube array based chip radiating method |
CN108024392B (en) * | 2018-01-04 | 2024-01-12 | 承德福仁堂保健咨询服务有限公司 | Device for heating stone material from inside by adopting semiconductor chip |
CN111023323B (en) * | 2019-12-18 | 2024-09-24 | 珠海格力电器股份有限公司 | Heat radiation structure and air conditioner outdoor unit with same |
CN111696925A (en) * | 2020-05-18 | 2020-09-22 | 马鞍山芯海科技有限公司 | Chip packaging structure and method |
CN114613266A (en) * | 2022-03-07 | 2022-06-10 | 深圳市华星光电半导体显示技术有限公司 | Display module and display device |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6407922B1 (en) * | 2000-09-29 | 2002-06-18 | Intel Corporation | Heat spreader, electronic package including the heat spreader, and methods of manufacturing the heat spreader |
US20030173338A1 (en) * | 2001-11-21 | 2003-09-18 | Vallance Robert Ryan | Processes for nanomachining using carbon nanotubes |
US20040005736A1 (en) * | 2002-07-02 | 2004-01-08 | Intel Corporation | Method and apparatus using nanotubes for cooling and grounding die |
CN1483668A (en) * | 2002-09-17 | 2004-03-24 | 清华大学 | A method for growing carbon nanotube arrays |
CN1501483A (en) * | 2002-11-14 | 2004-06-02 | 清华大学 | A kind of thermal interface material and its manufacturing method |
CN1509794A (en) * | 2002-12-23 | 2004-07-07 | ���ǵ�����ʽ���� | Apply Carbon Nanotube Filter |
-
2004
- 2004-08-14 CN CNB2004100511573A patent/CN100395887C/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6407922B1 (en) * | 2000-09-29 | 2002-06-18 | Intel Corporation | Heat spreader, electronic package including the heat spreader, and methods of manufacturing the heat spreader |
US20030173338A1 (en) * | 2001-11-21 | 2003-09-18 | Vallance Robert Ryan | Processes for nanomachining using carbon nanotubes |
US20040005736A1 (en) * | 2002-07-02 | 2004-01-08 | Intel Corporation | Method and apparatus using nanotubes for cooling and grounding die |
CN1483668A (en) * | 2002-09-17 | 2004-03-24 | 清华大学 | A method for growing carbon nanotube arrays |
CN1501483A (en) * | 2002-11-14 | 2004-06-02 | 清华大学 | A kind of thermal interface material and its manufacturing method |
CN1509794A (en) * | 2002-12-23 | 2004-07-07 | ���ǵ�����ʽ���� | Apply Carbon Nanotube Filter |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102280418A (en) * | 2010-06-09 | 2011-12-14 | 海力士半导体有限公司 | Semiconductor package with heat dissipation devices |
CN102280418B (en) * | 2010-06-09 | 2015-02-18 | 海力士半导体有限公司 | Semiconductor package with heat dissipation devices |
Also Published As
Publication number | Publication date |
---|---|
CN1734754A (en) | 2006-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100395887C (en) | Integrated circuit packaging structure and manufacturing method thereof | |
JP5146256B2 (en) | Sheet-like structure and manufacturing method thereof, and electronic device and manufacturing method thereof | |
JP5628312B2 (en) | Nanotube thermal interface structure | |
US10115656B2 (en) | Semiconductor device | |
TWI266401B (en) | Thermoelectric nano-wire devices | |
CN100358132C (en) | Thermal interface material producing method | |
CN1837147B (en) | Thermal interface material and its production method | |
US20110127013A1 (en) | Heat-radiating component and method of manufacturing the same | |
US20050136248A1 (en) | Thermal interface material and method for manufacturing same | |
US10490492B2 (en) | Method for forming semiconductor package using carbon nano material in molding compound | |
WO2008054364A2 (en) | Carbon nanotubes for the selective transfer of heat from electronics | |
CN101275209A (en) | Thermal interface material and preparation method thereof | |
CN101572255A (en) | Method for making carbon nanotube composite thermal interface material | |
JP2004104004A (en) | Pressure welding type semiconductor device | |
JP5013116B2 (en) | Sheet-like structure, method for producing the same, and electronic device | |
US7301232B2 (en) | Integrated circuit package with carbon nanotube array heat conductor | |
CN110729629A (en) | Semiconductor laser packaging structure based on graphene film and preparation method thereof | |
CN100364081C (en) | Radiator and method of manufacturing the same | |
EP4244887A1 (en) | Diamond-based thermal cooling devices methods and materials | |
CN100356556C (en) | Thermal interfacial material and method of manufacture | |
JP5768786B2 (en) | Sheet-like structure and electronic device | |
Solbrekken et al. | Use of superlattice thermionic emission for" hot spot" reduction in a convectively-cooled chip | |
US20220045027A1 (en) | Semiconductor device and method of manufacturing the same | |
CN1619800A (en) | Radiator and its preparation method | |
Awano et al. | Carbon Nanotube bumps for thermal and electric conduction in transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080618 Termination date: 20150814 |
|
EXPY | Termination of patent right or utility model |