CN100395813C - Driving circuit and driving method of electro-optical device, electro-optical device and electronic equipment - Google Patents

Abstract

The invention provides an electro-optical device capable of displaying images normally through area scanning. It has: a scanning line driving circuit for alternately supplying scanning signals to a plurality of scanning lines in each partial area to a plurality of partial areas obtained by dividing an image display area; and an image signal supply circuit for By vacating the method of dividing the vertical retrace period, and dividing the total number n of the plurality of sub-regions by 1/n horizontal scanning period, each of the plurality of sub-regions is scanned horizontally, based on the display data, generating An image signal is supplied to a plurality of data lines; a scanning line driving circuit is provided in each The field period is the last method, and a scanning signal is supplied.

Description

Driving circuit and driving method of electro-optical device, electro-optical device and electronic equipment

technical field

The present invention relates to the technical field of, for example, a driving circuit and a driving method for driving an electro-optical device such as a liquid crystal device, an electro-optical device having the driving circuit, and electronic equipment such as a liquid crystal projector having such an electro-optical device.

Background technique

An example of an electro-optical device driven by such a driving circuit is a liquid crystal device having data lines and scanning lines arranged vertically and horizontally in an image display region on a substrate, and pixel portions formed corresponding to their intersections.

In such a liquid crystal device, for example, based on a source signal supplied from a personal computer or a video recorder, a display data generation circuit generates a horizontal synchronization signal, a vertical synchronization signal, and display data. Then, each pixel unit is driven by a drive circuit based on these horizontal and vertical synchronization signals and display data. In addition, generally, the horizontal synchronization signal is generated so that the interval between output timings of two consecutive horizontal synchronization signals, that is, one horizontal scanning period, is basically a constant period on the time axis.

Here, the present inventors discovered a unique driving method for performing image display by scanning a plurality of partial regions obtained by dividing the image display region by dividing lines along scanning lines as follows. That is, according to this driving method, the driving circuit generates scanning signals based on the horizontal synchronizing signal and the vertical synchronizing signal, and supplies the scanning signals alternately to each sub-region and sequentially to each scanning line. Also, with respect to a pair of two subregions among the plurality of subregions, one of the two subregions is driven based on an image signal having a polarity different from the reference potential in a cycle of selecting a scanning line. In the pixel portion and the pixel portion of the other partial region of the two partial regions, an image signal generated based on display data by a drive circuit is supplied to each data line. According to such a driving method, when the plurality of subregions are two subregions, during one field period defined by the interval between the output timings of two vertical synchronizing signals, it is possible to change the polarity and write twice in the Each pixel unit displays an image signal of one screen.

Patent Document 1: JP 2004-177930

For example, when the video standard of the display device of a personal computer is, for example, SVGA (Super VGA (Video Graphics Display Card)), and the video standard of a liquid crystal device is, for example, XGA (Extended Graphics Array), in the display device and the liquid crystal device , the total number of pixels for image display or the driving frequency are different. Therefore, a so-called down-conversion or up-conversion may be performed by converting a source signal or display data having a different specification such as a total number of pixels or a drive frequency in accordance with a liquid crystal device. However, at the time of corresponding conversion, the total number of horizontal synchronization signals sometimes cannot be an integral multiple of the total number of vertical synchronization signals. As a result, within one field period, almost all the horizontal scanning periods can be defined as constant periods, but the final horizontal scanning period cannot reach the constant period. In other words, there arises a problem that the last horizontal sync pulses of each field period do not reach equal intervals.

Alternatively, in a video recorder, a source signal generated by reproducing a video tape is affected by a damaged state of the tape on the video tape, such as expansion and contraction. Therefore, signal processing may be performed with the horizontal scanning period as a constant period. Furthermore, in signal processing, almost all horizontal scanning periods within one field period can be defined as constant periods, but there is a problem that the last horizontal scanning period cannot be at equal intervals.

In this way, when the predetermined equal intervals are not reached in the last horizontal scanning period, in the above-mentioned area scanning, for each of the plurality of sub-areas, there is a scanning line corresponding to the last scanning signal supplied in one field period. There is a possibility that the image signal cannot be written normally in the corresponding pixel portion. This is because, before the image signal is written in all the pixel portions corresponding to the scanning line to which the last scanning signal is supplied, the image signal to be written in the pixel portion corresponding to another scanning line adjacent to the scanning line occurs. There is a problem that image signals are written in part of the pixel portion, or the writing time of image signals cannot be sufficiently ensured. Especially when the edge of one partial area of the area scan is located at the center or near the center of the image display area, the above-mentioned abnormal writing of the image signal may cause very conspicuous display failure.

Contents of the invention

The present invention is made in view of the above facts, and its object is to provide a driving circuit and its driving method, an electro-optical device having such a driving circuit, and various electronic devices of the electro-optical device, even if the electro-optical device uses The above-mentioned problem occurs when the area scanning is used for image display, but the influence on the display screen can also be reduced, and the image display can be performed normally.

The drive circuit of the electro-optic device of the present invention provides a drive circuit for the electro-optic device in order to solve the above problems, which is used to drive the image display area on the substrate, has a plurality of data lines and a plurality of scan lines, and is connected to the The driving circuit of the electro-optic device of the plurality of pixel units electrically connected to the scanning line and the data line includes: the partial areas alternately and sequentially supply scan signals to the plurality of scan lines on each partial area; and the image signal supply circuit for each The method of dividing the vertical retrace period during the field period is divided by the total number n (n is a natural number greater than or equal to 2) of multiple partial areas divided by 1/n of the horizontal scanning period specified by the horizontal synchronization signal of the display data During the horizontal scanning period, each method of horizontally scanning a plurality of sub-regions generates image signals based on the display data and supplies them to the plurality of data lines; The order of supplying the scanning signal of a scanning line located along an edge of the scanning line in the image display area is the last mode in which the scanning signal is supplied in each of the field periods.

In the electro-optical device driven by the driving circuit of the present invention, in the image display region, each pixel portion includes a thin film transistor (Thin Film Transistor, hereinafter appropriately referred to as "" TFT") and other pixel switching elements, etc. In this case, in each pixel portion, the display element is electrically connected to the scanning line and the data line through the pixel switching element.

When the electro-optical device is driven, a source signal is supplied to the electro-optical device from a video recorder, a personal computer, or the like. Then, based on the source signal, the following processing is performed in the external circuit of the electro-optical device to generate display data and a vertical synchronization signal and a horizontal synchronization signal related to the display data. For example, in the external circuit of the electro-optical device, the above-mentioned down-conversion or up-conversion is performed based on the source signal, or the source signal generated by a video recorder or the like and has fluctuation in the direction of the time axis is performed, and the horizontal scanning period is defined as a constant period. signal processing. Therefore, the display data thus generated may be output as incomplete display data whose horizontal scanning period is not constant at the end of each field period. However, according to the present invention, it is possible to configure such inconsistency in displaying based on such incomplete display data, especially when displaying by area scan, not to be conspicuous on the display image.

Then, based on the horizontal synchronizing signal, the vertical synchronizing signal, and the display data, in the image display area of the electro-optical device, area scanning is performed as follows.

The scanning line driving circuit generates scanning signals at a timing based on a horizontal synchronizing signal in one field period, and sequentially outputs the scanning signals to a plurality of scanning lines, for example, line-sequentially, alternately to each partial area. For example, when the total number of partial regions is n=2, a scanning signal is supplied to one of the two partial regions during the 1/2 horizontal scanning period located in the first half of one horizontal scanning period. During the 1/2 horizontal scanning period which is the second half of one horizontal scanning period, a scanning signal is supplied to the other partial area of the two partial areas.

In addition, in the 1/2 horizontal scanning period located in the first half of one horizontal scanning period, the image signal supplied from the image signal supply circuit is supplied to the pixel corresponding to the scanning line supplying the scanning signal to one partial area through the data line. department. In each of these pixel portions, for example, when a scanning signal is supplied from a scanning line, a pixel switching element is turned on, and an image signal is supplied to a display element from a corresponding data line via the pixel switching element. Then, the display element performs image display based on the image signal.

In addition, in the 1/2 horizontal scanning period located in the second half of one horizontal scanning period, the image signal supplied from the image signal supply circuit is supplied to the other partial area via the data line, corresponding to the scanning line to which the scanning signal is supplied. of the pixel portion. Then, these pixel units perform image display in the same manner as the pixel units in one partial region.

In this way, when the total number of partial regions is n=2, two partial regions are alternately scanned in each horizontal scanning period of one field period. Here, in the last 1 horizontal scanning period of 1 field period, the last scanning signal is supplied to the other partial region in the second half of the 1/2 horizontal scanning period. The final scanning signal is supplied to a scanning line facing one side along the scanning line on the image display area in another partial area, and the pixel portion corresponding to the scanning line is horizontally scanned. Then, when the horizontal scanning ends in another part of the area, the vertical retrace period starts and one field period ends.

Therefore, in the case where the last horizontal scanning period is not a constant period, as long as the last horizontal scanning period is 1/2 the horizontal scanning period or more in length, it will not be visible on the display screen displayed on the image display area. The degree of display is poor. That is, if the last horizontal scanning period is 1/2 horizontal scanning period or more in length instead of a constant period, there is a possibility that image signals cannot be normally written in the pixel portion corresponding to one scanning line. However, in this case, since the horizontal scanning period is not equally spaced, the image signal that is normally written incompletely does not appear on the display screen because the pixel portion to be written is located at the edge of the image display area. Visibility is poorly displayed. Such a pixel portion may appear at the edge of the image display area to some extent, may be arranged in an area covered by a frame, or may be used as a dummy pixel portion.

Alternatively, at the end of the last horizontal scanning period, as long as the vertical retrace period, the writing of the image signal in each pixel portion of the image display area can be normally performed, there is no influence on the display screen.

The above results show that, according to the present invention, due to the incomplete display data in the last horizontal scanning period based on each field period, the inappropriateness when performing display by area scanning is not obvious on the display screen, so it is important to improve the image quality. The quality is very beneficial.

In the above, the case where the total number of partial regions n=2 has been mainly described, but according to the drive circuit of the electro-optical device of the present invention, as long as it is on the time axis, the offset from the constant period of the last horizontal scanning period of one field period to If shifted, with respect to the total number n of partial regions, the maximum suppression is within 1/n horizontal scanning period or less, and the above-mentioned effects can be obtained. That is, since the degree of freedom of signal processing on the external circuit of the electro-optic device is increased, and the margin for temporal shift in the last horizontal scanning period of each field period is set relatively large, it is very practically useful.

In one aspect of the driving circuit of the electro-optical device according to the present invention, the image signal supply circuit scans the image display area vertically during a 1/n field period divided by the total number n of the 1 field period. , generating the image signal.

According to this method, one screen is displayed in the image display area every 1/n field period. That is, n screens can be displayed in the image display area during one field period.

In another aspect of the drive circuit according to the present invention, the image signal supply circuit adjusts and generates the image signal at any one of a positive polarity and a negative polarity voltage with respect to a reference potential.

According to this aspect, the image signal supply circuit, in the image display area, for the paired two sub-regions among the plurality of sub-regions, the pixel portion of one sub-region and the pixel portion of the other sub-region are based on the difference between each other. In a method of displaying images with image signals of different polarities, the image signals are supplied, and image signals of different polarities are supplied at a predetermined cycle to the pixel portions of each partial region. Accordingly, in the image display region, plane inversion driving can be performed for each partial region.

In another aspect of the driving circuit of the present invention, a correction circuit is further provided so that, based on the vertical synchronizing signal and the horizontal synchronizing signal, in the last horizontal scanning period of the one field period, the final The length of the last horizontal scanning period is adjusted so that the period ends within the period within the end of the vertical retrace period after the start of the supply period of the scanning signal.

According to this aspect, by adjusting the length of the last horizontal scanning period using the correction circuit, it is possible to adjust the offset of the constant period from the last horizontal scanning period of one field period on the time axis. Thereby, the last horizontal scanning period can be completed within the supply period of the last scanning signal or during the vertical retrace period. Therefore, according to this aspect, based on the incomplete display data in the last horizontal scanning period of each field period, it is possible to make display defects by area scanning less conspicuous on the display screen.

In other forms of the driving circuit of the present invention, the plurality of partial regions are two partial regions obtained by dividing by the dividing line; the scanning line driving circuit alternately and The scanning signals are supplied line-sequentially with respect to the scanning lines on the respective partial regions.

According to this method, as long as the last horizontal scanning period of one field period has a length of 1/2 horizontal scanning period or more, it is possible to make the pass area based on the incomplete display data located in the last horizontal scanning period of each field period. Improper scanning for display is not noticeable on the display screen.

In other forms of the driving circuit of the present invention, the plurality of partial regions are four partial regions divided by the dividing line; the scanning line driving circuit alternately And the scanning signals are sequentially supplied with respect to the scanning lines on the respective partial regions.

According to this aspect, in one horizontal scanning period, an image signal is written to the pixel portion of each partial region every 1/4 horizontal scanning period. Then, in the last 1/4 horizontal scanning period of the last horizontal scanning period of one field period, the pixel portion corresponding to one scanning line facing one side along the scanning line on the image display region is horizontally scanned. Therefore, as long as the length of the last horizontal scanning period is 3/4 of the horizontal scanning period or more, based on the incomplete display data in the last horizontal scanning period of each field period, it is possible to make the display by area scanning The inappropriateness is not obvious on the display screen.

The electro-optical device of the present invention has the above-mentioned driving circuit (including various aspects) of the electro-optical device of the present invention in order to solve the above problems.

According to the electro-optical device of the present invention, by driving the electro-optical device using the driving circuit of the present invention described above, the quality of a displayed image in the image display region can be improved.

In order to solve the above-mentioned problems, the electronic equipment of the present invention includes the above-mentioned drive circuit for the electro-optical device of the present invention (including various aspects).

The electronic equipment of the present invention has the above-mentioned electro-optic device of the present invention, so it is possible to realize a projection type display device, a television, a mobile phone, an electronic notebook computer, a word processor, a viewfinder type monitor, etc., capable of displaying high-quality images. Various electronic equipment such as direct-view video tape recorders, workstations, TV phones, POS terminals, and touch panels. And, as the electronic equipment of the present invention, also can realize, for example electrophoretic device such as electronic paper, electron emission device (Field Emission Display and Conduction Electron-Emitter Display), as the DLP (Digital Light Processing) that adopts these electrophoretic device, electron emission device wait.

The driving method of the electro-optic device of the present invention is used to drive the image display area on the substrate in order to solve the above-mentioned problems, and has a plurality of data lines and a plurality of scanning lines, and is electrically connected to the scanning lines and the data lines respectively. The driving method of an electro-optical device of a plurality of connected pixel units includes: a first step of alternately dividing the plurality of sub-regions obtained by dividing the image display region by a dividing line along the scanning line; ground, and sequentially supply scanning signals to the plurality of scanning lines on each partial area; the second step is to vacate the vertical retrace period during each field period specified by the vertical synchronous signal of the display data. , and by dividing the 1/n horizontal scanning period of 1 horizontal scanning period specified by the horizontal synchronizing signal of the display data by the total number n (n is a natural number equal to or greater than 2) of the plurality of partial regions, horizontal scanning of the plurality of partial regions Respectively, image signals are generated based on the display data and supplied to the plurality of data lines; The order of supplying the scanning signal for one scanning line on one edge of the scanning line is the last mode in each of the field periods, and the scanning signal is supplied.

In the driving method of the present invention, similarly to the above-mentioned driving circuit of the present invention, due to incomplete display data in the last horizontal scanning period based on each field period, it is inappropriate when displaying by area scanning. It is not obvious on the screen, so it is very beneficial to improve the picture quality. In addition, since the degree of freedom of signal processing in the external circuit of the electro-optical device is increased, and the margin for temporal shift in the last horizontal scanning period of each field period is set relatively large, it is very useful for practical use.

In one aspect of the method for driving an electro-optical device according to the present invention, in the second step, the image display area is vertically scanned during the 1/n field period divided by the total number n , generating the image signal.

According to this aspect, n screens can be displayed in the image display area during one field period.

In another aspect of the method for driving an electro-optical device according to the present invention, in the second step, the image signal is adjusted and generated at either a positive polarity or a negative polarity voltage with respect to the reference potential.

According to this aspect, it is possible to perform plane inversion driving for each partial region in the image display region.

Such functions and benefits of the present invention will be clarified from the embodiments described below.

Description of drawings

FIG. 1 is a plan view showing the overall configuration of a liquid crystal panel.

Fig. 2 is a H-H' sectional view of Fig. 1 .

FIG. 3 is a block diagram showing the overall configuration of a liquid crystal device.

FIG. 4 is a block diagram showing an electrical configuration of a liquid crystal panel.

FIG. 5 is a diagram showing an example configuration of a scanning line driving circuit.

FIG. 6 is an explanatory diagram illustrating generation of an image signal in the image signal supply circuit.

FIG. 7 is a timing chart illustrating the operation of the scanning line driving circuit.

FIG. 8 is a timing chart showing temporal changes of various signals for driving each data line and each scanning line.

FIG. 9 is an explanatory diagram conceptually explaining the area scan of the present embodiment.

FIG. 10 is a block diagram showing the configuration of a correction circuit.

Fig. 11 is a flowchart illustrating the operation of the correction circuit.

12 is a block diagram showing an electrical configuration of a liquid crystal panel according to a second embodiment.

FIG. 13 is an explanatory diagram conceptually explaining the area scan of the second embodiment.

Fig. 14 is an explanatory diagram (Part 1) conceptually explaining the area scan of the third embodiment.

15 is an explanatory diagram illustrating generation of an image signal by the image signal supply circuit of the third embodiment.

FIG. 16 is an explanatory diagram (part 2 ) conceptually explaining the area scan of the third embodiment.

17 is a plan view showing the configuration of a projector as an example of electronic equipment to which a liquid crystal device is applied.

FIG. 18 is a perspective view showing the configuration of a personal computer as an example of electronic equipment to which a liquid crystal device is applied.

FIG. 19 is a perspective view showing the configuration of a mobile phone as an example of electronic equipment to which a liquid crystal device is applied.

In the figure: 10a-image display area, 10aa-first part area, 10ab-second part area, 10ac-third part area, 10ad-fourth part area, 10-TFT array substrate, 62-first frame memory, 70—pixel unit, 101—data line driving circuit, 104—scanning line driving circuit, 112—scanning line, 114—data line, 300—image signal supply circuit, 502—display data generating circuit.

Detailed ways

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following embodiments apply the electro-optical device of the present invention to a liquid crystal device.

<1. First Embodiment>

First, a first embodiment of the electro-optical device of the present invention will be described with reference to FIGS. 1 to 11 .

<1-1. Overall configuration of the electro-optical device>

1 and 2, the overall configuration of a liquid crystal panel as an example of an electro-optic panel in an electro-optical device or a liquid crystal device of the present invention will be described. Here, FIG. 1 is a plan view showing the overall configuration of the liquid crystal panel of the TFT array substrate viewed from the counter substrate together with each component formed on the TFT array substrate, and FIG. 2 is a H-H' sectional view of FIG. 1 . Here, a liquid crystal panel of a TFT active matrix driving method with a built-in driving circuit is taken as an example.

In FIGS. 1 and 2 , in the liquid crystal panel 100 of this embodiment, the TFT array substrate 10 and the counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the opposite substrate 20, and the TFT array substrate 10 and the opposite substrate 20 are bonded to each other through the sealing member 52 provided on the sealing area around the image display area 10a. .

The sealing member 52 is made of, for example, ultraviolet curable resin or thermosetting resin for laminating the two substrates. In the manufacturing process, it is applied on the TFT array substrate 10 and cured by ultraviolet irradiation or heating. In addition, a spacer such as glass fiber or glass beads is dispersed in the sealing member 52 to keep the distance (substrate gap) between the TFT array substrate 10 and the counter substrate 20 at a predetermined value.

Parallel to the inner side of the sealing region where the sealing member 52 is disposed, on the counter substrate 20 side, a light-shielding frame edge shielding film 53 defining the frame edge region of the image display region 10 a is provided. However, part or all of such frame-side light-shielding films 53 may be provided on the TFT array substrate 10 side as built-in light-shielding films.

A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a peripheral area located around the image display area 10 a outside the sealing area where the sealing member 52 is placed. In addition, the scanning line driving circuit 104 is provided along any one of the two sides adjacent to this one side, so as to cover the frame side light-shielding film 53 . Alternatively, they may be provided along two sides adjacent to one side of the TFT array substrate 10 on which the data line drive circuit 101 and the external circuit connection terminal 102 are provided. In this case, the two scanning line driving circuits 104 are connected to each other by a plurality of wirings provided along the remaining side of the TFT array substrate 10 .

In addition, vertical conductors 106 functioning as vertical conduction terminals between the two substrates are arranged at the four corners of the opposing substrate 20 . Further, on the TFT array substrate 10 , vertical conduction terminals are provided in regions facing these corners. This enables electrical conduction between the TFT array substrate 10 and the counter substrate 20 .

In FIG. 2 , on the TFT array substrate 10 , an alignment film is disposed on TFTs for pixel switching elements or on pixel electrodes 9 a after wiring such as scanning lines and data lines. In addition, on the counter substrate 20 , in addition to the counter electrode 21 , a grid-shaped or stripe-shaped light-shielding film 23 is formed, and then an alignment film is formed on the uppermost layer portion. In addition, the liquid crystal layer 50 is composed of, for example, a liquid crystal in which one or more types of nematic liquid crystals are mixed, and a predetermined alignment state is formed between the pair of alignment films.

In addition, although not shown in FIG. 1 and FIG. 2, on the TFT array substrate 10, in addition to the data line driving circuit 101 or the scanning line driving circuit 104, etc., it is also possible to form a circuit that is supplied to a plurality of data lines in advance of the image signal, respectively. A precharge circuit for a precharge signal of a predetermined voltage level, an inspection circuit for inspecting the quality, defects, etc. of the electro-optical device during manufacture or delivery, and the like.

<1-2: Overall configuration of the electro-optical device>

The overall configuration of the liquid crystal device will be described with reference to FIGS. 3 and 4 . Here, FIG. 3 is a block diagram showing the overall configuration of the liquid crystal device, and FIG. 4 is a block diagram showing the electrical configuration of the liquid crystal panel.

As shown in FIG. 3 , the liquid crystal device includes a liquid crystal panel 100 as a main component. Image signal supply circuit 300 , first frame memory 62 and second frame memory 63 , timing control circuit 400 , display data generation circuit 502 , and power supply circuit 700 .

The display data generation circuit 502 generates, for example, a horizontal synchronization signal Hs, a vertical synchronization signal Vs, a dot clock signal DCLK, and display data D0 based on a source signal DATA supplied from a video recorder or a personal computer. Here, for example, the display data generation circuit 502 performs the already-described down-conversion or up-conversion based on the source signal DATA, or performs the horizontal scanning period of the source signal generated by a video recorder or the like and has jitter in the direction of the time axis. Signal processing defined as constant duration. Therefore, the display data D0 generated in this way may be output as incomplete display data whose horizontal scanning period is not constant at the end of each field period. In addition, in order to adjust the offset of the constant period from the last horizontal scanning period of each field period, the display data generating circuit 502 includes a method for adjusting the temporal length of one horizontal scanning period in one field period as described later. The correction circuit 501.

The timing control circuit 400 is configured to output various timing signals used in each unit. The timing control circuit 400 generates a Y clock signal CLY, an inverted Y clock signal CLYinv, an X clock signal CLX, an inverted X Clock signal XCLinv, Y start pulse DY and X start pulse DX. In addition, in the timing control circuit 400 , two types of enable signal ENB1 and enable signal ENB2 that determine the output timing of the scanning signal described later are generated.

In addition, in this embodiment, in addition to the image signal supply circuit 300 and the first frame memory 62 and the second frame memory 63 shown in FIG. A data line driving circuit 101 is included.

The image signal supply circuit 300 is supplied with a horizontal synchronization signal Hs, a vertical synchronization signal Vs, a dot clock signal DCLK, and display data D0 from the display data generation circuit 502 . The image signal supply circuit 300 generates two types of field data based on the display data D0, and temporarily stores the generated two types of field data in the first frame memory 62 and the second frame memory 62 during a cycle of supplying a scanning signal to one scanning line as described later. One of the frame memories 63 simultaneously reads one type of field data stored in the other. In addition, each of the two types of field data includes display data for displaying one screen.

Then, the image signal supply circuit 300 performs predetermined processing on the read one type of field data. As an example of this predetermined processing, in the image signal supply circuit 300 , for example, one type of field data is converted in serial to parallel to generate N-phase, for example, 6-phase (N=6) image signals VID1 to VID6 . In addition, the image signal supply circuit 300 generates an image signal VIDk (k=1, 2, . VIDk.

Furthermore, the power supply circuit 700 supplies a common power supply of a predetermined common potential LCC to the counter electrode 21 shown in FIG. 2 . In the present embodiment, the counter electrode 21 is formed on the lower side of the counter substrate 20 shown in FIG. 2 so as to face the plurality of pixel electrodes 9 a.

Next, the electrical configuration on the liquid crystal panel 100 will be described.

As shown in FIG. 2 , on the liquid crystal panel 100 , an internal driving circuit including a scanning line driving circuit 104 and a data line driving circuit 101 is provided in the peripheral region of the TFT array substrate 10 .

The scanning line driving circuit 104 will be described later in detail, but can perform basic line-sequential horizontal scanning by supplying the Y clock signal CLY, the inverted Y clock signal CLYinv, and the Y start pulse DY. In addition, the scanning line driving circuit 104 outputs scanning signals G1 , G2 , .

In this embodiment, the main configuration of the data line driving circuit 101 includes a sampling signal supply circuit 101a and a sampling circuit 101b. An X clock signal CLX, an inverted X clock signal CLXinv, and an X start pulse DX are supplied to the sampling signal supply circuit 101a. The sampling signal supply circuit 101a generates sampling signals S1, .

The sampling circuit 101b has a plurality of sampling switches 202 composed of P-channel or N-channel single-channel TFTs or complementary TFTs.

The liquid crystal panel 100 also has data lines 114 and scanning lines 112 arranged vertically and horizontally on the image display area 10a occupying the center of its TFT array substrate, and in each pixel portion 70 corresponding to their intersections, there are liquid crystal elements arranged in a matrix. 118 pixel electrode 9a and TFT 116 for switching and controlling the pixel electrode 9a.

In addition, in this embodiment, the total number of scan lines 112 is defined as y (y is a natural number greater than or equal to 2), and the total number of data lines 114 is defined as x (x is a natural number greater than or equal to 2). ),Be explained.

As described above, for example, the video signals VID1 to VID6 developed in six phases in series and parallel are supplied to the liquid crystal panel 100 through the video signal lines 171 .

In the sampling circuit 101b, N (six in this embodiment) sampling switches 202 are used as a group, and sampling signals Si (i=1, 2, . . . , x). The sampling switches 202 belonging to one group use N (six in this embodiment) data lines 114 as one group, and sample and supply the video signal VIDk to the data lines 114 belonging to one group based on the sampling signal Si. That is, the data lines 114 belonging to one group are electrically connected to the image signal lines 171 through the sampling switches 202 belonging to one group. Therefore, in the present embodiment, since x data lines 114 are driven for each data line 114 belonging to one group, the driving frequency can be suppressed.

In FIG. 4, if paying attention to the structure of one pixel portion 70, the source electrode of the TFT 116 is electrically connected to the data line 114 for supplying the image signal VIDk, and the gate electrode of the TFT 116 is electrically connected to supply the scanning signal Gj(j). =1, 2, 3, . . . , y) the scanning line 112 is connected to the pixel electrode 9a of the liquid crystal element 118 on the drain electrode of the TFT 116 at the same time. Here, in each pixel portion 70 , the liquid crystal element 118 sandwiches liquid crystal between the pixel electrode 9 a and the counter electrode 21 . Therefore, each pixel unit 70 is arranged in a matrix corresponding to each intersection of the scanning line 112 and the data line 114 .

By turning off the switch on the TFT 116 only for a constant period, the image signal VIDk is supplied to the pixel electrode 9a of the liquid crystal element 118 at predetermined timing through the data line 114 . Accordingly, an applied voltage defined by the respective potentials of the pixel electrode 9 a and the counter electrode 21 is applied to the liquid crystal element 118 . Liquid crystals are capable of modulating light by changing the orientation or order of molecules assembled by an applied voltage level to perform gray scale display. In the normally white display mode, the transmittance to incident light is decreased by the voltage applied to each pixel unit, and in the normally black display mode, the transmittance to incident light is increased by the voltage applied to each pixel unit, as a whole , light having a contrast corresponding to the image signal VIDk is emitted from the liquid crystal panel 100 .

Here, a storage capacitor 119 is added in parallel with the liquid crystal element 118 in order to prevent leakage of the held image signal. For example, since the voltage of the pixel electrode 118 is held by the storage capacitor 119 for as much as 3 digits longer than the time when the source voltage is applied, the holding characteristic is improved so that high contrast can be realized.

<1-3: Operation of electro-optical device>

Next, the operation of the liquid crystal device will be described with reference to FIGS. 5 to 10 in addition to FIGS. 1 to 4 .

First, referring to FIG. 5 , the detailed configuration of the scanning line driving circuit 104 shown in FIG. 1 or FIG. 4 will be described. FIG. 5 shows an example of the configuration of the scanning line driving circuit 104 .

Here, in the following, in order to simplify the description, the area scan is described, the total number of scan lines 112 is specified as m=4, and the image display area 10a obtained by bisecting the image display area 10a using the dividing line 600 along the scan line 112 as shown in FIG. In the case of the first partial area 10aa and the second partial area 10ab, that is, area scanning when the total number of a plurality of partial areas is n=2.

In FIG. 5, the main configuration of the scanning line driving circuit 104 includes a Y-side shift register 104a for inputting a Y clock signal CLY, an inverted Y clock signal CLYinv, and a Y start pulse DY, and four scanning lines corresponding to 112. The output control unit 104b is composed of four logic circuits. One logic circuit, for example, includes a NAND (NAND) circuit 67 and a NOT (Not) circuit 68, and inputs an output signal from the Y-side shift register 104a, and two types of enable signals ENB1 and ENB2 to the NAND circuit 67 any party. In addition, the output signal of each NAND circuit 67 is output to the corresponding scanning line 112 as scanning signals G1 , G2 , G3 , and G4 via the NOT circuit 68 .

Next, area scanning performed on the first partial area 10aa and the second partial area 10ab will be described in detail with reference to FIGS. 6 to 9 in addition to FIGS. 1 to 5 .

6 is an explanatory diagram illustrating the generation of the image signal VIDk in the image signal supply circuit 300, FIG. 7 is a timing chart illustrating the operation of the scanning line driving circuit 104, and FIG. 112 Timing diagrams of the time variations of various signals. In addition, FIG. 9 is an explanatory diagram conceptually explaining the area scan of the present embodiment.

In FIG. 6, the image signal supply circuit 300 displays one screen in the image display area 10a based on one type of field data in each 1/2 field period within a field period specified by the vertical synchronizing signal Vs. The image signal VIDk is generated as follows. 6 shows an explanatory diagram related to the generation of the image signal VIDk when the total number of partial regions is specified as n=2 and the total number of scanning lines 112 is not limited to m=4. The image signal supply circuit 300 adjusts the voltage of the image signal VIDk to be equal to the voltage of the image signal VIDk during the 1/2 horizontal scanning period located in the first half of the horizontal scanning period within the horizontal scanning period specified by the horizontal synchronizing signal Hs. The potential v0 and the first display voltage specified by the display potential va(+) of positive polarity relative to the reference potential v0 convert the image signal VIDk to The voltage is adjusted to the second display voltage defined by the reference potential v0 and the negative polarity display potential vb(-) relative to the reference potential v0. FIG. 6 shows the video signal VIDk adjusted to the first display voltage as the video signal A, and the video signal VIDk adjusted to the second display voltage as the video signal B. In addition, the polarities of the image signal A and the image signal B are reversed with respect to the reference potential v0 every 1/2 field period.

Then, in the image signal supply circuit 300 , after the end of the supply of the image signal B in the last horizontal scanning period in every one field period, the image signal VIDk for a predetermined vertical retrace period is supplied.

Next, the area scanning in the 1/2 field period will be described with reference to FIGS. 7 and 8 .

In the 1/2 field period, from the scanning line driving circuit 104 shown in FIG. The area 10aa and the second sub-area 10ab sequentially supply the scanning signals G1 and G2 or G3 and G4 to the scanning lines 112 from above the sub-area 10aa or 10ab along the direction in which the scanning lines 112 are arranged.

As shown in FIG. 7, the output signals SR1-SR4 from the Y-side shift register 104a are output to the scanning lines 112 at the same timing as when the first sub-region 10aa and the second sub-region 10ab are simultaneously scanned horizontally. That is, in the first subregion 10aa and the second subregion 10ab, the output signals SR1 and SR3 corresponding to the scanning line 112 supplying the scanning signal Gj to the No. No. 2 supplies the output signals SR2 and SR4 corresponding to the scan line 112 of the scan signal Gj. Here, since the total number of scanning lines m=4 is explained, it is limited to this case, and output signals SR1, SR3 and output signals SR2, SR4 are alternately output every one horizontal scanning period. In addition, enable signals ENB1 and ENB2 alternately rise from low level to high level every 1/2 horizontal scanning period. Therefore, in the logic circuit, one of the output signals SR1 to SR4 that is output during the rising timing period of any one of the enable signals ENB1 and ENB2 is selected and output to the scanning line 112 as the scanning signal Gj. As a result, as shown in FIG. 7, the scanning signals G1 to G4 are sequentially sent from the scanning line driving circuit 104 every 1/2 horizontal scanning period.

In FIG. 8, if the 1/2 field period starts at time t0, in the first sub-region 10aa, the scanning line drive circuit 104 supplies the corresponding No. 1 scanning line 112 with the No. Scan signal G1.

Then, the image signal A is supplied from the image signal supply circuit 300 during the image signal supply period from time t1 to time t2. In addition, during the image signal supply period, the sampling signals S1, S2, . On state. Then, the image signal A is supplied to the data line 114 via the sampling switch 202 in the ON state, and supplied to the pixel portion 70 corresponding to the first scanning line 112 via the data line 114 .

Thereafter, at time t3, in the second partial region 10ab, the scanning line drive circuit 104 supplies the first number of the second partial region 10ab to the corresponding second scanning line 112 (if the slave scanning line driving circuit The output order of 104 is the scanning signal G3 of No. 2).

Then, the image signal B is supplied from the image signal supply circuit 300 during the image signal supply period from time t4 to time t5. The image signal B is supplied to each data line via the sampling switches 202 that are sequentially turned on with the sampling switches 202 belonging to one group based on the sampling signals S1, S2, ..., Sn supplied from the sampling signal supply circuit 101a. 114. Then, the image signal B is supplied to the pixel unit 70 corresponding to the second scanning line 112 via each data line 114 .

Thereafter, at time t6, in the first partial region 10aa, the scanning line driver circuit 104 supplies the second number of the first partial region 10aa to the corresponding third scanning line 112 (if the slave scanning line driving circuit The output order of 104 is the scanning signal G2 of No. 3). Then, in the image signal supply period from time t7 to time t8, image signal A is supplied to the pixel portion 70 corresponding to the third scanning line 112 similarly to the pixel portion 70 corresponding to the first scanning line 112 .

Next, at time t9, in the second sub-region 10ab, the scanning line driving circuit 104 supplies the second number of the second sub-region 10ab to the corresponding No. The output sequence is the scan signal G4 of No. 4). During the image signal supply period from time t10 to time t11 , the image signal B is supplied to the pixel portion 70 corresponding to the fourth scanning line 112 similarly to the pixel portion 70 corresponding to the second scanning line 112 .

Thereafter, the 1/2 field period ends at time t12. As described above, in FIG. 9 , in each horizontal scanning period of the 1/2 field period, in the 1/2 horizontal scanning period located in the first half of the 1 horizontal scanning period, when the horizontal scanning period on the first partial region 10aa After the image signal A is written in the pixel portion 70 corresponding to the scanning line 112, the pixel portion corresponding to the scanning line 112 on the second subregion 10ab is 70 to write the image signal B. Then, in every 1/2 field period, one screen is displayed in the image display area 10a, and at the same time, the polarities of the image signals A and B are respectively reversed by the image signal supply circuit 300, so that the first partial area 10aa and the first partial area 10aa can be driven in plane inversion, respectively. Part 2 area 10ab.

Here, returning to FIG. 6 , in the last horizontal scanning period of one field period, during the 1/2 horizontal scanning period of the second half of the last horizontal scanning period, the final horizontal scanning period of the second partial region 10ab is The fourth scanning line 112 supplies the last scanning signal G4. Then, the image signal B is supplied from the image signal supply circuit 300, and the pixel portion 70 corresponding to the fourth scanning line 112 is scanned horizontally. When the horizontal scanning of the pixel unit 70 corresponding to the fourth scanning line 112 is completed, the image signal VIDk for defining the vertical retrace period is output from the image signal supply circuit 300 .

In this embodiment, the display data generation circuit 502 includes a correction circuit 501 for adjusting the temporal length of the last horizontal scanning period of one field period. An example of the configuration and operation of the correction circuit 501 will be described with reference to FIGS. 10 and 11 . FIG. 10 is a block diagram showing the configuration of the correction circuit 501 , and FIG. 11 is a flowchart illustrating the operation of the correction circuit 501 .

In FIG. 10 , a correction circuit 501 includes a counter 512 , a detection unit 510 , and three types of logic circuits 514 , 516 , and 518 .

In the correction circuit 501, the horizontal synchronization signal Hs0, the vertical synchronization signal Vs, and the dot clock signal DCLK generated based on the source signal DATA are input to the display data generation circuit 502. The display data generation circuit 502 generates such that the interval between two consecutive horizontal synchronization signals Hs0 on the time axis reaches a predetermined interval. Accordingly, each horizontal scanning period in one field period becomes a constant period. However, if the total number of horizontal synchronization signals Hs0 is not an integral multiple of the total number of vertical synchronization signals Vs, the last horizontal scanning period of one field period may not be a constant period on the time axis. That is, the interval between two horizontal synchronization signals Hs0 generated by the display data generation circuit 502 and continuous on the time axis is not limited to a predetermined interval.

The counter 512 calculates whether or not the interval between the input timings of the two horizontal synchronizing signals Hs0 continuously input on the time axis is half of the temporal length of one horizontal scanning period, that is, a constant period. The output signal C1 is output as long as the length of the horizontal scanning period is equal to or longer than 1/2 of the horizontal scanning period. In addition, the interval between two output signals C1 at consecutive positions on the time axis has a length equivalent to one horizontal scanning period which is a constant period.

On the other hand, the output signal C2 output from the counter 512 rises from the low level to the high level at the input timing of the horizontal synchronization signal Hs0, and falls from the high level to the low level at the output timing of the output signal C1. . On the time axis, the output signal C2 is a signal that reaches a high level with a length equal to half the time length of one horizontal scanning period that is a constant period, that is, 1/2 the horizontal scanning period.

The detection unit 510, based on the output signal C2, the interval between the input timings of the two horizontal synchronizing signals Hs0 at consecutive positions on the time axis is less than half of the temporal length of one horizontal scanning period which is a constant period, That is, when the length is shorter than 1/2 of the horizontal scanning period, the detection signal C3 is output for the horizontal synchronizing signal Hs0 that is input relatively late among the two horizontal synchronizing signals Hs0 .

The logic circuit 514 calculates the logical product (AND) of the output signal C1 and the detection signal C3, and outputs an output signal C4. Furthermore, the logic circuit 516 outputs an output signal C5 when the horizontal synchronizing signal Hs0 is input when the output signal C2 is at the low level. Also, the logic circuit 518 calculates the logical sum (OR) of the two output signals C4 and C5, and outputs the horizontal synchronization signal Hs whose output timing has been corrected.

Next, the operation of the correction circuit 501 will be described with reference to FIG. 11 . In FIG. 11 , at time t51 , the last horizontal synchronizing signal Hs0 of one field period is input to the correction circuit 501 . Here, the input timing of the last horizontal synchronizing signal Hs0 and the time interval between the input timings of the horizontal synchronizing signal Hs0 continuously input before the last horizontal synchronizing signal Hs0 are equivalent to one horizontal scanning period which is a constant period. Since the length is equal to or longer than 1/2 of the horizontal scanning period, the output signal C1 and the output signal C2 are output from the counter 512 . In addition, the output signal C5 is output by the logic circuit 516 , while the horizontal synchronization signal Hs is output by the logic circuit 518 . Then, the last horizontal synchronizing signal Hs of one field period is output from the display data generation circuit 502 .

Next, at time t52 , one field period ends, and the next horizontal synchronization signal Hs connected to the last horizontal synchronization signal Hs0 is input to the correction circuit 501 . The time interval between the input timing of the next horizontal synchronizing signal Hs0 and the input timing of the last horizontal synchronizing signal Hs0 is shorter than 1/2 the length of the horizontal scanning period on the time axis. The detection unit 510 outputs the output signal C3 because the next horizontal synchronizing signal Hs0 is input while the output signal C2 is at a high level. In addition, at time t52 , the output signal C5 is not output by the logic circuit 516 . Also, at time t52 , since the output signal C1 is not output, the output signal C4 is not output from the logic circuit 514 , and thus the horizontal synchronization signal Hs is not output from the logic circuit 518 .

Continuing, at time t53 , since the output signal C1 is output and the output signal C3 is at a high level, the logic circuit 514 outputs the output signal C4 . Then, the horizontal synchronization signal Hs is output from the logic circuit 518 .

Here, the interval between the last horizontal scanning period of one field period defined by the output timing of the horizontal synchronizing signal Hs output at time t51 and the output timing of horizontal synchronizing signal Hs output at time t53 is corrected to be the same as 1/2 the same length as the horizontal scan period.

Returning to FIG. 6 , initially, the last horizontal scanning period of one field period is preferably a constant period. However, even if the last one horizontal scanning period is shorter than the constant period, the last one horizontal scanning period can be corrected to have the same length as the 1/2 horizontal scanning period by the correction circuit 501 . Therefore, the offset dt of the constant period from the last horizontal scanning period is adjusted to one horizontal scanning period equivalent to the 1/2 horizontal scanning period. In addition, in this embodiment, the offset dt of the constant period from the last horizontal scanning period may be adjusted by the correction circuit 501 so as to be shorter than 1/2 horizontal scanning period.

In this case, as shown in FIG. 6 , there is a possibility that the image signal B cannot be written normally in the pixel portion 70 corresponding to the fourth scanning line 112 . However, in this case, since the horizontal scanning period is not equally spaced, the image signal B that is normally incompletely written will not occur because the pixel portion 70 to be written is located at the edge of the image display area 10a. Visible display defects on the display screen. Alternatively, as long as the end time of the last horizontal scanning period is within the vertical retrace period, writing of image signals to each pixel unit 70 in the image display area 10a can be performed normally, so there is no influence on the display screen.

Therefore, according to the present embodiment described above, since the inconsistency when displaying by area scanning based on the incomplete display data D0 in the last horizontal scanning period of each field period is not obvious on the display screen, the Improving picture quality is very beneficial. In addition, since the degree of freedom of signal processing by the display data generating circuit 502 is increased, and a margin for temporal shift in the last horizontal scanning period of each field period is set relatively large, it is very practical.

<2. Second Embodiment>

Next, a second embodiment of the electro-optical device of the present invention will be described. In the second embodiment, a liquid crystal device serving as an electro-optical device has a different configuration of a liquid crystal panel than in the first embodiment. Therefore, below, regarding the configuration and operation of the liquid crystal device, only differences from the first embodiment will be described with reference to FIGS. 12 to 14 . In addition, the same code|symbol is attached|subjected to the same structure as 1st Embodiment, and overlapping description is abbreviate|omitted.

First, referring to FIG. 12 , the configuration of the liquid crystal panel according to the second embodiment will be described. 12 is a block diagram showing a circuit configuration of a liquid crystal panel in the second embodiment.

As shown in FIG. 12, on the liquid crystal panel 100, a dummy region 10c is provided in the image display region 10a. In the dummy region 10c, corresponding to the intersection of the scanning line 112 and the data line 114, a dummy pixel portion 70a not involved in image display is formed. The configuration of the dummy pixel portion 70a is substantially the same as that of the pixel portion 70 in the image display region 10a. In addition, since the dummy pixel portion 70 a does not participate in image display, driving elements such as the liquid crystal element 118 and the TFT 116 may or may not be formed.

Next, the operation of the liquid crystal device according to the second embodiment will be described with reference to FIG. 13 in addition to FIG. 12 . FIG. 13 is an explanatory diagram conceptually explaining the area scan of the second embodiment. In addition, in the second embodiment, the overall configuration of the liquid crystal device is the same as that of the first embodiment. Therefore, the overall configuration of the liquid crystal device will be described with reference to FIG. 3 .

Hereinafter, for simplicity of description, the total number of scanning lines 112 is m=4. In this case, as in FIG. 5 , area scanning is performed on the first partial area 10aa and the second partial area 10ab obtained by dividing the image display area 10a by the dividing line 600 along the scanning line 112 . The second partial region 10ab includes a dummy region 10c.

Next, area scanning in the 1/2 field period will be described with reference to FIG. 13 .

In FIG. 13, in each horizontal scanning period of the 1/2 field period, in the 1/2 horizontal scanning period located in the first half of the 1 horizontal scanning period, the scanning line 112 on the first partial region 10aa is horizontally scanned. The corresponding pixel portions 70 are written with the image signal A in these pixel portions 70 . Thereafter, in the 1/2 horizontal scanning period located in the second half of the horizontal scanning period, the pixel portions 70 corresponding to the scanning lines 112 on the second partial region 10ab are horizontally scanned, and an image is written on these pixel portions 70 Signal B. In this way, in the first partial area 10aa, the image signal A is written in the pixel portion 70 corresponding to the first scanning line 112, and the image signal B is written in the pixel portion 70 corresponding to the second scanning line 112, and then In the last 1 horizontal scanning period of the 1/2 field period, in the 1/2 horizontal scanning period located in the first half, the third scan on the image display area 10a which is the last on the first partial area 10aa The image signal A is written in the pixel portion 70 corresponding to the line 112 . Then, in the last 1 horizontal scanning period of the 1/2 field period, an image signal is written in the dummy pixel portion 70a corresponding to the fourth scanning line 112 in the second half of the horizontal scanning period. b.

Here, in the display data generating circuit 502 , the temporal length of the last horizontal scanning period of one field period can be adjusted by the correction circuit 501 . Accordingly, the offset dt of the constant period from the last horizontal scanning period is adjusted to be equal to or shorter than the 1/2 horizontal scanning period. In the last horizontal scanning period, since the image signal B corresponding to the dummy pixel portion 70a is written in the 1/2 horizontal scanning period located in the second half of the horizontal scanning period, the image display of each pixel portion 70 has no effect. any impact. Therefore, also in the second embodiment, the same advantages as those of the first embodiment can be enjoyed.

<3. Third embodiment>

Next, a third embodiment of the electro-optical device of the present invention will be described. In the third embodiment, the operation of the liquid crystal device as the electro-optical device is different from that in the first embodiment. Therefore, below, regarding the operation of the liquid crystal device, only differences from the first embodiment will be described with reference to FIGS. 14 to 16 . In addition, the same code|symbol is attached|subjected to the same structure as 1st Embodiment, and overlapping description is abbreviate|omitted.

14 and 16 are explanatory diagrams conceptually explaining the area scanning of the third embodiment, and FIG. 15 is an explanatory diagram illustrating generation of an image signal VIDk by the image signal supply circuit of the third embodiment. In addition, in the third embodiment, since the configuration of the liquid crystal device is the same as that in the first embodiment, it will be described with reference to FIGS. 3 and 4 .

Hereinafter, the total number of scanning lines 112 is defined as 4y, and as shown in FIG. The area 10ab, the third sub-area 10ac, and the fourth sub-area 10ad perform area scanning, that is, area scanning when the total number of a plurality of sub-areas n=4.

In the third embodiment, the image signal supply circuit 300 generates four types of field data based on the display data D0. In the third embodiment, four types of frame memories are provided instead of the first frame memory 62 and the second frame memory 63 shown in FIG. Any of the four types of field data is stored at one time, and one of the stored field data is read out from any of the four frame memories at the same time.

In FIG. 15 , video signal supply circuit 300 generates video signal VIDk for displaying one screen in image display region 10 a based on one type of field data in every 1/4 field period in one field period. At this time, the image signal supply circuit 300 adjusts the display voltage of the image signal VIDk every 1/4 horizontal scanning period in one horizontal scanning period. In FIG. 15 , by adjusting the display voltage in this way, an image signal VIDk generated every 1/4 horizontal scanning period is shown as four types of image signals A, B, C, and D. In the image signal supply circuit 300, the four types of image signals A, B, C, and D are adjusted to either positive or negative voltages with respect to the reference potential v0.

As shown in FIG. 15 , within one horizontal scanning period, image signal A, image signal B, image signal C, and image signal D are supplied from the image signal supply circuit 300 every 1/4 horizontal scanning period in this order. In addition, the image signal supply circuit 300 inverts the polarities of the four types of image signals A, B, C, and D with respect to the reference potential v0 in every 1/4 field period.

Next, area scanning in a 1/4 field period will be described with reference to FIG. 16 .

In the third embodiment, in one horizontal scanning period, the scanning signal Gj is alternately supplied from the scanning line driving circuit 104 to the first subregion 10aa, the second subregion 10ab, the third subregion 10ac, and the fourth subregion 10ad. , while in the 1/4 field period, in the first sub-region 10aa, the second sub-region 10ab, the third sub-region 10ac and the fourth sub-region 10ad, respectively along the arrangement direction of the scanning line 112, from the first sub-region The upper surface of 10aa, 10ab, 10ac, or 10ad faces downward, and scanning signal Gj is sequentially supplied to each scanning line 112 . In addition, within one horizontal scanning period, the scanning signal Gj is supplied every 1/4 horizontal scanning period in the order of the first subregion 10aa, the second subregion 10ab, the third subregion 10ac, and the fourth subregion 10ad.

Therefore, as shown in FIG. 16, in each horizontal scanning period of the 1/4 field period, the pixel portion 70 corresponding to the scanning line 112 on the first partial region 10aa is horizontally scanned in the 1/4 horizontal scanning period, and the After the image signal A is written in these pixel portions 70, the pixel portion 70 corresponding to the scanning line 112 on the second subregion 10ab is horizontally scanned in the next 1/4 horizontal scanning period connected to the 1/4 horizontal scanning period. , the image signal B is written in these pixel portions 70 . Next, in the 1/4 horizontal scanning period of the first half of the 2/4 horizontal scanning period of the second half of one horizontal scanning period, the pixel portion 70 corresponding to the scanning line 112 on the third subregion 10ac is horizontally scanned, and After the image signal C is written on these pixel portions 70, during the remaining last 1/4 horizontal scanning period, the pixel portions 70 corresponding to the scanning lines 112 on the fourth sub-region 10ad are horizontally scanned, and the pixel portions 70 are written on these pixel portions 70. input image signal D. Then, during the 1/4 field period, one screen is displayed on the image display area 10a. In addition, the image signal supply circuit 300 drives two pairs of the first sub-region 10aa, the second sub-region 10ab, the third sub-region 10ac, and the fourth sub-region 10ad with image signals based on mutually different polarities. Image signals A, B, C, and D are generated in a partial-area manner. Then, by inverting the polarity of the image signals A, B, C, and D in each 1/4 field period, the planes of the first sub-region 10aa, the second sub-region 10ab, the third sub-region 10ac, and the 4 part area 10ad.

In the third embodiment, in FIG. 15 , the correction circuit 501 adjusts the offset dt1 of the constant period from the last horizontal scanning period of one field period to be equal to or smaller than the 1/4 horizontal scanning period. short.

In the last 1 horizontal scanning period, during the last 1/4 horizontal scanning period, the image signal D is written in the pixel portion 70 corresponding to the last scanning line 112 of the fourth subregion 10ad. Therefore, there is a possibility that the image signal D cannot be written normally in the pixel portion 70 corresponding to the last scanning line 112 . However, since the pixel portion 70 corresponding to the last scanning line 112 of the fourth partial area 10ad is located at the edge of the image display area 10a, display defects to the extent visible on the display screen do not occur. Alternatively, as long as the end time of the last horizontal scanning period is within the vertical retrace period, writing of image signals to each pixel unit 70 in the image display area 10a can be performed normally, so there is no influence on the display screen. Therefore, also in the third embodiment, the same advantages as those of the first and second embodiments can be enjoyed.

<4. Electronic equipment>

Next, the case where the above-mentioned liquid crystal device is used in various electronic devices will be described.

<4-1. Projector>

First, a projector using the liquid crystal device as a light valve will be described. FIG. 17 is a plan layout view showing a configuration example of a projector. As shown in the figure, inside the projector 1100, a lamp unit 1102 composed of a white light source such as a halogen lamp is provided. Projected light emitted from the lamp unit 1102 is separated into RGB3 primary colors by four reflectors 1106 and two dichroic mirrors 1108 provided in the light valve 1104, and enters the light valves 1110R, 1110B, and 1110G corresponding to the respective primary colors. The three light valves 1110R, 1110B, and 1110G are each composed of a liquid crystal module including a liquid crystal device.

In the light valves 1110R, 1110B, and 1110G, the liquid crystal panel 100 is driven by the primary color signals of R, G, and B supplied from the image signal supply circuit 300 , respectively. Then, the light modulated by these liquid crystal panels 100 enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light beams are refracted at 90 degrees, and G light beams go straight. Therefore, it is possible to synthesize images of each color, and then project the color image on a fluorescent screen or the like via the projection lens 1114 .

Here, focusing on the display images formed by the light valves 1110R, 1110B, and 1110G, the display image formed by the light valve 1110G needs to be reversed left and right with respect to the display images formed by the light valves 1110R, 1110B.

In addition, since light corresponding to each primary color of R, G, and B enters the light valves 1110R, 1110B, and 1110G through the dichroic mirror 1108 , no color filter is required.

<4-2. Mobile PC>

Next, an example in which a liquid crystal device is applied to a mobile personal computer will be described. FIG. 18 is a perspective view showing the configuration of the personal computer. In the drawing, a computer 1200 is composed of a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206 . This liquid crystal display unit 1206 is configured by adding a backlight to the back of the liquid crystal device 1005 described above.

<4-3. Mobile phone>

In addition, an example in which a liquid crystal device is applied to a mobile phone will be described. Fig. 19 is a perspective view showing the structure of the mobile phone. In the figure, a mobile phone 1300 has a plurality of operation buttons 1302 and a reflective liquid crystal device 1005 . A front light is provided in front of the reflective liquid crystal device 1005 as necessary.

In addition, in addition to the electronic equipment described with reference to FIGS. 17 to 19, liquid crystal televisions, viewfinder-type and monitor direct-view video tape recorders, vehicle guidance devices, pagers, electronic notebook computers, desktop computers, and word processors can also be mentioned. , workstations, TV phones, POS terminals, devices with touch panels, etc. And, of course, it can also be used for these various electronic devices.

The present invention is not limited to the above-mentioned embodiments, and can be appropriately changed without departing from the purpose or idea described in the technical solution and the specification as a whole. The driving circuit and driving concept of the electro-optic device accompanying such changes have the following An electro-optical device for driving a circuit and an electronic device having the electro-optic device are also included in the technical scope of the present invention.

Claims (11)

1. A driving circuit of an electro-optical device, which is used to drive an image display area on a substrate, has a plurality of data lines and a plurality of scanning lines, and is electrically connected to the scanning lines and the data lines respectively An electro-optical device having a plurality of pixel portions, characterized by: have, a scanning line driving circuit that alternately for a plurality of sub-regions obtained by dividing the image display region by dividing lines along the scanning line, and for the plurality of sub-regions in each sub-region Scanning lines are sequentially supplied with scanning signals; and An image signal supply circuit that is divided in such a way that a vertical retrace period is vacated every field period specified by a vertical synchronizing signal related to display data, and the total number n of the plurality of sub-regions in use, where n is a natural number greater than or equal to 2, and divides 1/n horizontal scanning period of 1 horizontal scanning period specified by the horizontal synchronizing signal related to the display data, and horizontally scans each of the plurality of partial regions, based on the display data, generate an image signal, supply the plurality of data lines, the scan line driving circuit so that the supply order of the scan signal for one scan line is relative to one of the plurality of scan lines located on an edge along the scan line in the image display area , the scan signal is supplied in the last mode in each one field period. 2. The driving circuit of the electro-optic device according to claim 1, wherein the image signal supply circuit scans the image vertically during the 1/n field period divided by the total number n of the 1 field period. The image signal is generated in the manner of an image display area. 3. The drive circuit for an electro-optic device according to claim 1 or 2, wherein the image signal supply circuit adjusts and generates voltages of either positive polarity or negative polarity with respect to the reference potential, respectively. the image signal. 4. The driving circuit of the electro-optic device as claimed in claim 1 or 2, characterized in that: Furthermore, a correction circuit is provided that, based on the vertical synchronizing signal and the horizontal synchronizing signal, causes the last horizontal scanning period of the one field period to change to The length of the last horizontal scanning period is adjusted so that the vertical retrace period ends. 5. The driving circuit of the electro-optic device as claimed in claim 1 or 2, characterized in that: The plurality of partial areas are two partial areas obtained by dividing by the dividing line; The scanning line driving circuit supplies the scanning signal to the scanning lines in each partial area alternately and line-sequentially to the two partial areas. 6. The driving circuit of the electro-optic device as claimed in claim 1 or 2, characterized in that: The plurality of partial areas are four partial areas obtained by dividing by the dividing line; The scanning line driving circuit supplies the scanning signal to the scanning lines in the respective partial areas alternately and line-sequentially to the four partial areas. 7. An electro-optical device, characterized by comprising a drive circuit for the electro-optical device according to any one of claims 1 to 6. 8. An electronic device comprising the electro-optic device according to claim 7. 9. A driving method of an electro-optical device, the driving method is used to drive an image display area on a substrate, having a plurality of data lines and a plurality of scanning lines, and electrically connected to the scanning lines and the data lines respectively An electro-optical device having a plurality of pixel portions, characterized by: include, In the first step, for a plurality of partial regions obtained by dividing the image display region by dividing lines along the scanning lines, alternately for the plurality of partial regions, and for the plurality of scanning lines in each partial region sequentially, supplying scan signals; and The second step is to divide the vertical retrace period in every field period specified by the vertical synchronous signal related to the display data, and use the total number n of the plurality of sub-regions in use, where n is greater than a natural number equal to 2, dividing 1/n horizontal scanning period of 1 horizontal scanning period specified by a horizontal synchronizing signal related to said display data, a manner of horizontally scanning each of said plurality of partial regions, based on said display data, generating image signals to supply the plurality of data lines, In the first step, the order of supplying the scan signal for a scan line relative to an edge of the scan line in the image display area among the plurality of scan lines , the scan signal is supplied in the last mode every one of the field periods. 10. The driving method of an electro-optic device as claimed in claim 9, wherein in the second step, during the 1/n field period divided by the total number n of the 1 field period, the The image signal is generated in the manner of an image display area. 11. The driving method of an electro-optical device according to claim 9 or 10, wherein in the second step, with respect to the reference potential, according to any one of positive and negative voltages, respectively adjusting, The image signal is generated.

Images