CN100394381C - Synchronous multi-thread processor circuit and operating method - Google Patents

Abstract

Processing circuitry associated with running threads in an SMT processor can be configured to run with different performance metrics based on the number of threads currently running on the SMT processor. For example, according to some embodiments of the present invention, processing circuits related to the operation of threads in the SMT processor, such as floating point units or data caches, can be activated in a high-power mode based on the number of currently running threads in the SMT processor. or low power mode operation. Furthermore, as the number of threads run by an SMT processor increases, the performance metrics of the processing circuitry can be reduced, thereby providing the benefits of the SMT processor architecture while allowing a reduction in the amount of power consumed by the processing circuitry associated with the threads. Related computer program products and methods are also disclosed.

Description

Synchronous multi-thread processor circuit and operating method

This application claims priority from Korean Patent Application No. 2003-107595 filed on February 20, 2003, which is incorporated herein by reference in its entirety.

technical field

The present invention generally relates to computer processor architecture, and more particularly to synchronous multi-threaded computer processors, related computer program products and methods of operation thereof.

Background technique

Simultaneous multithreading (SMT) is a processor architecture that utilizes hardware multithreading to allow multiple independent threads to issue instructions during each cycle. Unlike other hardware multithreading architectures that only activate a single hardware context (ie, thread) in any given cycle, the SMT architecture allows all thread contexts to compete and share processor resources simultaneously.

SMT processors can use other unused cycles to execute instructions, which can reduce the impact of long wait operations in SMT processors. Also, performance may increase as the number of threads increases, which may also increase the power consumed by the SMT processor.

A block diagram of a conventional SMT processor is illustrated in Figure 1 . The operation of the traditional SMT processor in Figure 1 ^is described in Dean M.Tullsen; Susan J.Egger; Henry M.Levy; Jack L.Lo; 202 entitled Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, the disclosure of which is incorporated herein by reference. The architecture and operation of conventional SMT processors are well known in the art and they will not be described in further detail here.

Contents of the invention

Embodiments in accordance with the present invention may provide processing circuits, computer program products, and/or methods that operate at different performance metrics based on the number of threads executed by a simultaneous multithreading (SMT) processor. For example, in multiple embodiments of the present invention, the processing circuits related to the running of threads in the SMT processor, such as floating point units or data caches, can be based on the number of threads currently running on the SMT processor, in order of One of a high power mode or a low power mode operates. Furthermore, as the number of threads run by an SMT processor increases, the performance metrics of the processing circuitry can be reduced, thereby providing the benefits of the SMT processor architecture while allowing a reduction in the amount of power consumed by the processing circuitry associated with the threads. In other words, the SMT processor can run at the same power but with higher performance, or can consume more power but run at a higher performance index than conventional SMT processors.

In multiple embodiments according to the present invention, the processing circuit may be configured to run with a first performance index when the number of threads currently running by the SMT processor is less than or equal to a threshold value, and when the number of threads currently running by the SMT processor is When the number of running threads is greater than the threshold, run with the second performance indicator.

In various embodiments according to the present invention, the performance index control circuit may be used to provide a performance index for the processing circuit based on the number of threads currently running on the SMT processor. According to multiple embodiments of the present invention, when the number of currently running threads of the SMT processor is less than or equal to a threshold, the performance index control circuit can increase the performance index provided to the processing circuit to the first performance index. When the number of currently running threads of the SMT processor exceeds the threshold, the performance index control circuit can reduce the performance index provided to at least one processing circuit to a second performance index that is less than the first performance index.

In multiple embodiments according to the present invention, when the number of currently running threads of the SMT processor exceeds a second threshold greater than the first threshold, the performance index control circuit further reduces the performance index of the processing circuit to be less than the first threshold The third performance index of the second performance index.

Various embodiments of performance indicator variables may be provided in accordance with the present invention. For example, according to some embodiments of the invention, the processing circuit may be a cache memory circuit comprising a tag memory and a data memory for providing access to the tag memory when the cache memory is operating at a first performance indicator Synchronized cache data. The data store may be used to provide cache data responsive to a hit in the tag memory when the cache memory circuit is operating at a second performance indicator that is less than the first performance indicator.

In various embodiments according to the present invention, the cache may be at least one of a data cache for storing data operated by instructions and an instruction cache for storing instructions operated by associated data . According to various embodiments of the invention, the data cache is further operable to not provide cache data responsive to misses in the tag memory when operating at the second performance indicator.

In various embodiments according to the invention, the processing circuit may be a floating point unit. According to multiple embodiments of the present invention, the floating point unit may be a first floating point unit for running with a first performance index when the number of threads run by the SMT processor is less than or equal to a threshold, and the SMT processor may It further includes a second floating-point unit running with a second performance index smaller than the first performance index when the number of threads run by the SMT processor is greater than the threshold.

In various embodiments according to the present invention, the performance index control circuit is operable to increase or decrease the number of threads currently running by the SMT processor in response to threads being created and completed in the SMT processor, respectively.

According to various embodiments of the invention, the second processing circuit is operable to operate at a second performance indicator less than the first performance indicator in response to the number of threads currently running in the SMT processor increasing above the threshold.

According to various embodiments of the present invention, the performance index control circuit can be used to reduce the performance index provided to at least one processing circuit in response to the creation of a new thread, thereby reducing the number of threads currently running by the SMT processor from less than or equal to The threshold is increased above the threshold. According to various embodiments of the present invention, the performance index control circuit is operable to reduce the performance index of the processing circuit to a plurality of decreasing performance indexes as the number of threads currently running by the SMT processor exceeds each of rising thresholds one of the.

According to various embodiments of the present invention, the performance indicator control circuit is operable to maintain a first performance indicator for the first processing circuit, and respond to the number of threads currently running by the SMT increasing from less than or equal to a threshold value to greater than the threshold value, for the second The second processing circuit provides a second performance index less than the first performance index.

According to other embodiments of the present invention, the performance indicator control circuit may be used to provide performance indicators to the processing circuit in the SMT processor based on the number of threads currently running on the SMT processor.

Still according to other embodiments of the present invention, the thread management circuit can be used to allocate the processing circuit related to the SMT processor to the thread running in the SMT processor after the thread is created. The performance indicator control circuit is operable to provide one of a plurality of performance indicators to the processing circuit based on the number of threads currently executing by the SMT processor compared to at least one threshold.

Still according to other embodiments of the present invention, the cache memory associated with the SMT processor may include a tag memory and a data memory, which may be accessed synchronously or after accessing the tag memory based on the number of threads currently running on the SMT processor access to the data memory.

Description of drawings

FIG. 1 is a block diagram illustrating a conventional simultaneous multithreading (SMT) processor circuit architecture.

Figure 2 is a block diagram illustrating an embodiment of an SMT processor according to the present invention.

Figure 3 is a block diagram illustrating an embodiment of a thread management circuit according to the present invention.

FIG. 4 is a block diagram illustrating an embodiment of a performance index control circuit according to the present invention.

FIG. 5 is a flowchart illustrating an embodiment of the performance index control circuit according to the present invention.

Figure 6 is a block diagram illustrating an embodiment of a cache memory in accordance with the present invention.

Figure 7 is a block diagram illustrating an embodiment of an SMT processor according to the present invention.

Figure 8 is a block diagram illustrating an embodiment of an SMT processor according to the present invention.

Figure 9 is a block diagram illustrating an embodiment of an SMT processor according to the present invention.

FIG. 10 is a block diagram illustrating an embodiment of a performance index control circuit according to the present invention.

FIG. 11 is a flowchart illustrating an embodiment of a performance index control circuit according to the present invention.

Detailed ways

The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which illustrative embodiments of the invention are shown. However, the invention may be embodied in many different forms and should not be construed as limited to these embodiments; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully inform Those skilled in the art convey the scope of the invention. Throughout, like numerals refer to like elements.

It should be understood that although the terms "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from other elements. Thus, a first element discussed below could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the disclosure.

As one of ordinary skill in the art will understand, the present invention may be embodied as a circuit, a computer program product, and/or a computer program product. Accordingly, the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware features. Furthermore, the present invention can take the form of a computer program product on a computer-usable storage medium having computer-usable program code. Any suitable computer readable medium may be utilized including hard disks, CD-ROMs, optical storage devices, or magnetic storage devices.

The computer program code or "code" used to implement the operation according to the present invention can be written in an object-oriented programming language, such as JAVA Smalltalk or C++, JavaScript, VisualBasic, TSQL, Perl, or other programming languages. The software embodiments of the present invention do not rely on a particular programming language for implementation. Portions of code may all execute on one or more systems utilized by an intermediate server.

The code may execute entirely on one or more computer systems, or may execute partly on a server and partly on a client within a client device, or on a proxy server at an intermediate station in a communication network. In the latter scheme, the client device may connect to the server through a local or wide area network (eg, an intranet), or through the Internet (eg, via an Internet service provider). The invention can be embodied through the use of various protocols over various types of computer networks.

The present invention will be described below in combination with block diagrams and flowcharts illustrating methods, systems and computer program products according to embodiments of the present invention. It should be understood that each and every module of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a simultaneous multi-threaded (SMT) processor circuit, a special purpose computer, or other programmable data processing apparatus to create a machine such that all programs executed by a computer processor or other programmable data processing apparatus The instructions described above generate means for performing the functions specified in the blocks of the block diagrams and/or flowcharts.

These computer program instructions may be stored in a computer-readable memory to instruct a computer or other programmable data processing apparatus to operate in a specific manner, so that the instructions stored in the computer-readable memory generate the Or a piece of product with a command device for the function specified in the module.

The computer program instructions can be loaded into an SMT processor circuit or other programmable data processing device to perform a series of operational steps in a calculator or other programmable device, thereby generating a computer-implemented Instructions executed on a programming device provide the steps to implement the functions specified in the block diagrams and/or flowcharts or modules.

According to an embodiment of the present invention, a processing circuit related to running threads in the SMT processor may be provided, wherein the processing circuit is used to run with different performance indicators based on the number of threads currently running on the SMT processor. It should be appreciated that different performance metrics may include different circuit operating speeds and/or different accuracy metrics. According to various embodiments of the present invention, processing circuits according to the present invention may operate at different clock speeds and/or use different circuit types (eg, different types of CMOS devices) to provide different performance metrics. For example, according to multiple embodiments of the present invention, processing circuits related to the operation of threads in the SMT processor, such as floating point units or data caches, can be clocked at a high speed based on the number of currently running threads in the SMT processor. high power mode at high clock speeds or low power mode operation at low clock speeds. Furthermore, as the number of threads run by an SMT processor increases, the performance metrics of the processing circuitry can be reduced, thereby providing the benefits of the SMT processor architecture while allowing a reduction in the amount of power consumed by the processing circuitry associated with the threads.

It should be appreciated that in accordance with embodiments of the present invention, thread-level parallelism techniques that enable the use of multiple threads that inherently run in parallel to one another may be shown. As used herein, a "thread" may be an individual process thread with associated instructions and data may represent a process that is part of a parallel computer program having multiple processes. A thread can also be represented as a separate computer program that runs independently of other programs. Each thread may have an associated state, eg, defined by states respectively for associated instructions, data, program counters, and/or registers. For thread-related state, information sufficient for the thread executed by the processor can be included.

According to various embodiments of the present invention, the performance indicator control circuit is configured to provide respective performance indicators to the processing circuits allocated to the threads created in the SMT processor. For example, the performance index control circuit can provide a first performance index to enable the processing circuit to operate in a high power mode, and further, can provide a second performance index to the processing circuit operating in a low power mode. Still according to other embodiments of the present invention, the performance index control circuit provides an intermediate performance index (that is, other performance index between high power and low power).

According to various embodiments of the invention, the processing circuit operating at different performance metrics may be a cache memory including a tag memory and a data memory. When the cache memory is operating at the first performance indicator (ie, in a high power mode), the tag memory and the data memory can be accessed synchronously, regardless of whether the access to the tag memory will result in a hit. Synchronous access to the data memory provides higher performance when the hit rate in the tag memory is high. In other words, the cache memory is also capable of operating at a second performance level (ie, such as a low power mode), wherein the data memory is only accessed in response to a hit in the tag memory. Thus, some of the power consumption associated with accessing the data memory can be avoided if a tag miss occurs. Furthermore, accesses to the tag memory and data memory can be shifted in time if a tag hit occurs.

Still in other embodiments, the processing circuit associated with the thread execution of the SMT processor may be an instruction cache or other type of processing circuit, like a floating point circuit or an integer load/store circuit. Furthermore, each of these processing circuits can operate at different performance metrics. For example, according to various embodiments of the present invention, cache memories, instruction caches, and floating point circuits and integer load/store circuits can operate simultaneously with different performance metrics.

Still further in accordance with embodiments of the present invention, processing circuits of the same type (e.g., floating point circuits and integer load/store circuits) can be divided into different performance classes, such that some of the circuits are set to operate at a first performance specification, while others The operating circuit is configured to operate at the second performance indicator. For example, according to various embodiments of the present invention, some of the floating-point circuits for allocation to threads in SMT processors may be used to run in a high power mode, while others may be used for allocation to threads in SMT processors. floating-point circuitry that can be used to run in a low-power mode.

Figure 2 is a block diagram illustrating an embodiment of an SMT processor according to the present invention. According to FIG. 2, when a new thread is created in the SMT processor 200, the thread management circuit 205 allocates a group of processing circuits to the newly created thread for use. The allocated processing circuitry may include a program counter 215 , a set of floating point registers 245 , and a set of integer registers 250 . Other processing circuits can also be assigned to newly created threads. It should be appreciated that when a thread completes, processing circuitry allocated for use by that thread may be released so that the processing circuitry may be reassigned to subsequently created threads.

In operation, the instruction fetch circuit 210 fetches an instruction from the instruction cache 220 and provides the instruction to the decoder 225 based on the location provided by the allocated program counter 215 . The decoder 225 outputs the decoded instructions to the register renaming circuit 230 . Depending on the type of instruction provided by register renaming circuit 230 , register renaming circuit 230 provides the renamed instruction to floating point instruction queue 235 or integer instruction queue 240 . For example, if the instruction type provided by the register renaming circuit 230 is a floating-point instruction, the instruction will be loaded into the floating-point instruction queue 235, whereas if the instruction provided by the register renaming circuit 230 is an integer instruction, the instruction will be loaded into the floating-point instruction queue 235. Loaded into the integer instruction queue 240 .

Instructions from floating point instruction queue 235 or integer instruction queue 240 are loaded into an associated register for execution by floating point circuit 255 or integer load/store circuit 260 . In particular, floating point instructions are passed from floating point instruction queue 235 to set of floating point registers 245 . Instructions in floating point registers 245 may be accessed through floating point circuitry 255 . Floating point circuitry 255 may also access floating point data stored in data cache 265 when instructions executed by floating point circuitry 255 (from floating point registers 245 ) involve data stored in data cache 265 , for example.

Integer instructions will be passed from integer instruction queue 240 to integer registers 250 . Integer load/store circuitry 260 may access integer instructions stored in integer registers 250 for execution of the instructions. Integer load/store circuitry 260 may also access data cache 265 when an integer instruction stored in integer register 250 involves integer data stored in data cache 265, for example.

According to an embodiment of the invention, thread management circuitry 205 provides performance metrics to data cache 265 . In particular, the performance indicator may control the data cache 265 to operate at the first performance indicator or the second performance indicator (ie, in a high power mode or a low power mode). For example, thread management circuitry 205 can provide a first performance indicator where data cache 265 is operating in a high power mode, or the thread management circuitry can provide a second performance indicator where data cache 265 is operating in a low power mode. It should be appreciated that although data cache 265 has been described operating at a first performance metric or at a second performance metric, many more performance metrics may be used in accordance with embodiments of the invention.

Figure 3 is a block diagram illustrating an embodiment of a thread management circuit according to the present invention. According to FIG. 3, the thread management circuit 305 receives information from the operating system, or in other words, from the thread generation circuit related to the creation of threads in the SMT processor. The thread management circuit 305 includes a thread allocation circuit 330 capable of allocating processing circuits to threads created by the SMT processor according to the present invention.

Thread management circuitry 305 also includes performance metrics control circuitry 340 that provides performance metrics to processing circuitry associated with threads created by the SMT processor. The performance indicator control circuit 340 can provide the performance indicator to the processing circuit based on the number of threads currently running by the SMT processor. In particular, as the number of threads executed by the SMT processor increases, the performance index control circuit can provide reduced performance index to the processing circuits associated with the threads executed by the SMT. Performance indicator control circuit 340 can determine the number of threads currently running on the SMT processor by incrementing and decrementing an internal count in response to the creation and completion of threads running on the SMT processor.

It should be understood that the performance index provided to the processing circuit according to the present invention may have a default value, such as the first performance index (or high power mode). Thus, as the number of threads increases, the performance metrics provided to the processing circuitry may be reduced, thereby reducing performance, and thus reducing the power consumption of the processing circuitry. It should be appreciated that the performance indicator may be provided to the processing circuit via a signal line capable of conducting a signal having at least two states, namely: a first performance indicator and a second performance indicator. For example, after the SMT processor is initialized, the number of running threads of the SMT processor may be zero, wherein the default value of the performance index provided to the processing circuit is the default first performance index (high power mode). As threads increase and eventually exceed a threshold, the performance indicator may be changed to a second performance indicator, for example, changing the state of a signal indicative of the used performance indicator.

FIG. 4 is a block diagram illustrating an embodiment of a performance index control circuit according to the present invention. According to FIG. 4, the counter circuit 405 may receive information from the operating system or the thread generation circuit discussed in accordance with FIG. 3 to determine the number of threads currently running by the SMT processor. For example, if counter circuit 405 shows four threads started by the SMT processor upon receiving information about the creation of a new thread, counter circuit 405 may increment to reflect that the SMT processor is currently running 5 threads.

The counter circuit 405 may provide the number of threads currently running by the SMT processor to the comparator circuit 410 . Along with the number of threads currently running by the SMT processor, a threshold is also provided to comparator circuit 410 . The threshold may show a programmable value for changes in the number of threads over performance metrics. Therefore, when the number of currently running threads of the SMT processor is less than or equal to the threshold, the performance mode provided to the processing circuit may remain at the first performance index, such as a high power mode. However, when the number of currently running threads of the SMT processor exceeds the threshold, the performance index may be reduced to reduce power consumption of the SMT processor.

FIG. 5 is a flowchart illustrating an embodiment of a performance index control circuit according to the present invention. According to Fig. 5, when initializing SMT processor, the quantity of thread that this SMT processor is running currently is zero (module 500), along with creating and finishing in thread in SMT processor, the thread quantity that is currently running in SMT processor N is incremented or decremented (block 505). For example, in the case of four threads running in an SMT processor, the N value would be 4. When a new thread is created, the N value is incremented to 5, however if a thread is subsequently completed, the N value is decremented back to 4.

The number of threads currently running by the SMT processor is compared to a threshold (block 510). If the number of threads currently running by the SMT processor is less than or equal to the threshold, the performance indicator control circuit provides a first performance indicator to the processing circuit assigned to the thread (block 515). For example, if the processing circuitry assigned to a thread is in accordance with the cache memory discussed in Figure 2, the cache memory can operate such that the tag memory and data memory are accessed synchronously (ie in high power mode). On the other hand, if the number of threads run by the SMT processor is greater than the threshold (block 510), the performance indicator control circuit provides a second performance indicator to the processing circuit associated with the thread (block 520). For example, in the embodiment discussed above with reference to FIG. 2, the cache memory can operate at a second performance index such that the data cache is only accessed in response to hits in the tag memory (i.e., in a low power mode) .

FIG. 6 is a block diagram illustrating an embodiment of the cache memory shown in FIG. 2 in accordance with the present invention. According to FIG. 6 , tag memory 610 is used to store addresses of data stored in data memory 620 . The SMT processor accesses tag memory 610 using addresses associated with available data. The item in the tag memory 610 is compared with the address by the tag comparison circuit 630 to determine whether the data required by the SMT processor is stored in the data memory 620 . If the tag comparison circuit 630 determines that the required data shown by the tag memory 610 is stored in the data memory 620, a tag hit is generated, otherwise a tag miss is generated. The enable output circuit 650 allows data to be output from the data memory 620 if a tag hit occurs.

According to an embodiment of the present invention, the performance index provided by the performance index control circuit is used to control how the tag memory 610 and the data memory 620 operate. In particular, data store enable circuit 640 allows simultaneous access to data store 620 and tag store 610 if a first performance indicator is provided to the cache memory, regardless of whether a tag hit has occurred. In contrast, if the second performance index is provided to the cache memory, the data memory enable circuit 640 does not allow access to the data memory 620 unless a tag hit occurs.

Therefore, according to an embodiment of the present invention, in the high power mode, the tag memory 610 and the data memory 620 may be accessed synchronously to provide improved performance, whereas in the low power mode, only when the tag memory 610 is shown generating Data memory 620 can only be accessed when a tag hit is obtained, thereby allowing the power consumption of the cache memory to be reduced.

Figure 7 is a block diagram illustrating an embodiment used in an instruction cache according to the present invention. According to FIG. 7, the thread management circuit 700 allocates the instruction cache 722 to the new thread. The performance index control circuit included in the thread management circuit 300 can provide the performance index to the instruction cache 722 to control how the instruction cache 722 operates.

In particular, instruction cache 722 is capable of operating in a high power mode in response to a first performance indicator and can be configured to operate in a low power mode in response to a second performance indicator. According to the above description, for example, in FIG. 5 , the first and second performance indicators may be provided to the instruction cache 722 based on the number of threads currently running on the SMT processor. In addition, instruction cache 722 can operate with different performance metrics in a manner similar to that described above with respect to FIG. 6 , where data memory 620 is only accessed in low power mode in response to tag hits. For example, when consecutive memory accesses to the same cache line are determined, different performance metrics may be provided in the instruction cache, allowing direct addressing. This type of restriction can be enforced using a direct addressing cache which allows avoiding reads to tag random access memory (RAM) and also allows tag comparisons to be eliminated. Furthermore, in a direct addressing cache, the translation from virtual address to physical address is also avoided.

Figure 8 is a block diagram illustrating an embodiment of individual processing circuits having different performance metrics in accordance with the present invention. According to FIG. 8, the first floating point circuit 805 is operable to operate at a first performance index, whereas the second floating point circuit 815 is operable to operate at a second performance index less than the first performance index. In other words, the first floating point circuit 805 can be used in high power mode, while the second floating point circuit 815 can be used in low power mode.

The first integer load/store circuit 810 is configured to operate at a first performance specification, whereas the second integer load/store circuit 820 is configured to operate at a second performance specification. Thread management circuit 800 is used to provide two separate performance metrics. In particular, the first performance index is provided to the first floating point circuit 805 and the first integer load/store circuit 810 . The second performance index provided by the thread management circuit 800 is provided to the second floating point circuit 815 and the second integer load/store circuit 820 . Thus, the first floating point circuit 805 and the first integer load/store circuit 810 are assigned to threads running at the first performance index, whereas the second floating point circuit 815 and the second integer load/store circuit 820 are assigned to A thread running at the second performance metric. It should be appreciated that the thread management circuit 800 can provide the first and second performance indicators separately or simultaneously. It should also be appreciated that more than two separate floating point circuits and integer load/store circuits may be provided as an additional performance measure.

According to an embodiment of the present invention, when the number of running threads in the SMT processor is less than or equal to the first threshold, the first performance index can be provided to the first floating point circuit 805 and the first integer load/store circuit 810 . When the number of currently running threads in the SMT processor exceeds the first threshold, a second performance index can be provided to the second floating point circuit 815 and the second integer load/store circuit 820 . Therefore, when the number of threads run by the SMT processor exceeds this threshold, all threads (those previously existing and those newly created) can use the second floating point circuit 815 and the second integer load/store circuit 820 To reduce the power loss of the SMT processor.

It should be appreciated that the floating point circuitry and integer load/store circuitry can operate at different clock speeds and/or use different circuit types (e.g., different types of CMOS devices) to provide different performance metrics in accordance with the present invention . For example, according to some embodiments of the present invention, the floating-point circuit related to the operation of threads in the SMT processor can be based on the number of currently running threads in the SMT processor, in a high power mode or a low clock speed at a high clock speed. Low power mode operation at speed.

FIG. 9 is a block diagram illustrating an embodiment of an SMT processor including multiple processing circuits responsive to individual performance metrics provided by thread management circuit 900 . In particular, thread management circuit 900 provides three separate performance metrics for an instruction cache 930, a data cache 965, first and second floating point circuits 905, 915, and first and second integer/load- Storage circuits 910,920. It should be appreciated that the performance metrics provided to the first and second floating point circuits 905, 915 and to the first and second integer load/store circuits 910, 920 may operate in the manner discussed above with respect to FIG. Furthermore, data cache 965 and instruction cache 930 can operate in the manner discussed above with respect to FIGS. 2 and 7 , respectively.

Therefore, separate performance indicators can be provided to different processing circuits, so that the processing circuits can operate with different performance indicators, thereby providing better control on the trade-off between performance and power consumption. For example, when the data cache 265 and the first and second floating point circuits 905, 915, and the first and second integer load/store circuits 910, 920 are operating at the second performance index, the instruction cache can be at the first A performance index is run. Other combinations of performance metrics may also be used.

FIG. 10 is a block diagram illustrating an embodiment of the performance index control circuit included in the thread management circuit 900 in FIG. 9 . In particular, the performance indicator control circuit includes a counter 1000 that is incremented and decremented in response to threads being created and completed in the SMT processor. First through third registers 1015, 1020, 1025, each capable of storing a separate threshold for the number of threads currently running on the SMT processor. The three comparator circuits 1030, 1035 and 1040 are respectively connected to the corresponding registers 1015, 1020 and 1025. In particular, a first register 1015 storing a first threshold value is connected to a first comparator circuit 1030 . The second register 1020 storing the second threshold value is connected to the second comparator circuit 1035 . A third register 1025 storing a third threshold value is connected to a third comparator circuit 1040 .

Each of the comparator circuits 1030, 1035, 1040 compares the number of threads currently running by the SMT processor with thresholds stored in respective registers. If the first comparator circuit 1030 determines that the number of threads run by the current SMT processor is greater than the first threshold in the first register 1015, then the first comparator circuit 1130 produces a performance index 1045, as shown in Figure 9, the performance index Connect to data cache 965. Therefore, when the number of threads run by the SMT processor exceeds the threshold in the first register 1015, the performance index of the data cache 965 changes from the first performance index to the second performance index (i.e., from high power mode to low power mode ).

If the second comparator circuit 1035 determines that the number of threads currently being run by the SMT processor exceeds the threshold value stored in the second register 1020, the second comparator circuit 1035 generates a performance indicator 1050 that is connected to the instruction cache 930 so that the The performance index of the instruction cache 930 is changed from the first performance index to the second performance index (ie, from the high power mode to the low power mode).

If the third comparator circuit 1040 determines that the number of threads currently being run by the SMT processor exceeds the threshold stored in the third register 1025, the third comparator circuit 1040 generates a signal that is connected to the first and second floating point circuits 905, 915. and the performance index 1055 of the first and second integer/load-store circuits 910,920. Accordingly, the performance specification of these processing circuits is also changed from the first performance specification to the second performance specification (ie from high power mode to low power mode). It should be appreciated that performance indicators 1055 connected to the floating point circuit and the integer load/store circuit operate in the manner described above with respect to FIG. 8 .

FIG. 11 is a flow chart illustrating the method of the embodiment of the performance index control circuit illustrated in FIG. 10 . According to FIG. 11 , when an SMT processor is initialized, the number of threads currently running by the SMT processor is zero (block 1100 ). As threads are created and completed by the SMT processor, the number of threads currently running by the SMT processor is incremented and decremented to provide a value N representing the number of threads currently running by the SMT processor (block 1105).

If the number of threads currently running by the SMT processor is less than or equal to the first threshold (block 1110), all processing circuits continue to run at the first performance index (or high performance index) (block 1115). On the other hand, if the number of threads currently running by the SMT processor exceeds the first threshold (block 1110), the processing circuits connected to the performance index 1045 begin to run at the second performance index (or low performance index) (block 1120) .

If the number of threads currently running by the SMT processor is less than or equal to a second threshold (block 1125), the processing circuitry coupled to performance indicator 1050 (and to performance indicator 1055) begins (or continues) with the first performance indicator operation while the processing circuitry coupled to the performance indicator 1045 (described above) is still operating at the second performance indicator (block 1130).

If the number of threads currently running by the SMT processor exceeds a second threshold (block 1125), the processing circuitry coupled to the performance indicator 1050, along with the processing circuitry coupled to the performance indicator 1045, begin (or continue) to run at the second performance indicator (block 1135), however the processing circuitry coupled to performance indicator 1055 continues to operate at the first performance indicator.

If the number of threads currently being run by the SMT processor is less than or equal to a third threshold (block 1140), the processing circuits connected to the performance index 1055 continue to run with the first performance index, while the processing circuits connected to the performance index 1045 and the performance index 1050 The processing circuit is still operating at the second performance indicator (block 1145). If the number of threads currently running by the SMT processor exceeds a third threshold (block 1140), the processing circuit connected to the performance index 1055 begins (or continues) to run with a second performance index (i.e., in a low power mode) (block 1150 ).

As mentioned above, according to the embodiments of the present invention, processing circuits related to running threads in the SMT processor can be provided, wherein the processing circuits run with different performance indicators based on the number of threads currently running on the SMT processor. For example, according to some embodiments of the present invention, processing circuits related to the execution of threads in an SMT processor, such as floating point units or data caches, can be configured in a high-power mode or Low power mode operation.

Furthermore, as the number of threads run by an SMT processor increases, the performance metrics of the processing circuitry can be reduced, thereby providing the advantages of the SMT processor architecture while allowing a reduction in the amount of power consumed by the processing circuitry associated with the threads . For example, according to some embodiments of the invention, processing circuits according to the invention can operate at different clock speeds and/or use different circuit types (eg, different types of CMOS devices) to provide different performance metrics. For example, according to some embodiments of the present invention, processing circuits related to the running of threads in an SMT processor, such as floating point circuits or data caches, can be clocked at a high clock speed based on the number of threads currently running on the SMT processor. run in high power mode at low clock speeds or in low power mode at low clock speeds.

Numerous changes and modifications may be made by one of ordinary skill in the art, given the presently disclosed advantage, without departing from the spirit and scope of the invention. Accordingly, it should be understood that the foregoing illustrated embodiments are for purposes of example only, and should not be taken to limit the invention as defined by the following claims. Accordingly, to the following claims it is intended that not only combinations of the foregoing literally stated elements be included, but also all combinations for performing substantially the same function in substantially the same way to obtain substantially the same result all equivalent elements. Therefore, the claims should be understood to include what is specifically illustrated and described above, what is conceptually equivalent, and what incorporates the basic principles of the present invention.

Claims (32)

1. A synchronous multi-thread processor, comprising: a performance indicator control circuit for providing a performance indicator for at least one processing circuit based on the number of threads currently running on the SMP; and At least one processing circuit related to the execution of threads in the SMP, and the processing circuit is configured to operate with different performance indicators based on the number of threads currently running on the SMP. 2. The synchronous multi-thread processor according to claim 1, wherein when the number of threads currently running by the synchronous multi-thread processor is less than or equal to a threshold value, at least one processing circuit is configured to operate at a first performance index; and Wherein when the number of currently running threads of the synchronous multi-thread processor is greater than the threshold, at least one processing circuit is configured to run with the second performance index. 3. The synchronous multi-thread processor according to claim 1, wherein when the number of currently running threads of the synchronous multi-thread processor is less than or equal to a threshold value, the performance index control circuit keeps the first provided to at least one processing circuit performance indicators; and Wherein when the number of currently running threads of the synchronous multi-thread processor exceeds the threshold, the performance index control circuit reduces the performance index provided to at least one processing circuit to a second performance index, and the second performance index is less than the set The above-mentioned first performance index. 4. The synchronous multi-thread processor according to claim 3, wherein said threshold comprises a first threshold, wherein when the number of currently running threads of the synchronous multi-thread processor exceeds a second threshold greater than said first threshold, The performance index control circuit further reduces the performance index provided to the at least one processing circuit to a third performance index, the third performance index being less than the second performance index. 5. The synchronous multithreaded processor of claim 1 , wherein at least one of the processing circuits comprises a cache memory circuit comprising a tag memory and a data memory, and when said cache memory is at a first performance index At runtime, the data memory is synchronized with accesses to the tag memory, providing data stored in the cache memory; and Wherein the data memory is configured to provide data stored in the cache memory in response to a hit in the tag memory when the cache memory circuit is operating at a second performance index less than the first performance index. 6. The synchronous multi-thread processor according to claim 5, wherein said cache memory circuit comprises a data cache memory for storing data executed by instructions and an instruction cache memory for instructions storing execution dependent data . 7. The synchronous multi-threaded processor of claim 5 , wherein the data memory is further configured to not provide data stored in the cache memory in response to a miss in the tag memory when operating at a second performance metric . 8. The synchronous multithreaded processor of claim 1, wherein at least one processing circuit includes a floating point unit. 9. The synchronous multi-thread processor according to claim 8, wherein the floating point unit comprises a first floating point unit, and the first floating point unit is used when the number of running threads of the synchronous multi-thread processor is less than or Running with the first performance indicator when equal to the threshold, the synchronous multi-threaded processor further includes: The second floating point unit is configured to run with a second performance index when the number of threads run by the SMP is greater than the threshold, wherein the second performance index is smaller than the first performance index. 10. The synchronous multi-threaded processor of claim 1, wherein at least one processing circuit comprises an integer register. 11. The synchronous multithreading processor according to claim 1, wherein the performance index control circuit is used to determine the synchronous multithreading by increasing or decreasing an internal count in response to creation and completion of threads in the synchronous multithreading processor, respectively. The number of threads currently running on the processor. 12. The synchronous multithreading processor of claim 1 , wherein at least one processing circuit comprises a first processing circuit configured to decrease the number of threads currently running in the synchronous multithreading processor in response to To be less than or equal to the threshold, run with the first performance indicator, the synchronous multi-threaded processor further includes: The second processing circuit is configured to operate at a second performance indicator lower than the first performance indicator in response to the number of threads currently running in the SMP being increased above the threshold. 13. The synchronous multi-thread processor according to claim 1, wherein the performance index control circuit is used to respond to the creation of a new thread, so that the number of currently running threads of the synchronous multi-thread processor increases from less than or equal to a threshold to greater than The threshold is lowered to provide a performance indicator to at least one processing circuit. 14. The synchronous multi-thread processor according to claim 1 , wherein the performance indicator control circuit is configured to set at least The performance index of a processing circuit is sequentially reduced to the descending performance index of its adjacent performance index. 15. The synchronous multi-thread processor according to claim 1, wherein the performance index control circuit is used to maintain a first performance index for the first processing circuit, and in response to the number of currently running threads of the synchronous multi-thread processor is small The equal to or greater threshold increases to greater than the threshold, providing a second performance index less than the first performance index to the second processing circuit. 16. A synchronous multi-threaded processor comprising: a performance indicator control circuit, configured to provide performance indicators to a processing circuit in the synchronous multithread processor based on the number of threads currently running by the synchronous multithread processor, Wherein the performance index control circuit is further used to respond to the creation of a new thread, by increasing the internal count to determine the number of currently running threads of the synchronous multi-threaded processor, thereby providing a new number of running threads, and used for synchronous multi-threading based on The new number of threads run by the thread processor provides performance metrics to the processing circuitry. 17. The synchronous multi-thread processor according to claim 16, wherein when the number of currently running threads of the synchronous multi-thread processor is less than or equal to a threshold value, the performance index control circuit is used to keep the first performance indicators; and When the number of currently running threads of the SMP exceeds the threshold, the performance index control circuit reduces the performance index provided to the processing circuit to a second performance index that is smaller than the first performance index. 18. The synchronous multi-thread processor according to claim 17, wherein the performance index control circuit is further used to maintain a first performance index for the first processing circuit, and responds to the number of currently running threads of the synchronous multi-thread processor Increasing from less than or equal to the threshold to greater than the threshold, a second performance index less than the first performance index is provided to the second processing circuit. 19. The synchronous multithreaded processor of claim 16, wherein the processing circuitry includes at least one of a floating point unit and a data cache. 20. The synchronous multi-thread processor according to claim 16, wherein when the number of threads currently running by the synchronous multi-thread processing circuit is less than or equal to a threshold value, the processing circuit is configured to operate at a first performance index; and When the number of threads currently running by the synchronous multi-thread processing circuit is greater than the threshold, the processing circuit is configured to run with the second performance indicator. 21. A synchronous multi-threaded processor comprising: thread management circuitry for allocating processing circuitry associated with the SMP to threads running in the SMP as threads are created; and Performance indicator control circuitry for providing one of a plurality of performance indicators to the processing circuitry based on the number of threads currently running by the SMP compared to at least one threshold. 22. The synchronous multi-thread processor according to claim 21, wherein when the number of currently running threads of the synchronous multi-thread processor is less than or equal to at least one threshold, the performance index control circuit is used to keep providing a first performance indicator of the circuit; and Wherein when the number of currently running threads of the synchronous multi-thread processor exceeds at least one threshold, the performance index control circuit is configured to reduce the performance index provided to the processing circuit to a second performance index that is less than the first performance index. 23. The synchronous multi-thread processor according to claim 21, wherein the performance indicator control circuit is used to increase the number of currently running threads of the synchronous multi-thread processor from less than or equal to a threshold value to greater than at least one threshold, while degrading the performance index provided to the processing circuit. 24. The synchronous multi-thread processor according to claim 21, wherein the performance index control circuit is used to provide A performance index for the processing circuit is sequentially reduced to the descending performance index of its adjacent performance index. 25. The synchronous multi-thread processor according to claim 21 , wherein the performance index control circuit is used to maintain a first performance index for the first processing circuit, and in response to the number of currently running threads of the synchronous multi-thread processor being small At or equal to at least one threshold is increased to greater than at least one threshold, providing the second processing circuit with a second performance indicator that is less than the first performance indicator. 26. A cache memory associated with the synchronous multithreading processor of claim 1, said cache memory comprising a tag memory and a data memory, both memories being either accessed synchronously, or said data memory being accessed according to the synchronous multithreading The number of threads currently running on the processor is accessed after this tag memory, wherein the tag memory and the data memory are accessed synchronously in response to a number of threads currently running on the SMP being less than or equal to a threshold, The data memory is accessed in response to a hit in the tag memory caused by a number of threads currently running on the SMP being greater than a threshold. 27. A method of operating a simultaneous multithreaded processor, comprising: providing a performance indicator to at least one processing circuit based on the number of threads currently running on the synchronous multithreaded processor, where providing steps takes precedence over: comparing the number of threads currently running by the synchronous multithreaded processor to a threshold, thereby providing a performance indicator for at least one processing circuit, where the compare step takes precedence over: Incrementing the number of threads currently running on the SMP in response to a new thread starting in the SMP; and The number of threads currently running by the SMP is decremented in response to threads ending in the SMP. 28. The method of claim 27, wherein the step of providing comprises: providing the first performance indicator to at least one processing circuit if the number of threads currently running by the SMP is less than or equal to the threshold; and If the number of threads currently running by the SMP exceeds the threshold, providing a second performance index that is less than the first performance index to at least one processing circuit. 29. The method of claim 28, further comprising: A further reduced performance index is provided to the processing circuit in response to the creation of the new thread causing the number of threads currently running by the synchronous multithreaded processor to increase beyond thresholds other than the raised first, second and third thresholds. 30. A synchronous multi-threaded processor comprising: means for providing a performance indicator to at least one processing circuit based on the number of threads currently running on the simultaneous multithreaded processor; means for comparing the number of threads currently running by the synchronous multithreaded processor with a threshold, thereby providing said performance indicator to at least one processing circuit; means for incrementing the number of threads currently running by the SMP in response to a new thread starting in the SMP; and Means for decrementing the number of threads currently running by the simultaneous multithreaded processor in response to a thread terminating in the simultaneous multithreaded processor. 31. The synchronous multithreaded processor of claim 30, wherein the means for providing comprises: means for providing a first performance indicator to at least one processing circuit if the number of threads currently running by the synchronous multithreaded processor is less than or equal to a threshold; and Means for providing a second performance indicator that is less than the first performance indicator to at least one processing circuit if the number of threads currently running by the SMP exceeds a threshold. 32. The synchronous multithreaded processor of claim 31 , further comprising: Means for providing a further reduced performance indicator to a processing circuit in response to the creation of a new thread causing the number of threads currently running by a synchronous multithreaded processor to increase beyond thresholds other than raised first, second and third thresholds .

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