CN100392709C - Plasma display panel and driving method thereof - Google Patents

Abstract

The invention relates to a plasma display panel and its driving method. When the sustain electrode is biased with a predetermined voltage, waveforms for performing reset operation, address operation and sustain operation are applied to the scan electrode, and the positive voltage of the sustain voltage pulse applied to the scan electrode is controlled so that during the sustain period The absolute value can be greater than the absolute value of its negative voltage. Also, when a waveform having a sustain discharge function is applied to the scan electrodes, the address electrodes float, and the voltage of the address electrodes is controlled to increase or decrease according to the voltage of the scan electrodes.

Description

Plasma display panel and driving method thereof

technical field

The present invention relates to a plasma display panel (PDP) driver, a driving method thereof, and a plasma display.

Background technique

A plasma display is a flat panel display using plasma generated through a gas discharge process to display characters or images, on which tens to millions of pixels are provided in a matrix according to its size. Plasma displays are generally classified as DC plasma displays or AC plasma displays according to the provided driving voltage waveform and the structure of discharge cells.

Since DC plasma displays have electrodes arranged in the discharge space, they allow current to flow in the discharge space when a voltage is supplied, and thus they presumably require resistors for limiting the current. On the other hand, since an AC plasma display has electrodes covered by an insulating layer, a capacitance is naturally formed to limit current and protect the electrodes from impact of ions during discharge. Therefore, they have a longer lifetime than DC plasmas.

Figure 1 shows a perspective view of an AC PDP. As shown in the drawing, scan (Y) electrodes 4 and sustain (X) electrodes 5 arranged over insulating layer 2 and protective film 3 are provided in pairs and parallel to each other under first glass substrate 1 . A plurality of address (A) electrodes 8 covered by an insulating layer 7 are mounted on the second glass substrate 6 . On the insulating layer 7 between the address electrodes 8 , barrier ribs 9 parallel to the address electrodes 8 are formed, and phosphors 10 are formed on the surface of the insulating layer 7 between the barrier ribs 9 . The first and second glass substrates 1 , 6 with the discharge space 11 disposed therebetween are provided facing each other so that the scan electrodes 4 and the sustain electrodes 5 may cross the address electrodes 8 , respectively. Address electrode 8 and discharge space 11 formed at the intersection of scan electrode 4 and sustain electrode 5 constitute one discharge cell 12 .

FIG. 2 shows a PDP electrode arrangement diagram of the PDP shown in FIG. 1 . PDP electrodes have an m×n matrix structure. Address (A) electrodes A1 to Am are arranged in the column direction, and scan (Y) electrodes Y1 to Yn and sustain (X) electrodes X1 to Xn are alternately arranged in the row direction. The discharge space 12 shown in FIG. 2 corresponds to the discharge space 12 shown in FIG. 1 .

In the traditional AC PDP driving method, a frame is divided into a plurality of subframes, and includes a reset period, an address period and a sustain period. In the reset period, the discharge cells are reset to stably perform an address operation. In the address period, turned-on cells and non-turned-on cells are selected on the panel, and wall charges are accumulated on turned-on cells, ie, addressed cells. In the sustain period, discharge for actually displaying an image is performed on the addressed cells.

In order to perform the above operations, in the sustain period, sustain discharge pulses are alternately applied to the scan electrodes and the sustain electrodes, and when the sustain electrodes are biased to a predetermined voltage in the reset period and the address period, a reset waveform and a scan electrode are applied to the scan electrodes. waveform. Generally, a scan driving board for driving the scan electrodes and a sustain driving board for driving the sustain electrodes are provided separately, which creates a problem of mounting the driving board on the chassis while increasing costs.

Therefore, a method has been proposed which combines two plates into a single plate to provide it to one side of the scan electrode and extends one end of the sustain electrode to achieve the purpose of merging the plates, but this merging increases The impedance formed on the extended sustain electrode.

In order to solve the above-mentioned problems, Korean Published Patent Application No. 10-2003-90370 discloses a method for supplying a sustain discharge pulse through a scan electrode driver and minimizing the sustain electrode driver.

FIG. 3 shows a conventional PDP driving waveform in a sustain period. During the sustain period, voltages Vs and -Vs for sustain discharge are alternately applied to the scan (Y) electrodes (or sustain (X) electrodes), while the voltage on the sustain electrodes (or scan electrodes) is maintained at the ground voltage.

In this example, when the conditions of all the discharge cells are the same, since little wall charges are accumulated on the cells not selected in the address period, when the voltages Vs and -Vs are applied to the scan electrodes during the sustain period , no discharge is generated between the scan electrodes and the address electrodes of the unselected discharge cells.

However, due to the unstable wall charge state between the discharge cells when the voltages Vs and -Vs are applied to the scan electrodes during the sustain period, there is no cell between the scan electrodes and the address electrodes during the address period. Misfiring may occur.

Therefore, in order to prevent the misfire between the address electrode and the scan electrode in the related art, when the voltage Vs is applied to the sustain electrode, the address electrode floats during the sustain period, or the address voltage Va is applied. to the address electrodes, thereby reducing the voltage difference between the address electrodes and the sustain electrodes.

When positive wall charges are accumulated on the scan electrodes of unselected discharge cells during the address period, and the voltage Vs is applied to the scan electrodes during the sustain period, the prior art described above reduces the contact between the scan electrodes and the address electrodes. pressure difference between. However, when negative wall charges are accumulated on scan electrodes of unselected discharge cells during the address period and a negative voltage -Vs is applied to the scan electrodes during the sustain period, due to the voltage between the scan electrodes and the address electrodes The difference may be greater than the ignition voltage, so misfires may occur.

Contents of the invention

According to the present invention, there is provided a driving waveform for preventing misfiring of a PDP having an integrated board for driving scan (Y) electrodes and sustain (X) electrodes.

In one aspect of the present invention, there is provided a method of dividing one frame into a plurality of subfields and driving a plasma display panel including a plurality of first electrodes, second electrodes and address (A) electrodes. In at least one subfield: (a) when the second electrode is biased by the first voltage, apply a reset waveform to the first electrode to establish a discharge cell to be addressed; (b) when the second electrode is biased When the first voltage is applied, a second voltage is sequentially applied to the first electrode; (c) when the second electrode is biased by the first voltage, a third voltage greater than the first voltage is applied to the first electrode for maintaining discharge; and (d) applying a fourth voltage less than the first voltage to the first electrode for sustain discharge when the second electrode is biased at the first voltage. The absolute difference between the first voltage and the third voltage is larger than the absolute difference between the first voltage and the fourth voltage.

In (c), the voltage of the address electrode is increased to a fifth voltage, while, in (d), the voltage of the address electrode is maintained to a sixth voltage less than the fifth voltage.

A fifth voltage and a sixth voltage are applied to the address electrodes, respectively, and the address electrodes float in (c) and (d).

In another aspect of the present invention, a method of driving a plasma display panel including a first electrode, a second electrode and an address electrode is provided. During the sustain period, when the second electrode is biased to the first voltage, a second voltage greater than the first voltage is applied to the first electrode; at the same time, when the second electrode is biased to the first voltage, the second voltage less than the first voltage A third voltage is applied to the first electrode. The fourth voltage, which is the address electrode voltage when the second electrode is applied to the first electrode, does not correspond to the fifth voltage, which is the address electrode voltage when the third voltage is applied to the first electrode. An absolute difference in voltage between the first voltage and the second voltage is greater than an absolute difference in voltage between the first voltage and the third voltage.

The fourth voltage is greater than the fifth voltage, and the address electrodes float.

In yet another aspect of the present invention, a plasma display panel having a panel and a driving circuit is provided. The panel includes a plurality of first electrodes, second electrodes and address electrodes, and the drive circuit alternately applies a positive first voltage and a negative second voltage to the first electrodes during the sustain period, and controls when the first voltage is applied to The voltage of the address electrode when the first electrode is made larger than the voltage of the address electrode when the second voltage is applied to the first electrode, and the absolute value of the negative second voltage is smaller than the absolute value of the positive first voltage. The driving circuit maintains the voltage of the second electrode to the ground voltage, the address electrode floats, and maintains the voltage of the second electrode to the ground voltage during the reset period and the address period.

In still another aspect of the present invention, a method of dividing a frame into a plurality of subfields and driving a plasma display panel including a plurality of first electrodes, second electrodes and third electrodes is provided. In at least one subfield, the discharge cell to be turned on is selected during the address period, and when the first electrode is biased to the first voltage during the sustain period, there will be a second voltage greater than the first voltage and a second voltage less than the first voltage A third voltage is alternately applied to the second electrodes. When a third voltage is applied to the second electrode during the sustain period, the third plate floats. The fourth voltage is applied to the third electrodes of the discharge cells to be turned on, and the fifth voltage less than the fourth voltage is applied to the third electrodes of the discharge cells not turned on during the address period, and when the third While the electrodes are floating, the third electrode is disconnected from the power supply for supplying the fifth voltage.

Description of drawings

Figure 1 shows a perspective view of an AC PDP.

FIG. 2 shows an electrode arrangement diagram of a PDP.

FIG. 3 shows driving waveforms of a conventional PDP during a sustain period.

FIG. 4 shows a PDP according to an exemplary embodiment of the present invention.

FIG. 5 shows PDP driving waveforms according to the first exemplary embodiment of the present invention.

6 illustrates sustain (X), scan (Y) and address (A) electrodes, and an address selection circuit coupled to the address electrodes, according to a first exemplary embodiment of the present invention.

7A and 7B illustrate the wall charge states of the driving waveform discharge cells according to the first exemplary embodiment of the present invention.

FIG. 8 shows PDP driving waveforms according to a second exemplary embodiment of the present invention.

FIG. 9 shows an address selection circuit according to a second exemplary embodiment of the present invention.

FIG. 10 shows PDP driving waveforms according to a third exemplary embodiment of the present invention.

FIG. 11 shows an address selection circuit according to a third exemplary embodiment of the present invention.

Detailed ways

Referring to FIG. 4 , a PDP according to an exemplary embodiment of the present invention includes a plasma panel 100 , an address (A) electrode driver 200 , a sustain scan (XY) electrode driver 320 and a controller 400 .

The plasma panel 100 includes a plurality of address (A) electrodes A1 to Am arranged in a column direction, and a plurality of first electrodes Y1 to Yn (also generally referred to as Y electrodes) and second electrodes X1 to Am arranged in a row direction. Xn (also collectively referred to as X electrode).

The address electrode driver 200 receives an address driving control signal S _A from the controller 400 , and applies a display data signal for selecting a discharge cell to be displayed to a corresponding address electrode according to an image signal applied to the controller 400 .

A sustain scan (XY) electrode driver 320 receives an XY electrode driving signal S _XY from the controller 200 and applies the signal to the X and Y electrodes. The controller 400 receives an external image signal, generates an address driving control signal S _A and an XY electrode driving signal S _xy , and distributes the signals S _A and S _xy to the address electrode driver 200 and the sustain scan (XY) electrode driver 320 .

A PDP driving method will be described below with reference to FIG. 5, which shows driving waveforms applied to a PDO according to a first exemplary embodiment of the present invention. The subfield includes a reset period, an address period, and a sustain period, and the voltage of the sustain (X) electrode is maintained at 0 volts during the reset period, the address period, and the sustain period.

During the reset period, the voltage Vs is applied to the scan (Y) electrodes, and a voltage gradually rising to the voltage Vset is applied to the scan electrodes. A weak discharge is generated between the scan electrodes and the sustain electrodes to form negative wall charges on the scan electrodes and positive wall charges on the sustain electrodes. The voltage of the scan electrode is reduced to the voltage Vs, and a voltage gradually falling to the voltage -Vnf is applied to the scan electrode. A weak discharge is generated between the scan electrodes and the sustain electrodes to eliminate most of the negative wall charges formed on the scan electrodes and the positive wall charges formed on the sustain electrodes.

During the address period, instead of applying a bias voltage to the X electrode, the level of the scan voltage applied to the Y electrode is subtracted from the bias voltage applied to the X electrode during the address period, so that the X electrode and the Y electrode The voltage of the electrodes is maintained at 0 volts, and the voltage difference between the X electrode and the Y electrode is maintained.

That is, in the case of the unselected scan electrode bias voltage -VscH, the voltage -VscL is applied to the selected scan electrode, and the positive voltage Va is applied to the address (A) electrode, which addresses (A) The electrodes pass through the discharge cells to be turned on from among the discharge cells formed on the selected scan electrodes. A discharge is generated between the address electrode applied with the voltage Va and the scan electrode applied with the voltage -VscL, and between the scan electrode and the sustain electrode, thereby forming wall charges for the sustain discharge during the sustain period.

During the sustain period, pulses having voltages +Vs1 and -Vs2 are alternately applied to the scan electrodes to generate a sustain discharge between the scan electrodes and the sustain electrodes, and the address electrodes float during the sustain period.

In the case where the absolute values of the voltages +Vs1 and -Vs2 are comparable to each other, when negative wall charges are accumulated on the scan electrodes of unselected discharge cells during the address period, and the negative voltage -Vs is applied to the scan electrodes during the sustain period When the electrode is connected, because the voltage difference between the scan electrode and the address electrode is greater than the ignition voltage, misfire occurs.

Therefore, as shown in FIG. 5, when the voltage difference between the voltages +Vs1 and -Vs2 is maintained at 2 volts, the voltage +Vs1 is established such that its absolute value is greater than the absolute value of the voltage -Vs2.

Referring to FIGS. 6 and 7, when the address electrode is floating during the sustain period, the output waveform of the address (A) electrode will be described in more detail.

6 illustrates sustain (X) electrodes, scan (Y) electrodes, address electrodes, and an address selection circuit coupled to the address electrodes according to a first exemplary embodiment of the present invention. 7A and 7B illustrate wall charge states of discharge cells according to driving waveforms according to the first exemplary embodiment of the present invention. The address selection circuit of FIG. 6 includes a driving transistor AH and a ground transistor AL, each having a body diode.

As shown in Figure 6, since the panel capacitance is formed between the scanning (Y) electrode and the addressing (A) electrode, when the output of the addressing electrode is floating during the sustain period, when the voltage +Vs1 is applied to the scanning electrode, the scanning The potential of the electrodes increases, and the potential of the address electrodes increases. When the potential of the addressing electrode increases to be greater than the voltage Va, the voltage of the addressing electrode is fixed at the voltage Va by the body diode of the drive transistor AH of the addressing selection circuit (as given by path (1) in FIG. 6 ). . Therefore, when the voltage of the scan electrode is increased to be greater than the voltage Va, the voltage of the address electrode is maintained at the voltage Va.

In this case, since when positive wall charges are accumulated on the scan electrodes of unselected discharge cells during the address period and a voltage +Vs1 greater than the voltage Vs is applied to the scan electrodes during the sustain period, the address The voltage of the electrode floats at the voltage Va, so the difference between the voltage Va of the address electrode and the sum of the wall voltage Vw1 of the scan electrode and the voltage +Vs1 applied to the scan electrode is reduced to less than that between the address electrode and the scan electrode The ignition voltage Vf, and therefore does not produce misfire (as shown in Figure 7A). Meanwhile, since the voltage of the scan electrode is reduced due to the bias of the negative wall charges and the voltage +Vs1 is applied to the scan electrode when the negative wall charges are accumulated on the scan electrode, no ignition is generated between the scan electrode and the address electrode. bad.

Further, when the voltage -Vs2 is applied to the scan electrodes in a case where the output of the address electrodes is floating during the sustain period, the potential of the scan electrodes is lowered, and the potential of the address electrodes is also lowered. When the potential of the address electrode is lowered to less than 0V, the voltage of the address electrode through the body diode of the drive transistor AL of the address selection circuit is fixed at 0V (as shown in path (2) of FIG. 6 ). Therefore, when the voltage of the scan electrode is lowered to less than 0V, the voltage of the address electrode is maintained at 0V.

In this case, since negative wall charges are accumulated on the scan electrodes of unselected discharge cells during the address period and the voltage -Vs2 is applied to the scan electrodes during the sustain period, the absolute value of the voltage -Vs2 The value is smaller than the voltage Vs, so the difference between the wall pressure Vw1 of the scan electrode and the voltage -Vs2 applied to the scan electrode is smaller than the ignition voltage Vf between the address electrode and the scan electrode, and thus does not cause misfire (as shown in Figure 7B shown). Meanwhile, since the voltage of the scan electrode is reduced due to the bias of the positive wall charges and the voltage -Vs2 is applied to the scan electrode when the positive wall charges are accumulated on the scan electrode, no voltage is generated between the scan electrode and the address electrode. Poor ignition.

The voltage +Vs1 is less than the firing voltage between the sustain electrode and the scan electrode, so that unaddressed discharge cells do not generate a sustain discharge during the address period. Also, the voltage -Vs2 must have a value such that the voltage -Vs2 together with the wall charges of the address discharge cells can generate a discharge. In this case, the voltages +Vs1 and -Vs2 can be controlled within a range in which the difference between the voltages +Vs1 and -Vs2 corresponds to the difference between the conventional voltages +Vs and -Vs.

According to the first exemplary embodiment, the address electrodes float during the sustain period. In addition, when the voltage pulse +Vs1 is applied to the scan electrodes during the sustain period, the address electrodes may float, and unlike this, the voltage pulse Va may be directly applied to the address electrodes.

In the first exemplary embodiment, when the drive waveform is applied to the scan electrodes, the sustain electrodes are biased at 0V. In addition, it is also possible to bias the sustain electrodes to another voltage and modify the drive waveform of the scan electrodes so that it is different from other voltages. The voltage is the same as the difference between 0V.

Furthermore, in the first exemplary embodiment, the voltages -Vs2 and +Vs1 are alternately applied to the scan electrodes during the sustain period, and in addition, it is possible to increase the voltage of the scan electrodes from the voltage -Vs2 to 0V, and to increase the voltage from 0V to Increase to +Vs1, decrease voltage from +Vs1 to 0V, and decrease voltage from 0V to -Vs2.

In the first exemplary embodiment, the voltages -Vs2 and +Vs1 are alternately applied to the scan electrodes during the sustain period, and in addition, it is possible to alternately apply the voltages Vs and -Vs to the scan electrodes during the sustain period, and when the voltage - When Vs is applied to the scan electrodes, the address electrodes float.

FIG. 8 shows driving waveforms of a PDP according to a second exemplary embodiment of the present invention. Pulses with voltages Vs and -Vs are alternately applied to the scan (Y) electrodes during the sustain period, and when the voltage -Vs is applied to the scan electrodes, the address (A) electrodes float. Since a capacitive element is formed by the address electrodes and the scan electrodes, when the voltage of the scan electrodes is lowered and the address electrodes are floating, the voltage of the address electrodes is lowered together with the voltage of the scan electrodes. Then, when the voltage -Vs is applied to the Y electrodes, since the voltage between the address electrodes and the scan electrodes is lowered to be smaller than that in the case where the voltages Vs and -Vs are alternately applied to the scan electrodes, the scan electrodes are avoided. Misfiring to and from address electrodes of cells not selected during the address period.

When the voltage -Vs is applied to the scan electrodes during the sustain period, and the address electrodes are floating as shown in Figure 8, the voltage of the address electrodes follows the voltage of the scan electrodes to decrease, and when the voltage of the address electrodes decreases to less than the ground voltage When , the voltage of the address electrode is fixed at the ground voltage through the body diode of the transistor AL of the address selection circuit. Thus, the voltage of the address electrode does not drop below the ground voltage, and therefore, since the driving waveform corresponds to that of FIG. 3, the driving waveform shown in FIG. 8 is not provided.

Thus, in the second exemplary embodiment, the switch SW1 is coupled between the transistor AL and the ground voltage GND. FIG. 9 shows an address selection circuit according to a second exemplary embodiment of the present invention. The switch SW1 is coupled between the address selection circuit and the ground voltage 0V. When the voltage -Vs is applied to the scan (Y) electrode and the address (A) electrode is floating during the sustain period, the switch SW1 is closed to cut off the address electrode from the ground voltage 0V and allow the voltage of the address electrode to follow the voltage of the scan electrode reduce.

In the second exemplary embodiment, when the voltage -Vs is applied to the scan electrodes during the sustain period, the voltage of the address electrodes is lowered to a negative voltage, thereby reducing the voltage between the scan electrodes and the address electrodes. poor, thereby avoiding the occurrence of misfiring of unselected discharge cells during the address period.

According to the second exemplary embodiment, since the driving waveform floats the address electrodes when the voltage -Vs is applied to the scan electrodes, the switch SW1 is repeatedly turned on and off, thereby increasing power consumption. Meanwhile, when the voltage Vs is applied to the scan electrodes to generate a discharge, electrons move to the scan electrodes and positive ions move to the address electrodes. In order to express color, the addressing electrode is coated with a fluorescent layer, and positive ions hit the surface of the fluorescent layer, which reduces the lifetime of the fluorescent layer.

Thus, a method for solving the above-mentioned problems will now be described with reference to FIG. 10, which shows a PDP driving waveform according to a third exemplary embodiment of the present invention. When the voltage Vs is applied to the scan electrodes during the sustain period in the third exemplary embodiment, the address (A) electrodes float. That is, during the sustain period, the address electrodes float, and sustain discharge pulses having voltages Vs and -Vs are alternately applied to the scan electrodes.

When the voltage Vs is applied to the scan electrodes and the address electrodes float, the voltage of the address electrodes increases according to the voltage of the scan electrodes. Then, the potential of the address electrode increases, and a large amount of positive ions move to the sustain (X) electrode after the sustain discharge, thereby protecting the phosphor layer coating the address electrode.

According to the third exemplary embodiment, when a driving waveform is generated by using the general address selection circuit shown in FIG. 6, the voltage of the address (A) electrode increases according to the voltage of the address electrode fixed at the voltage Va.

Therefore, in a manner similar to the third exemplary embodiment, in order to supply a voltage greater than the voltage Va to the address electrodes, the path of the voltage Va and the address electrodes are cut off.

FIG. 11 shows an address selection circuit according to a third exemplary embodiment of the present invention. The address selection circuit according to the third exemplary embodiment is the same as the address selection circuit shown in FIG. 9 except that the switch SW2 is coupled between the voltage Va and the address IC.

A method of applying a driving waveform through an address selection circuit according to a third exemplary embodiment is described below.

When the address (A) electrode is floating and the voltage Vs is applied to the scan (Y) electrode by closing the switches SW1 and SW2, the voltage of the address electrode is increased to a positive voltage, and when the voltage Vs is applied to the scan electrode, the address The voltage of the electrodes drops to a negative voltage. In this case, since the switches SW1 and SW2 are closed and the address electrodes intercept the 0V voltage and Va, a voltage greater than Va is applied to the scan electrode when the voltage Vs is applied, and a voltage less than 0V is applied when the voltage -Vs is applied. applied to the scan electrodes.

As described above, by biasing the sustain electrodes to a predetermined voltage, eliminating the sustain (X) electrode driving plate, applying a driving waveform to the scan electrodes, thereby performing a reset operation, an address operation, and a sustain discharge operation. Simultaneously, since the pulse for sustain discharge is applied to the scan electrode driving board, the impedance on the path through which the sustain discharge pulse is applied is established as a constant value.

As shown in the first to third exemplary embodiments, reset periods of subfields forming a frame may respectively have rising periods and falling periods, and also, reset periods of some subfields may respectively have falling periods.

The sustain electrodes are biased at a predetermined voltage throughout the driving cycle, but the invention is not limited thereto.

According to the present invention, when the sustain electrodes are biased to a constant voltage, the sustain electrode driving plate is removed since the driving waveform is applied to the scan electrodes.

Furthermore, by controlling the absolute value of the positive voltage of the sustain voltage pulse applied to the scan electrode (or sustain electrode) during the sustain period to be greater than the absolute value of the negative voltage, the unselected discharge in the address period is solved The misfiring of the cell reduces the voltage difference between the address electrode and the scan electrode (or sustain electrode).

The misfire of the sustain period is prevented by addressing the electrode floating in the sustain period, and a switch is added between the respective power supplies to provide address voltage and non-address voltage and an address IC for the address electrode in the address period , and when the address electrode floats during the sustain period, the voltage is increased to be greater than the address voltage or decreased to be less than the address voltage.

It will be understood by those skilled in the art that various modifications and changes can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers modifications and variations thereof without departing from the scope defined by the appended claims and their equivalents.

Claims (28)

1. one kind is divided into a frame a plurality of sons and it is carried out method of driving in plasma display panel, and described plasma display panel has a plurality of first electrodes, second electrode and addressing electrode, and described method comprises:

In at least one height field,

(a) when second electrode is setovered first voltage, apply reset wave to first electrode to set up with the discharge cell that is addressed;

(b) when second electrode is setovered first voltage, order applies second voltage to first electrode;

(c) when second electrode is setovered first voltage, apply tertiary voltage greater than first voltage to first electrode to keep discharge; With

(d) when second electrode is setovered first voltage, apply less than the 4th voltage of first voltage to first electrode keeping discharge,

Wherein, the absolute difference between first voltage and the tertiary voltage is greater than the absolute difference between first voltage and the 4th voltage.

2. apply voltage to the five voltages that tertiary voltage comprises increases addressing electrode according to the process of claim 1 wherein, and apply the 4th voltage and comprise that voltage with addressing electrode maintains the 6th voltage less than the 5th voltage.

3. according to the method for claim 2, wherein apply tertiary voltage and apply the 4th voltage and comprise respectively the 5th voltage and the 6th voltage are applied to addressing electrode.

4. comprise that according to the process of claim 1 wherein to apply tertiary voltage and apply the 4th voltage addressing electrode floats.

5. according to the process of claim 1 wherein that first voltage is ground voltage.

6. according to the method for claim 5, wherein the 6th voltage is ground voltage.

7. according to the method for claim 2, wherein the 6th voltage is suitable with first voltage.

8. a driving comprises the method for the plasma display panel of a plurality of first electrodes, second electrode and addressing electrode, comprising:

During the cycle of keeping,

When second electrode is setovered first voltage, apply second voltage greater than first voltage to first electrode; And

When second electrode is setovered first voltage, apply tertiary voltage less than first voltage to first electrode,

Wherein, different as the 4th voltage of addressing electrode voltage when second voltage is applied to first electrode with the 5th voltage when tertiary voltage is applied to first electrode as addressing electrode voltage, and

Absolute difference between first voltage and second voltage is greater than the absolute difference between first voltage and the tertiary voltage.

9. method according to Claim 8, wherein the 4th voltage is greater than the 5th voltage.

10. method according to Claim 8, wherein first voltage is ground voltage.

11. method according to Claim 8, wherein addressing electrode floats.

12. method according to Claim 8, wherein during reset cycle and addressing period, second electrode is biased first voltage.

13. a plasma display panel comprises:

Panel with a plurality of first electrodes, second electrode and addressing electrode; And

Driving circuit, second voltage that is used for alternately applying the first positive voltage during the cycle of keeping and bears is to first electrode, and when the first positive voltage is applied to first electrode, the voltage of control addressing electrode, make its voltage greater than addressing electrode when second voltage that will bear is applied to first electrode, the absolute value of the second negative voltage is less than the absolute value of the first positive voltage.

14. according to the plasma display panel of claim 13, wherein driving circuit maintains ground voltage with the voltage of second electrode.

15. according to the plasma display panel of claim 13, the driving circuit addressing electrode that floats wherein.

16. according to the plasma display panel of claim 13, wherein driving circuit maintains ground voltage with the voltage of second electrode during reset cycle and addressing period.

17. a method that a frame is divided into a plurality of son and drives above-mentioned frame in plasma display panel, described plasma display panel has a plurality of first electrodes, second electrode and third electrode, and described method comprises:

In at least one height field,

During addressing period, select the discharge cell that is switched on; And

When during first electrode is being kept the cycle, being biased first voltage, alternately apply greater than second voltage of first voltage and less than the tertiary voltage of first voltage to second electrode,

Wherein, when during the cycle of keeping tertiary voltage being applied to second electrode, third electrode floats.

18. according to the method for claim 17, wherein, during addressing period, the 4th voltage is applied to the third electrode of the discharge cell that will be switched on, and will be applied to the third electrode of the discharge cell that will not arrived less than the 5th voltage of the 4th voltage, and

When third electrode floated, third electrode disconnected from the power supply that applies the 5th voltage.

19. according to the method for claim 18, wherein third electrode floated during the cycle of keeping.

20. according to the method for claim 19, wherein, when during the cycle of keeping second voltage being applied to second electrode, third electrode disconnects from the power supply that applies the 4th voltage.

21. according to the method for claim 17, wherein, during reset cycle and addressing period, first electrode is biased first voltage.

22. according to the method for claim 21, wherein first voltage is ground voltage.

23. according to the method for claim 18, wherein the 5th voltage is ground voltage.

24. a plasma display panel comprises:

Have a plurality of first electrodes, second electrode, and with the panel of the third electrode of first and second electrode crossing;

A plurality of selection circuit are used for optionally applying the third electrode of first voltage to the discharge cell that will be switched on during addressing period, and apply second voltage less than first voltage to the third electrode that will not be switched on; And

Driving circuit, be used for during the cycle of keeping, when the voltage of second electrode maintains tertiary voltage, alternately apply greater than the 4th voltage of tertiary voltage and less than the 5th voltage of tertiary voltage to first electrode, and when the 5th voltage was applied to first electrode, third electrode floated.

25. according to the plasma display panel of claim 24, wherein each selects circuit to comprise:

Be coupled in and be used to apply first power supply of first voltage and the first transistor between the third electrode; And

Be coupled in and be used to apply the second source of second voltage and the transistor seconds between the third electrode,

Wherein plasma display panel further comprises first switch that is coupled between transistor seconds and the second source, and closes when third electrode floats.

26. according to the plasma display panel of claim 25, further comprise the second switch that is coupled between the first transistor and first power supply,

Wherein keeping the unsteady third electrode of cycle drive circuit, and when applying the 4th voltage during the cycle of keeping, closing second switch to first electrode.

27. according to the plasma display panel of claim 24, wherein second electrode is biased tertiary voltage during reset cycle and addressing period.

28. according to the plasma display panel of claim 27, wherein tertiary voltage is a ground voltage.

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