CN100388699C - Discrete Fourier Transform Device in Asymmetric Digital Subscriber Loop System - Google Patents

Abstract

The present invention provides the discrete Fourier transform device in the ADSL system, can be used for the modulation and the demodulation of 256 channels, finishes the DFT (I-DFT and F-DFT) processing of 512 points, comprises 1 dual-port RAM12, Twiddle factor module 14, timing control module 10, read-write address generation module 11 and butterfly operation module 13; after the data of front-stage input dual-port RAM A is ready, timing control module 10 starts read-write address generation module 11 to start reading Write data and twiddle factor, butterfly operation module 13 utilizes Hermitian symmetry algorithm to carry out butterfly operation according to data and twiddle factor, intermediate data is stored in the dual-port RAM12; The present invention adopts the mode of serial processing, only needs to use less The hardware can be realized, which solves the problem of shortage of hardware resources; in addition, the Hermitian algorithm is used to further simplify the calculation of discrete Fourier transform, reducing the amount of calculation by nearly 50%.

Description

Discrete Fourier Transform Device in Asymmetric Digital Subscriber Loop System

technical field

The present invention relates to the field of data communication, in particular to a discrete Fourier transform (DFT) device in an asymmetrical digital subscriber loop (ADSL for short) system.

Background technique

The ADSL system adopts advanced digital modulation and signal processing technology. While transmitting telephone services on ordinary telephone lines, it provides high-speed broadband data services and video services with up to 640kbit\s and 8Mbit\s speeds at the same time. Its key technology Discrete Multi-Tone (DMT) modulation technology in high-speed channels. In the ADSL system, the 1MHz bandwidth is divided into 256 sub-channels through DMT technology, and the bandwidth of each sub-channel is 4.3125kHz, and then according to the channel attenuation characteristics and noise conditions, the input data is adaptively allocated to each sub-channel.

The structural diagram of the DMT system in the ADSL system is shown in Figure 1, and the direction of the arrow is the transmission direction of the data. In the modulation direction, the signal to be sent is modulated by inverse discrete Fourier transform (I-DFT) after bit allocation, constellation coding and gain adjustment, and the modulated signal is sent out after adding cyclic prefix and clipping processing ; In the demodulation direction, the received signal is firstly subjected to time domain equalization and decyclic prefix, demodulated by forward discrete Fourier transform (F-DFT), and then frequency domain equalization, constellation decoding and bit demodulation. In fact, demodulation is the inverse process of modulation, among which discrete Fourier transform DFT (I-DFT, F-DFT) is the key to complete the modulation and demodulation of 256 channels. According to the regulations of the American National Standard ANSIT1.413, a frame period is 68/69*250≈246μs, and the time for a 512-point DFT process must be less than a frame period.

In order to improve the operation speed, the current DFT device generally adopts a parallel processing method, that is, each butterfly operation unit of the N-point DFT performs operation at the same time. If the conventional time decimation (DIT) or frequency decimation (DIF) method is used for N-point FFT butterfly operation, 6Nlog ₂ ^2N real number adders and 4Nlog ₂ ^2N real number multipliers are required, which will take up considerable hardware resources , is a major disadvantage of hardware implementation. In order to save hardware, US Patent 6,157,938 "FAST FOURIER TRANSFORMDEVICE AITH PARALLEL LATTICE ARCHITECTURE" proposes a new fast Fourier transform device. Figure 2 is a schematic diagram of the above-mentioned fast Fourier transform device in the DMT system, which converts the parallel N frequency domain data into 2N data through conjugation, and then obtains 2N data through inverse fast Fourier transform (IFFT) operation data, and then convert it into time-domain data in parallel and serial, and the 2N time-domain data flows through the transmission channel undergo serial-to-parallel conversion, and then perform fast Fourier transform (FFT) operation on the serial-to-parallel converted data to obtain The first N frequency domain data. Figure 3 is the structure diagram of the IFFT proposed by the above-mentioned US patent. The multiplication processing module 1 performs multiplication processing on N data at the same time, and obtains two sets of data MDCT and MDST respectively, and then after the circuit expansion module 2 and the left shift module, 2N data are obtained. Data after IFFT. From this, it can be known that using this US patent to process IFFT requires 4(N-1) real number multipliers and [5(N-1)+2] real number adders, which still requires more hardware resources. In the ADSL system, since there are many modules involved in DMT, how to save hardware resources becomes one of the most important issues, and the existing technology cannot meet the requirements well, so there is an urgent need for DFT devices suitable for ADSL systems to achieve effective The purpose of controlling hardware resources and quickly completing modulation and demodulation in real time.

Contents of the invention

The technical problem to be solved by the present invention is to provide the discrete Fourier transform device in the ADSL system, which can be used for the modulation and demodulation of 256 channels in the DMT system, and completes the DFT (I-DFT and F-DFT) processing of 512 points .

The discrete Fourier transform device of the present invention includes a dual-port RAM, a twiddle factor module, a timing control module, a read-write address generation module and a butterfly operation module;

The dual-port RAM: under the control of the read-write address generation module, reads and writes the intermediate operation data of the butterfly operation module;

The twiddle factor module: used to store the twiddle factor W _2N ^±k required in the butterfly operation process, which is read by the read-write address generation module and output to the butterfly operation module;

The timing control module: used to control the reading and writing of the reading and writing address generation module, and control the working timing of each module;

The read-write address generation module: controlled by the timing control module, reads the data in the dual-port RAM and the external dual-port RAM A, and the twiddle factor in the twiddle factor module is given to the butterfly operation module, and control calculation results are written in the dual-port RAM and the external dual-port RAM C;

The butterfly calculation module: used to perform butterfly calculations based on the data and twiddle factors using the Hermitian symmetric algorithm, and the obtained calculation results are written into the dual-port RAM and external memory under the control of the read-write address generation module In the dual-port RAM C.

The discrete Fourier transform device of the present invention adopts the mode of serial processing, only needs to use less hardware to realize, saves 511 complex number multipliers and a plurality of adders compared with existing DFT device, thus solves the problem of In addition, using the conjugate symmetry of the system, the calculation of the 512-point discrete Fourier transform is further simplified by using the Hermitian algorithm, which reduces the calculation amount by nearly 50%, saves the calculation time, and reduces the power consumption. consumption.

Description of drawings

Fig. 1 is a structural block diagram of the DMT system in the ADSL system.

Fig. 2 is a schematic diagram of FFT (I-FFT, F-FFT) of US Patent 6,157,938 in a DMT system.

FIG. 3 is a circuit structure diagram of the FFT in FIG. 2 .

Fig. 4 is a schematic diagram of the discrete Fourier transform device of the present invention in a DMT system.

Fig. 5 is a schematic structural diagram of the discrete Fourier transform device of the present invention.

FIG. 6 is a processing flowchart of the inverse discrete Fourier transform (I-DFT) device in FIG. 4 .

FIG. 7 is a processing flowchart of the forward discrete Fourier transform (F-DFT) device in FIG. 4 .

Fig. 8 is a schematic diagram of the butterfly operation rule used in the preprocessing process.

Fig. 9 is a schematic diagram of the butterfly operation rules of each stage of the inverse fast Fourier transform.

FIG. 10 is a circuit diagram of the butterfly operation module 13 in FIG. 5 .

FIG. 11 is an internal structure diagram of the butterfly operation unit 300 in FIG. 10 .

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

The DMT system in the ADSL system includes two directions of modulation and demodulation, as shown in Figure 1. In the modulation direction, the data to be sent is first allocated to bits, and the data of different bits is allocated to 256 channels according to the transmission performance of the channel. After the bit allocation, the data is constellation coded, and then its gain is adjusted. , and then modulate the signal to 256 channels through I-DFT, and then send it out after processing such as adding cyclic prefix and clipping; The signals of each channel are processed and demodulated by F-DFT, and then frequency-domain equalization, constellation decoding, bit de-allocation and other processing are performed on it to complete the DMT demodulation. It can be seen from the above process that demodulation is the reverse process of modulation.

Figure 2 and Figure 3 are structural diagrams of the US patent, which have been introduced in detail above, and it can be seen that this patent uses parallel processing to complete the IFFT (FFT) process, which requires more hardware resources.

Fig. 4 is the schematic diagram of the present invention in the DMT system, the frequency domain data X(k) after the gain adjustment is stored in the gain adjustment RAM successively, after the data of 256 channels all finish the gain adjustment, read out X(k) successively ), X(N-k) perform 512-point I-DFT calculations, where N=512/2=256, indicating the number of channels. The calculated time-domain signal is output to the cyclic prefix RAM and buffered to complete the data modulation of 256 channels. The modulated signal is transmitted through the transmission channel. On the receiving side, after the time-domain data of one frame after removing the cyclic prefix is ready, read the time-domain data in the RAM of the de-cyclic prefix in sequence to perform F-DFT operation, and finally output the obtained frequency-domain signal to the frequency-domain equalization RAM. Complete the data demodulation of 256 channels.

5 is a structural diagram of the discrete Fourier transform device of the present invention, including a dual-port RAM 12 , a twiddle factor module 14 , a timing control module 10 , a read-write address generation module 11 and a butterfly operation module 13 . Since each butterfly operation of each stage is applicable to the same address operation rule, only one dual-port RAM 12 can be used to complete the reading and writing of the intermediate data of the butterfly operation. The twiddle factor module 14 stores the twiddle factor W _2N ^±k required in the butterfly operation, and outputs it to the butterfly operation module 13 under the control of the read-write address generation module 11 . The timing control module 10 starts the reading and writing address generation module 11 to read and write data after the data input to the dual-port RAM A in the previous stage is ready, and also controls the working timing of each module. The read-write address generation module 11 is controlled by the timing control module 10, reads data at different addresses in different RAMs and the corresponding twiddle factors in the twiddle factor module 14 at different times, and writes the butterfly operation results into corresponding RAMs. The butterfly operation module 13 performs butterfly operation according to the data and the twiddle factors. The read-write address generation module 11 and the butterfly operation module 13 are also connected to the external dual-port RAM A and dual-port RAM C.

The dual-port RAM A is the cache of the input data of the previous stage. In the modulation direction, the dual-port RAM A is the gain adjustment RAM in Figure 4. In the demodulation direction, the dual-port RAM A is the decyclic prefix RAM in Figure 4. The dual-port RAMC is to store the operation result of the DFT operation to the last stage. The dual-port RAM C in the modulation direction is the cyclic prefix RAM in Figure 4, and the dual-port RAM C in the demodulation direction is the frequency domain equalization RAM in Figure 4.

Since demodulation is the inverse process of modulation, the I-DFT for modulation and the F-DFT for demodulation can adopt the same structure as shown in FIG. 5 above, but the processing flow is different. The processing procedures of I-DFT and F-DFT will be introduced in detail below.

According to the processing timing requirements for 2N-point DFT in ADSL system: the available frequency of DFT in ADSL system is 35.328MHZ, and the maximum 512-point DFT should be completed within 68/69*250us. If the FFT method of 2N-point DIF or DIT is adopted, NIOg ₂ ^2N times of disk operations are required, so 512-point FFT operations require 2304 times of butterfly operations.

According to the characteristics of the time-frequency domain data of the system, the invention adopts the Hermitian symmetric algorithm, which can reduce the calculation amount by one time. The formula of the Hermitian symmetric algorithm is shown in formula (1).

${\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

$<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; N</span>}}\underset{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}<span\; class="notranslate">\; \{</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2N"\; label="W"\; filenames="C0211218800132.png"\; state="\{\{state\}\}">W</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; N</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; \}</span><span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; nk</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Among them, x _c (n) is the time-domain data sequence, its real part is the even sequence x(2n) of the continuously input time-domain data, and the imaginary part is the odd sequence x(2n+1) of the continuously input time-domain data, where n=0, 1, 2, 3...N-1; X(k) is the frequency domain data sequence, where k=0, 1, 2, 3...N-1; N represents the total channel modulated number, equal to 256; X ^* indicates conjugate data; W _2N ^-k and W _N ^-nk are twiddle factors.

From formula (1), we can get the formulas (2) and (3) for converting X(k) into X′(k) when performing I-DFT processing in the modulation direction:

${\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2N"\; label="W"\; filenames="C0211218800132.png"\; state="\{\{state\}\}">W</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; N</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; \{</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2N"\; label="W"\; filenames="C0211218800132.png"\; state="\{\{state\}\}">W</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; N</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; \}</span>}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

In the modulation direction, I-DFT processing includes two steps, preprocessing and IFFT butterfly operation, that is, the frequency domain data is preprocessed first, and X(k) and X(N-k) are used to perform 128 butterfly operations to obtain X' (k), X′(N-k), and then perform 8-level (128*8 times) butterfly operation of 256-point IFFT on it to obtain the time-domain signal, so that the completion of 512-point I-DFT only requires 1152 butterfly operations It only needs 65us to complete the 512-point I-DFT, which is far lower than the timing requirements of the ADSL system.

FIG. 6 is the processing flowchart of the I-DFT device in FIG. 4 , which needs to go through 9 stages of operations in total, ie stage=1, 2, 3, 4, 5, 6, 7, 8, 9. The first level (stage=1) operation is to preprocess the 256 data X(k) in the frequency domain to complete the conversion from X(k) to X'(k), that is, to complete formula (2) and formula (3) in sequence 128 times of butterfly operations; from the second stage to the ninth stage (stage=2~9) is an eight-stage operation of 256-point IFFT, and the data is obtained after the preprocessing of X(k) to X'(k) conversion is completed X ₁ (m), enters the first stage of IFFT operation, obtains X ₂ (m) after 128 butterfly operations, enters the second stage of IFFT, enters the third stage, fourth stage and finally the eighth stage in turn, and obtains Time-domain data X(n), thus completing the modulation of 256 channels.

Similarly, when the demodulation direction is subjected to F-DFT processing, the formulas for converting X′(k) into X(k) can be obtained from formula (1) as shown in formulas (4) and (5):

$\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; \{</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span><span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span><span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2N"\; label="W"\; filenames="C0211218800132.png"\; state="\{\{state\}\}">W</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; N</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

$\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; \{</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span><span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{<span\; class="notranslate">\; \&prime;</span><span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2N"\; label="W"\; filenames="C0211218800132.png"\; state="\{\{state\}\}">W</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; N</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; \}</span>}^{<span\; class="notranslate">\; *</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

In this way, in the direction of demodulation, F-DFT processing also includes two steps, FFT butterfly operation and post-processing, that is, first perform 8-level (128*8 times) butterfly operation of 256-point FFT on the time domain data to obtain X' (k), X'(N-k), and then post-process them according to formula (4) and formula (5) to get X(k), X(N-k), so that only 1152 discs are needed to complete 512-point F-DFT It only takes 65us to complete the 512-point F-DFT, which meets the timing requirements of the ADSL system.

Fig. 7 is the processing flow diagram of the F-DFT device in Fig. 4, which also needs to go through 9 stages of operations in total, that is, stage=1, 2, 3, 4, 5, 6, 7, 8, 9, firstly through the 256-point FFT Eight-level operation (stage=1～8) converts time domain data X(n) into X′(k), that is, x ₈ (m) in the figure, and then performs post-processing to complete formula (4) and formula (5) The 128 butterfly operations convert 256 data X'(k) into frequency domain data X(k), thus completing the signal demodulation of 256 channels.

Fig. 8 is a schematic diagram illustrating the law of butterfly operation in the preprocessing process. The preprocessing process is to complete the operation of formula (2) and formula (3), because the values of X'(k) and X'(N-k) are calculated by taking X(k) and X(N-k) to form a butterfly operation unit , so when N=256, there are X(0) and X(256), X(1) and X(255), X(2) and X(254), ..., X(128) and X(128) A total of 129 butterfly operations, where X(0) and x(256) are zero-frequency sub-channels and Nyquist frequency sub-channels, their data and results are all 0, no butterfly operations are performed, so only 128 are required The values of X'(1)~X'(255) can be obtained by the butterfly operation.

The butterfly operation law in the post-processing process is the same as that in the pre-processing process, but the direction is opposite, that is, the arrow in Figure 8 is reversed. Then the post-processing is to complete the operation of formula (4) and formula (5), obtain X(k) from X'(k), and take X'(k) and X'(N-k) each time in the same way to form a butterfly operation unit, Get the values of X(k) and X(N-k), X'(0) and X(256), X'(1) and X(255), X'(2) and X(254),..., until X'(128) and X'(128) have a total of 129 butterfly operations, and the results of X'(0) and X'(256) are treated as 0, so only 128 butterfly operations are required to obtain X( 0) to X(255) values.

Fig. 9 takes 16-point IFFT as an example to illustrate the butterfly operation rule of each level of 256-point IFFT. For N=2 ^M points IFFT (FFT), needs to go through M stage butterfly operations altogether, and each stage has N/2 butterfly operation units again, the composition law of the butterfly operation units of each level is: inverse Read out the data in order to perform the first-level butterfly operation, wherein the reverse order refers to converting the data serial number k=[a:b] into k _reverse =[b:a], k=0, 1, 2, ..., 127. Write the result of each butterfly operation of the preprocessing into the corresponding address of the dual-port RAM 12 in reverse order, and each X'(2k) _inversion ) and X'((2k+1)) _inversion ) form a butterfly Operation unit, the obtained operation result is the value of x _l (2k) and x _l (2k+1), that is, after X(0) and X(128), X(64) and X(192),...,X (127) and X(255) have a total of 128 butterfly operations, and the results of each butterfly operation are stored in the corresponding addresses of the dual-port RAM12 in sequence; the second stage also has 128 butterfly operation units, which are divided into 64 groups , each group has two butterfly units: x ₁ (4k) and x ₁ (4k+2) and x ₁ (4k+1) and x ₁ (4k+3), where k=0, 1, 2, ..., 63, get the results x ₂ (4k) and x ₂ (4k+2) and x ₂ (4k+1) and x ₂ (4k+3) of the butterfly operation respectively, the results of each butterfly operation are respectively Stored in the corresponding address of the dual-port RAM12 in order; the third stage also has 128 butterfly operation units, which are divided into 32 groups, and each group has 4 butterfly operation units: x ₂ (16k) and x ₂ (16k+ 4), x ₂ (16k+1) and x ₂ (16k+5), x ₂ (16k+2) and x ₂ (16k+6), x ₂ (16k+3) and x ₂ (16k+7) , where k=0, 1, 2, ..., 31, the results of butterfly operation x ₃ (16k) and x ₃ (16k+4), x ₃ (16+1) and x ₃ (16k+5 ), x ₃ (16k+2) and x ₃ (16k+6), x ₃ (16k+3) and x ₃ (16k+7), the results of each butterfly operation are stored in the dual-port RAM12 in sequence In the corresponding address; and so on, until the 128 butterfly operation units of the eighth stage have only one group of 128 butterfly operation units, i.e. x ₈ (k) and x ₈ (k+128), wherein k=0, 1, 2 , ..., 127, obtain the time-domain data x _c (n) and x _c (n+128) after the butterfly operation respectively, wherein n=k, store the result of the butterfly operation into the cyclic prefix RAM respectively in order in the corresponding address.

The butterfly operation law of each level of 256-point FFT is the same as the butterfly operation law of each level of 256-point IFFT, but because the processing flow of F-DFT and I-DFT is different, the first-level read data of FFT and the final eighth-level Level write data is different. The first stage operation of FFT is to read data in reverse order from the decyclic prefix RAM, and each x _c ((2n) _inversion ) and x _c ((2n+1) _inverse ) form a butterfly operation unit, and the obtained operation result is the value of x ₁ (2k) and x ₁ (2k+1), that is, after x _c (0) and x _c (128), x _c (64) and x _c (192), ..., x _c (127 ) and x _c (255) a total of 128 butterfly operations; the eighth stage operation of FFT is to store the results in dual-port RAM12, the butterfly operation results x ₈ (k) and x ₈ (k+128) (where k =0, 1, 2, ..., 127) are data X' (k) and X' (k+128), and the result of each butterfly operation is stored in the corresponding address of dual-port RAM12 respectively, to be Level one post-processing. Operations at other levels are the same as IFFT operations.

Fig. 10 has provided the structural diagram of butterfly computing module 13, comprises selector 301, selector 302 and butterfly computing unit 300, and selector 301 receives the data from dual-port RAM A or dual-port RAM 12, and outputs to butterfly The twiddle factor in the twiddle factor module 14 is also sent to the butterfly operation unit 300 for calculation, and the calculation result is output to the dual-port RAM C or the dual-port RAM 12 through the selector 302 . When starting the first stage (stage=1) operation of I-DFT or F-DFT, read data from dual-port RAM A (gain adjustment RAM or decyclic prefix RAM), while other stages (stage=2～ 9) The operation reads data from the dual-port RAM 12, and outputs _Xl (m1) and _Xl (m2) through the one-to-two selector 301, wherein _Xl (m1) and _Xl (m2) represent the first level The data obtained by the operation of the butterfly operation unit 300 obtains the operation results X _l+1 (m1) and X _l+1 (m2) of the first stage l+1 through the operation of the butterfly operation unit 300, and the result passes through a two-choice selector 302 to store the data in In the dual-port RAM12 or dual-port RAM C, the operation results of each stage when the stage number is less than 9 are stored in the dual-port RAM12, and the operation results with the stage number = 9 are stored in the dual-port RAM C (with cyclic prefix RAM or domain equalization RAM), where m1 and m2 refer to the serial numbers of the two input data of the butterfly operation unit of each stage.

Fig. 11 is a structural diagram of the butterfly operation unit 300 in Fig. 10, the butterfly operation unit 300 includes a conjugator 3001, three selectors 3003, 3004, 3005, two adders 3007, 3008, and two subtractors 3006, 3009 and a complex multiplier 3002. Selector 301 _outputs two data X _l (m1) and X _l (m2), wherein X _l (m1) enters adder 3007 and subtractor 3009 respectively; X _l (m2) enters the selector 3003. When stage=1, the selector 3003 outputs the conjugate data of X ₁ (m2). When stage>1, the selector 3003 outputs X _l (m2). Data X ₁ (m1) and the output data of the selector 3003 perform complex addition and subtraction in the adder 3007 and the subtractor 3009 at the same time, and the difference output by the subtractor 3009 is multiplied by the corresponding twiddle factor in the complex multiplier 3002, The resulting complex product is then multiplied with the output of the adder 3007 to perform complex addition and subtraction operations in the adder 3008 and the subtractor 3006 respectively, and the resulting sum and the result of the adder 3007 are sent to the selector 3004, and the resulting difference is multiplied with the complex number The result of the selector 3002 is sent to the selector 3005. When stage=1, the selector 3005 output X ₁₊₁ (ml) is equal to the result of the adder 3008, and the selector 3005 output X ₁₊₁ (m2) is equal to the subtractor 3006 When stage>1, the selector 3004 outputs X _l+1 (m1) which is equal to the result of the adder 3007, and the selector 3005 outputs X _l+1 (m2) which is equal to the result of the complex multiplier 3002.

Claims (5)

1. a discrete Fourier transform device in an asymmetric digital subscriber loop system, is characterized in that, comprises 1 dual-port RAM (12), twiddle factor module (14), timing control module (10), read-write address Produce module (11) and butterfly computing module (13); The dual-port RAM (12): is controlled by the read-write address generation module (11), and reads and writes the intermediate operation data of the butterfly operation module (13); The twiddle factor module (14): used to store the twiddle factor W _2N ^±k required in the butterfly operation process, which is read by the read-write address generation module (11) and output to the butterfly operation module ( 13); The timing control module (10): used to control the reading and writing of the reading and writing address generation module (11), and control the working timing of each module; The read-write address generation module (11): controlled by the timing control module (10), reads the data in the dual-port RAM (12) and the external dual-port RAM A, and the twiddle factor module ( The twiddle factor in 14) is given to the butterfly operation module (13), and the control calculation result is written in the dual-port RAM (12) and the external dual-port RAM C; The butterfly operation module (13): used for performing butterfly calculations based on the data and the twiddle factor using the Hermitian symmetry algorithm, and the obtained calculation results are written into the said read-write address generation module (11) under the control of the In the above-mentioned dual-port RAM (12) and the external dual-port RAM C. 2. the discrete Fourier transform device in the asymmetric digital subscriber loop system according to claim 1, is characterized in that, described butterfly operation module (13) also comprises selector (301), selector (302) And butterfly operation unit (300), selector (301) receives the data from dual-port RAM A or dual-port RAM (12), output to butterfly operation unit (300), the twiddle factor in the twiddle factor module (14) Also sent to the butterfly operation unit (300) for calculation, the calculation result is output to dual-port RAM C or dual-port RAM (12) through the selector (302). 3. the discrete Fourier transform device in the asymmetric digital subscriber loop system according to claim 2, is characterized in that, described butterfly operation unit (300) comprises 1 conjugator (3001), 3 select devices (3003, 3004, 3005), 2 adders (3007, 3008), 2 subtractors (3006, 3009) and 1 complex multiplier (3002); the selector (301) outputs two data X _l ( m1) and X _l (m2), wherein the data X _l (m1) enters the adder (3007) and the subtractor (3009) respectively, and the data X _l (m2) passes through the conjugator (3001) and the data X _l (m2) enters in selector (3003); The output data of data X ₁ (m1) and selector (3003) carries out complex addition and subtraction in adder (3007) and subtractor (3009), and subtractor (3009) ) output difference and the corresponding twiddle factor are multiplied in the complex multiplier (3002), and the complex multiplication of the gained is carried out in the adder (3008) and the subtractor (3006) respectively with the output of the adder (3007). In the addition and subtraction operation, the obtained sum and the result of the adder (3007) are sent to the selector (3004), and the obtained difference and the result of the complex multiplier (3002) are sent to the selector (3005). 4. the discrete Fourier transform device in the asymmetrical digital subscriber loop system according to claim 2, is characterized in that, described selector (301,302) is all two selectors, according to operation series stage control its output; When carrying out the first stage calculation of series number stage=1, selector (301) outputs the data in the dual-port RAM A, and other all levels of operations, when promptly series number stage=2～9, selector (301) outputs Data in the dual-port RAM (12); When the series stage＜9, the selector (302) outputs the calculation result in the dual-port RAM (12), and when the series stage=9, the selector (302) stores the calculation result in the dual-port RAM C. 5. the discrete Fourier transform device in the asymmetrical digital subscriber loop system according to claim 3, is characterized in that, described selector (3003,3004,3005) is all two selectors, according to the operation stage The number of stages controls its output results; When the series stage=1, the selector (3003) outputs the conjugate data of X _l (m2), and when stage>1, the selector (3003) outputs the data X _l (m2); When stage=1, the selector (3004) output X ₁₊₁ (m1) was equal to the result of the adder (3008), and the selector (3005) output X ₁₊₁ (m2) was equal to the result of the subtractor (3006); When stage>1, the selector (3004) output X _l+1 (m1) is equal to the result of the adder (3007), and the selector (3005) outputs X _l+1 (m2) is equal to the result of the complex multiplier (3002) .

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